Realization of cascadable electro-optical hybrid RS flip flop using hybrid NAND gates

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1 ealization of cascadable electro-optical hybrid flip flop using hybrid NAND gates Ekkurthi.reenivasa ao E.C.E Department,Vasavi College of Engineering, Hyderabad, M.atyam, Professor of E.C.E (etd.), IIIT, Hyderabad, K.Lal Kishore, Professor of E.C.E (etd.), J.N.T.University, Hyderabad, Abstract - An Electro-Optical Hybrid Flip Flop is defined as a sequential circuit which accept electrical and/or optical signals and produces both electrical and optical signals. The basic building blocks for developing large and complex sequential circuits and systems are flip flops. This paper reports the feasibility of developing cascadable electro-optical hybrid flip flop. The realization of the basic hybrid flip flop using hybrid NAND gates has been discussed and its functionality is demonstrated. The circuit is found to be working satisfactorily. Key words: Hybrid Circuits, Hybrid Flip Flops, Hybrid Logic Gates, Optoelectronics, Hybrid Optoelectronics, Electro-Optical Logic Gates, Electro-Optical Hybrid Flip Flops. I. INTODUCTION Flip flops are the basic building blocks for developing large and complex sequential circuits and systems. everal research groups have reported different types of optical flip flops. Chang-Hee Lee et al realized an optical flip flop [1] with a very simple structure based on optoelectronic feedback using discrete components. T. Chino et al reported an integrated optoelectronic flip flop [2] based on optically coupled inverters. K. Matsuda et al reported optoelectronic bitable switches and latching device [3-4]. X.An et al demonstrated optical set-reset memory pixel [5]. The need for optically controlled bistable, astable and tristable devices is amply explained by.noda et al from the point of optical computing [6]. M.K.avishankar and M.atyam reported a bitable multivibrator [7] which can be triggered optically/electrically. In general, latches and flip flops are realized using universal logic gates like NO/NAND. Most of the research groups have reported latches/flip flops, which responds to only one stimulus namely either electrical or optical signals and most of them are not cascadable. This paper presents the feasibility of developing cascadable electro-optical hybrid flip flop using universal hybrid NAND gates. Universal electro-optical hybrid logic gates [8] have already been published by the authors of this paper. The electro-optical hybrid flip flop presented in this paper is intended to demonstrate the functionality of the flip flop. In the first instance, the definition of electrical and optical logic levels of hybrid NAND gate are presented and thereafter, realization of hybrid flip flop is discussed. II. DEFINITION OF ELECTICAL AND OPTICAL LOGIC LEVEL The basic hybrid flip flop has been realized using well known concept i.e., by cross coupling two hybrid NAND gates and the coupling can be either electrical or optical in nature. As the flip flops are used in building large and complex sequential circuits and systems, it is necessary for each flip flop to have the capacity to drive the output stage(s) in the system. It means that they must be cascadable. The requirement for achieving cascadability is that the input logic levels and the output logic levels of the flip flop should be almost the same or at least they should be within tolerable logic levels, so that there is no degradation in the cascaded system. Electrical and optical logic levels are defined as per the noise margin criteria for digital logic circuits [9] using the universal electro-optical hybrid NAND gate and are explained below. Ideally, electrical LOW input/output logic level is defined as 0V and 5V as electrical HIGH input/output logic level. The tolerable input voltages V IL and V IH are measured using the points at which the slope of the Voltage Transfer Characteristics (VTC) of hybrid NAND gate shown in Fig.1 equals 1, where, V IL is the maximum IN : X Vol. 2 No. 3 Aug-Oct

2 input voltage that will be recognized as tolerable LOW input logic level and V IH is the minimum input voltage that will be recognized as tolerable electrical input logic level HIGH. Voltages below V IL are reliably recognized as electrical logic level LOW at the input of a logic gate, and voltages above V IH are recognized reliably as electrical logic level HIGH at the input. Voltages corresponding to the region between V IL and V IH do not represent valid logic input levels and generate logically undefined output voltages. The voltages labeled as V OL and V OH represent the tolerable electrical output voltages at the 1 slope points corresponding to input levels of V IH and V IL respectively. Fig.1. Voltage transfer characteristics of hybrid NAND gate. There is no access to measure the light intensity of Light Emitting Diode (LED) in the optocoupler. Therefore, current flowing through the LED has been used to represent the optical logic. A measure of light intensity can be obtained by noting the current flowing through the LED from the characteristics. From the transfer characteristics of optocoupler, it is found that when a forward current flowing through LED is 0mA, there is no light output from the LED and in this case the phototransistor is OFF. When a forward current flowing through LED is 10mA, the LED produces sufficient high light output and in this case the phototransistor is ON. Therefore ideally, optical LOW input/output logic level is defined as 0mA and 10mA as optical HIGH input/output logic level. imilarly, tolerable optical logic levels are defined in terms of currents from the Current Transfer Characteristics (CTC) of hybrid NAND gate shown in Fig.2. The tolerable input currents I IL and I IH are measured using the points at which the slope of the CTC equals 1, where, I IL is the maximum input current flowing through source LED that will be recognized as tolerable optical input logic level LOW and I IH is the minimum input current flowing through source LED that will be recognized as tolerable optical input logic HIGH. Currents below I IL are reliably recognized as tolerable optical logic LOW at the input of a logic gate, and currents above I IH are recognized reliably as optical logic level HIGH at the input. Currents corresponding to the region between I IL and I IH do not represent valid optical input logic levels and generate logically undefined output currents. The tolerable currents labeled as I OL and I OH represent the gate output currents at the 1 slope points corresponding to optical input logic levels of I IH and I IL respectively. The summary of definition of electrical and optical logic levels of hybrid NAND gate are given in Table.1. IN : X Vol. 2 No. 3 Aug-Oct

3 Fig.2. Current transfer characteristics of hybrid NAND gate. Table.1 Definition of electrical and optical logic levels of hybrid NAND gate Ideal case electrical logic levels (V) Input LOW Input HIGH Output LOW Output HIGH Tolerable electrical logic levels (V) V IL V IH V OL V OH Ideal case optical logic levels (ma) Input LOW Input HIGH Output LOW Output HIGH Tolerable optical logic levels (ma) I IL I IH I OL I OH III. EALIZATION OF HYBID FLIP FLOP The basic hybrid flip flop has been realized using well known concept i.e., by cross coupling two hybrid NAND gates [8] and the coupling can be either electrical or optical in nature. The circuit diagram of electrooptical hybrid flip flop using universal hybrid NAND gates is shown in Fig.3. The first hybrid NAND gate consists of two phototransistors (PT 1 and PT 2 ), which are connected in series. The load of NAND gate consists of a Load LED 1 to provide optical output and a series resistor L1 across which the electrical output is taken. IN : X Vol. 2 No. 3 Aug-Oct

4 imilarly, the second hybrid NAND gate consists of two phototransistors (PT 3 and PT 4 ), which are connected in series. The load consists of a Load LED 2 to provide optical output and a series resistor L2 across which the electrical output is taken. The phototransistors are used as switches, which can be operated with either electrical or optical input signals. To realize the electro-optical hybrid flip flop, Light Emitting Diode (LED) which can give optical output and phototransistor which can respond to electrical/optical signals are used. ince alignment of light source and photo detectors are involved in realizing hybrid flip flop, it is proposed to use optocouplers as they are available with perfectly aligned LED and the phototransistor in a single IC package. Hence, optocouplers (4N32) have been used for implementing and verifying the functionality of hybrid flip flop. The current source is implemented using BC558A transistor. + V EE + V EE Current ource 1 Current ource 2 87KΩ I = 10mA 87KΩ I = 10mA + V D1 + V D2 I i1 386Ω Load LED 1 Light Output 1 I i2 386Ω Load LED 2 Light Output 2 ource LED 1 PT 1 I o1 V o1 Q ource LED 2 PT 3 I o2 V o2 Q V i1 L1 500Ω V i2 L2 500Ω PT 2 PT 4 Fig. 3 Circuit diagram of hybrid flip flop using hybrid NAND gates. The flip flop has two inputs, and the inputs are generally designated "" and "" for "et" and "eset" respectively. The inputs can be either electrical inputs or optical inputs. The input is used to set the flip flop. When the flip flop is set, it is said to store a binary bit 1. The input resets the flip flop and when it is reset, it is said to store a binary bit 0. The flip flop has two outputs, normal output (Q) and complement output (Q) which are always in complementary state relative to one another. If the logic level of the Q output is HIGH, the flip flop is set and if it is LOW, it is reset. The hybrid flip flop produces both electrical and optical outputs. In this circuit, inputs for the hybrid flip flop are either electrical inputs (V i1 and V i2 ) and/or optical inputs I i1 and I i2 (current through source LED s). V o1 /I o1 is the normal electrical/optical output (Q) and V o2 /I o2 is complement electrical/optical output (Q) of the hybrid flip flop. The dotted lines in the circuit diagram indicates the feed back path between the NAND gates which is either electrical or optical. In this circuit, the electrical feed back is used. IV. PINCIPLE OF OPEATION OF HYBID FLIP FLOP The operation of hybrid flip flop can be explained by considering the operating modes of the four phototransistors (PT 1, PT 2, PT 3 and PT 4 ) shown in Fig.3. If both inputs of the hybrid flip flop are equal to electrical and/or optical logic LOW, PT 1 of first NAND gate and PT 3 of second NAND gate does not conduct. Hence, most of the current from the current source 1 flows through Load LED 1 and produces electrical logic IN : X Vol. 2 No. 3 Aug-Oct

5 HIGH and optical logic HIGH as normal output (Q). imilarly, most of the current from current source 2 flows through Load LED 2 producing electrical HIGH and optical HIGH as complementary output ( Q ). Thus, the application of electrical and/or optical logic LOW to both of the inputs will produce electrical logic HIGH and optical logic HIGH as normal (Q) and complementary ( Q ) outputs. This contradicts the assumption that Q and Q must be complementary. This condition where both the inputs of flip flop are electrical/optical logic LOW is Not Allowed (NA). When input is electrical/optical logic LOW, and input is electrical/optical logic HIGH, the PT 1 of first NAND gate is turned OFF and most of the current from the current source 1 flows through the Load LED 1. Hence, the hybrid flip flop produces optical HIGH and electrical HIGH as normal output (Q). ince, this normal output (Q) is fed back to the base input of PT 4 of second NAND gate, PT 3 and PT 4 are turned ON and most of the current from the current source 2 flows through them and very negligible amount of current flows through Load LED 2. Hence, hybrid flip flop produces optical logic LOW and electrical logic LOW as complement output ( Q ). Thus, when input is electrical/optical logic LOW and input is either electrical/optical logic HIGH, the hybrid flip flop produces electrical logic HIGH and optical logic HIGH as normal output (Q) and electrical LOW and optical LOW as complementary output ( Q ). When the input is electrical/optical logic HIGH, and the input is electrical/optical logic LOW, the PT 3 of second NAND gate is turned OFF and most of the current from the current source 2 flows through the Load LED 2. Hence, the hybrid flip flop produces optical HIGH and electrical HIGH as complement output ( Q ). ince, this complement output ( Q ) is fed back to the base input of PT 2 of first NAND gate, PT 1 and PT 2 will conduct and most of the current from the current source 1 flows through them and very negligible amount of current flows through Load LED 1. Hence, the hybrid flip flop produces optical logic LOW and electrical logic LOW as normal output (Q). Thus, when input is either electrical or optical logic HIGH and input is either electrical or optical logic LOW, the hybrid flip flop produces electrical logic LOW and optical logic LOW as normal output (Q) and electrical HIGH and optical HIGH as complementary output ( Q ). If both the inputs of the hybrid latch are equal to electrical and/or optical logic HIGH, the output state of hybrid latch does not change. V. EXPEIMENTAL EULT In order to verify the functionality, the hybrid flip flop is implemented with a current source of 10mA. The collector of BC558A transistor behaves as current source, when connected to a power supply. To generate 10mA of current through the current source, a power supply supply voltage (V EE ) of 6.2V with a base resistance of 87KΩ is used. The voltage drop across the source LED/Load LED is around 1.15V, when current of 10mA flowing through the LED. The value of current limiting resistor is selected as 386Ω to provide an input current of 10mA through source LED. To produce electrical logic HIGH corresponding to a voltage of 5V, a series load resistor of value 500Ω is connected to the Load LED. This circuit thus satisfies the conditions that input logic levels and output logic levels are almost the same and can be used for building cascadable hybrid sequential circuits and systems. To verify the functionality of hybrid flip flop shown in Fig.3, the experiment is performed for different electrical and/or optical input logic level values. The experimental results of hybrid flip flop realized using NAND gates is shown in Table.2. The experimental results of hybrid flip flop using hybrid NAND gates are discussed in the following section. IN : X Vol. 2 No. 3 Aug-Oct

6 Table.2 Experimental results of hybrid flip flop Electrical inputs V i1 (V) V i2 (V) Electrical output V o (V) V o1 (V) V o2 (V) Optical output I o (ma) I o1 (ma) I o2 (ma) Q n Q n Q n Q n Optical inputs (Current through source LEDs) Electrical output V o (V) Optical output I o (ma) I i1 (ma) I i2 (ma) V o1 (V) V o2 (V) Qn+1 I o1 (ma) I o2 (ma) Q n Q n Q n Q n Hybrid inputs (Optical and Electrical inputs) Electrical output V o (V) Optical output I o (ma) I i1 (ma) V i2 (V) V o1 (V) V o2 (V) Qn+1 I o1 (ma) I o2 (ma) Q n Q n Q n Q n VI. DICUION OF EXPEIMENTAL EULT If both the inputs are equal to electrical logic LOW (0V), the hybrid flip flop produces electrical output of 4.8V and optical output of 9.6mA for both normal ( ) and complement ( ) outputs. This contradicts our assumption that and must be complementary. This condition where both the inputs of hybrid flip flop are electrical logic LOW is Not Allowed (NA). When input is electrical logic LOW (0V) and input is electrical logic HIGH (5V), the hybrid flip flop produces electrical output (V o1 ) of 4.8V and optical output (I o1 ) of 9.6mA as normal output (Q n ). In this case, the hybrid flip flop is said to be in set state. When input is electrical logic HIGH (5V) and input is electrical logic LOW (0V), the hybrid flip flop produces electrical output (V o1 ) of 0V and optical output (I o1 ) of 0mA as normal output (Q n ). In this case, the hybrid flip flop is said to be reset. If both inputs are equal to electrical logic HIGH (5V), the hybrid flip flop does not change output state. imilar is the case with different combinations of optical input logic level values or hybrid input logic level values as shown in Table2. Thus, the functionality of hybrid flip flop has been demonstrated. VII. CONCLUION The basic building block for a sequential circuit is a flip flop. This paper demonstrated the cascadable electro-optical hybrid flip flop which accept either electrical or optical signals and produce both electrical and optical signals. The circuit is implemented using universal hybrid NAND logic gates. The hybrid flip flop may be used to construct large and complex hierarchical hybrid memory circuits like registers and counters. The electro-optical hybrid logic gates have been reported earlier and hybrid flip flop in this paper. These hybrid logic circuits may be used in building cascadable, hierarchical circuits and systems as the input and output logic levels are almost the same and within the tolerable logic levels. It is felt that this effort would pave the way for developing new branch of Hybrid Optoelectronic Circuits and ystems which will involve both electrical and optical signals and have advantages of both the systems. IN : X Vol. 2 No. 3 Aug-Oct

7 EFEENCE [1] Chang-Hee Lee et al, Optical flip flop using discrete components, Applied Optics, 25, pp 14, [2] T. Chino et al., Novel Integrated optoelectronic flip flop based on optically coupled inverters, Elec. Letters, 28, pp7, [3] K. Matsuda et al., Integration of optoelectronic bistable switches with a function of optical erasing, IEEE Trans. Electron Dev., 11, pp ,1990. [4] K. Matsuda et al., Dynamic set and reset optoelectronic latching device, IEEE Photon. Tech. Lett., 4, pp , [5] X. An et al., Highly compact integrated optical set-reset memory pixels for optical processing arrays, IEEE photonics Tech. Lett. 5, pp 5, [6]. Noda et al., Light controlled optical bistable device by bistable laser diode and hetero junction photo transistors, Electron. Letters., 26(14), pp , [7] M.K. avishankar and M. atyam., Optically/Electrically (ymmetrically) Triggerable bistable multivibrator, IEEE Trans. On circuits and systems-1: Fundamental theory and applications, 43(7), pp , [8] Ekkurthi reenivasa ao, M. atyam, K. LalKishore, Universal Electro-optical hybrid logic gates emiconductor Physics, Quantum Electronics & Optoelectronics, 11(1), pp , [9] J.. Houser, Noise margin criteria for digital logic circuits, IEEE Trans. on Education, vol. 36, no. 4, pp , IN : X Vol. 2 No. 3 Aug-Oct

HIGH LOW Astable multivibrators HIGH LOW 1:1

HIGH LOW Astable multivibrators HIGH LOW 1:1 1. Multivibrators A multivibrator circuit oscillates between a HIGH state and a LOW state producing a continuous output. Astable multivibrators generally have an even 50% duty cycle, that is that 50% of