MODULE TITLE : OPERATIONAL AMPLIFIERS TOPIC TITLE : OSCILLATORS LESSON 2 : RELAXATION OSCILLATORS

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1 MODULE ILE : OPEAIONAL AMPLIFIES OPIC ILE : OSCILLAOS LESSON : ELAXAION OSCILLAOS OA - - eesside University

2 INODUCION he '555' timer is a very popular and 'user friendly' I.C. used to produce 'single shot' or continuous pulse waveforms. he timer comes in both CMOS and bipolar versions; we concentrate upon the bipolar version although the two types of device are functionally the same. YOU AIMS Upon completing this lesson, you should be able to: design a '555' type timer circuit to produce a monostable or astable waveform to a given specification. SUDY ADVICE eference is made to the S flip-flop or bistable circuit of FIGUE. he particular version of the circuit shown uses NAND gates: note that for this gate, when any input is at logic the output is at logic. eesside University

3 A B F S Q A B F NAND flip-flop NAND gate and truth table FIG. he action of the flip-flop is as follows: Whenever S is at '' the output Q will be at ''; for this reason, this input is called the set input. When is at '' and 'S' is at '', there will be two ''s at the input of the upper NAND gate. Consequently, Q will be at ''; the output of the flip-flop has been reset by. If both S and are at '', the output Q will remain stable. For example, if Q is at '' then the lower NAND gate will have two ''s at its input, so its output will be ''. his '' is fed back into the upper NAND gate, holding its output at ''. eesside University

4 he truth table for the S flip-flop is: S Q NC (NC no change) A circuit such as the S flip-flop which can rest in one of two stable states is called a bistable. We will discover shortly two other circuits, the monostable which has only one stable (or resting) state and the astable which has no stable states but continually switches from one state to the other to produce a rectangular waveform on its output. HE 555 IME he '555' timer is a popular I.C. frequently used as a monostable or astable multivibrator. hese circuits are described shortly but first let's study the functional block diagram of FIGUE. eesside University

5 4 eset hreshold Control V x S Q A Output V y rigger Discharge GND FIG. (a) Gnd 8 rig 7 Disch Out 6 hres eset 4 5 Control op view FIG. (b) eesside University

6 5 Essentially, the timer can be seen to consist of two op-amp comparators used to drive an S 'flip-flop'. he flip-flop has a third ESE input which overrides the S and inputs. When ESE is low, Q is forced low. he output Q of the flip-flop is buffered by the amplifier A before being presented to the 'outside world'. Now focus your attention on the inputs to the comparators. hree equalvalued resistors form a potential divider chain to the inverting input of the upper comparator and the non-inverting input of the lower comparator. Express the voltages V x and V y in terms of. Vx VCC and Vy VCC So, if the IGGE input is below /, the output of the lower comparator is high. If the HESHOLD input is below /, the output of the upper comparator is low. Armed with these observations, we can complete a 'truth table' for the timer, so relating its output state to the state of its inputs. eesside University

7 6 Complete the table below. o set you off in the right direction, the first line has been completed. (emember that ESE overrides the S and inputs and referring back to the truth table in the Study Advice may well help!) rig S hres eset Q Out Discharge on/off? < V < V off < V > V > V < V > V > V X X V In the completed table below, NC means 'no change'. By this we mean that the output will remain as it was before the input condition S was applied. he 'X' symbol in an input column means we 'don't care' what the input is, the output will remain the same if it is a '' or a ''. his condition occurs when ESE is used to override the other inputs. eesside University

8 7 rig S hres eset Q Out Discharge on/off? < V < V off < V > V off > V < V NC NC NC > V > V V on X X X X V V on APPLICAION EXAMPLES he action of the I.C. is best understood by a couple of applications. We shall first investigate its use as a monostable multivibrator. he Monostable FIGUE (a) shows that the '555' timer can be used as a monostable multivibrator by the addition of just two components, a resistor and capacitor. hese are connected across the power supply, their junction being connected to the HESHOLD and DISCHAGE terminals of the timer. eesside University

9 8 eset hreshold Control v S Q A Output C rigger Step input Discharge GND FIG. (a) eesside University

10 9 rigger V t hreshold V V t v exp t C t Output V t FIG. (b) Before the circuit can be activated, the timer will have to be reset so that its output is at V and the IGGE voltage will be held high (above / ). In this reset condition, the discharge transistor will be on, so keeping the capacitor discharged. Virtually all the supply voltage will be dropped across the resistor. A pulse is now applied to the IGGE. In the timing diagram of FIGUE (b), this has been represented as a rather sloppy pulse with slow rise and fall times, just to make the point that nothing will happen until the IGGE voltage falls below /. When this occurs the S flip-flop will be set and the discharge transistor will be turned off. he capacitor can now charge and the voltage v will rise according to the equation: v V CC t exp C eesside University

11 When v exceeds / the S flip-flop is reset, causing the output to fall to volts and the discharge transistor to turn on again, so rapidly discharging the capacitor. A pulse of predetermined duration will have been produced at the output. he duration of is controlled by the time constant C and is independent of the duration of the input pulse. Pulse Duration he output of the timer remains high for as long as the HESHOLD voltage remains below /, that is until: V CC V CC t exp C When this condition is satisfied, t and we can write: exp C or exp C aking natural logs: ln. C C. C In the monostable mode, the external resistor should have a minimum value of kω. eesside University

12 he Astable FIGUE 4(a) shows the circuit of the '555' used as an astable. Here, three extra components are required two resistors and a capacitor. Note that the capacitor charges through both resistors but discharges through only one. Also, observe that the HESHOLD and IGGE inputs are tied together so that the 'truth table' for the timer is reduced to: rig S hres eset Q Out Discharge on/off? < V < V off > V < V NC NC NC > V > V V on eesside University

13 eset hreshold Control v S Q Output C rigger Discharge GND FIG. 4(a) eesside University

14 t t t V v t H L Output V t FIG. 4(b) When the circuit is first switched on, the capacitor will be discharged and the voltage v will be at zero volts. What will be the output state of the timer at switch on? eesside University

15 4 We will be operating on the first line of the abbreviated 'truth table', so the S flip-flop is set and the output is high ( ). he capacitor will now begin to charge and v will rise according to the equation: v V CC exp t C ( ) No change in output will occur as v rises between one third and two thirds of, but when it exceeds /, the upper comparator will cause the flipflop to reset; the output of the timer falls to zero volts and the discharge transistor is switched on. he capacitor now discharges through and v falls according to the equation: v V t exp C CC Again, no change in output occurs between two thirds and one third but when v falls below / the lower comparator sets the flip-flop and the timer's output goes high ( ) and the discharge transistor is turned off. he cycle now repeats itself so that a rectangular waveform is produced at the output. he iming Cycle he timing diagram of FIGUE 4(b) shows that the capacitor charges through the resistors and from / to / ; during this period, the timer's output is high. he duration of the pulse H is given by t t where: eesside University

16 5 t VCC exp ( ) C yielding t ( ) C ln and VCC t exp ( ) C yielding t ( ) C ln Now, ln. ln 4. and the pulse is high, is given by: so that H, the period for which t t C. 4. H 69. C H ( ) ( ) ( ) he capacitor discharges through from / to /. Determine the period L, for which the pulse is low. eesside University

17 6 t t L Now V CC V CC ( t ) exp C so that t C ln and V CC V CC ( t ) exp C so that t C ln hus L t t C ln ln. C L 69 he period of the output waveform is: H L and the frequency of the astable is: f When used as an astable, manufacturers specify that should be in the range of kω to kω. he astable has a maximum frequency of oscillation of about 5 khz. eesside University

18 7 he Control Input We have seen how the internal potential divider network of the timer sets the HESHOLD and IGGE voltage levels to / and / respectively. o give the timer greater versatility, a CONOL input has been included which allows these levels to be adjusted to above or below their nominal level. his is done by applying an external voltage to the control input. If the control input is unused, manufacturers recommend that it should be tied to the GND rail via a. μf capacitor. he timer, in its astable mode, can be used as a voltage-controlled oscillator (VCO) by means of the CONOL input. When used as a VCO, the frequency of the astable is controlled by the voltage on the control input. FIGUE 5 shows the effect of applying a sinusoidal voltage to the control input of a '555' astable. VCOs have many applications, one of them being the phase-locked loop. Control t Output t FIG. 5 eesside University

19 8 SELF-ASSESSMEN QUESIONS. FIGUE 6(a) shows a '555' timer used as a monostable. Note that the ESE is tied to the positive supply. he CONOL input is tied to earth via a capacitor to minimize the effects of noise. FIGUE 6(b) shows waveforms produced by the circuit when first 'powered-up' and then triggered. (a) Explain the shape of the waveforms. (b) If the pulse width is to be.5 seconds, calculate a suitable value for. 9V eset Cont hres Disch Out v O v rig GND v C C. μf FIG. 6(a) eesside University

20 9 "Power-up" v v O uncertain level v C ime FIG. 6(b). (a) he duty cycle D of a rectangular waveform (like that of FIGUE H 4(b) is defined as D %. Show that the duty cycle for the '555' astable timer (FIGUE 4(a)) is D % (b) An astable '555' timer circuit is required to produce a rectangular wave of frequency khz and 75% duty cycle. Determine the values of the timing resistors if a. μf timing capacitor is used. eesside University

21 ANSWES O SELF-ASSESSMEN QUESIONS. (a) After 'power-up' the capacitor will start to charge up to. It will be uncertain what the output voltage v o will be as the ESE has not been asserted. But, assuming that the trigger input is high (> / ) then, when the threshold voltage exceeds /, the output of the timer is forced low (line 4 of the 'truth table' given in the lesson) and the discharge transistor turns on. he capacitor will now discharge and the threshold input will be made low (line ). When a negative going pulse on the trigger input takes it below /, the output goes high and the discharge transistor is turned off. he capacitor can now charge and its voltage v C rises exponentially as shown in the lower waveform. When v C exceeds /, the output goes low and the discharge transistor is turned on again causing the capacitor to rapidly discharge. he monostable is now ready to receive another trigger pulse. (b) We must use the relation. C where C. μf. hus. C M Ω or 4.7 M Ω to the nearest preferred value.. (a) 69. C and 69. C H ( ) L H L ( ) 6.9 C 69. C ( ) 69. C eesside University

22 herefore D 69. ( ) ( ) C 69. C % D % (b) 4 4 seconds. As D H %, then H s and L 5. 5 s. Using L.69 C, we can find the required value of : L.69C Ω We can now find from D % ( ) yielding Ω Selecting resistors to the nearest preferred value gives and.6 kω. 7.5 kω eesside University

23 SUMMAY In its monostable mode, the '555' timer can produce time delays of up to several hours duration. Only a single external resistor and capacitor are required. he duration of the output pulse is:. C When used as an astable, the timer requires two external resistors and one capacitor. he values of these components independently control the frequency and duty cycle of the output waveform. he 'output high' duration of the waveform is: H.69 ( ) C and the 'output low' duration is: L.69 C eesside University

Multivibrators. Department of Electrical & Electronics Engineering, Amrita School of Engineering

Multivibrators. Department of Electrical & Electronics Engineering, Amrita School of Engineering Multivibrators Multivibrators Multivibrator is an electronic circuit that generates square, rectangular, pulse waveforms. Also called as nonlinear oscillators or function generators. Multivibrator is basically