Government Polytechnic Muzaffarpur Name of the Lab: Applied Electronics Lab

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1 Government Polytechnic Muzaffarpur Name of the Lab: Applied Electronics Lab Subject Code: Experiment-1 Aim: To obtain the characteristics of field effect transistor (FET). Theory: The Field Effect Transistor (FET) is a three terminal device. Three terminals are Drain (D), Source (S) and Gate (G). In FET, current flow is due to only one type of charge particles, either electrons or holes. So FET is known as unipolar device. The name field effect is derived from the fact that the current is controlled by an electric field set up in the device by an externally applied voltage. Thus FET is a voltage controlled device while bipolar transistor is current controlled device. The Field Effect Transistor (FET) can be broadly classified into following categories: In this experiment we will obtain output characteristics of N-channel FET using CS (Common source) Configuration. It is also known as drain characteristics. Basic construction of N-channel FET and its symbol are shown in the following figure. When gate to source voltage VGS is zero, N type channel is open so drain current will flow through it. As we increase negative voltage on the gate terminal, VGS=-1V, -2V, -3V etc., drain current reduces. The reduction in drain current is due to reduction in width of channel. As we increase negative gate voltage, width of depletion region spreads in the channel. Depletion region (generated field due to reverse bias) does not have charge carriers so width of channel will reduce. As we increase negative value of VGS, penetration of depletion region (field) will be more and more due to which channel becomes narrower. At one point drain current reduces to zero when entire channel will be closed due to penetration of depletion region. The value of VGS at which drain current reduces to zero is called cut-off voltage VGS(OFF). Normally Drain current reduces to zero at VGS=-Vp. Thus VGS(OFF) = -VP where VP is pinch-off voltage. Pinch-off voltage VP is the value of voltage VDS at which drain current becomes constant.

2 Circuit Diagram: Experiment Procedure: o Connect circuit as shown in the circuit diagram for output (drain) characteristics. o Connect variable power supply 0-10V at gate circuit and 0-12V at drain circuit. o Keep gate to source voltage zero (VGS=0). o Increase drain supply VDD from 0V to 12V, note down readings of drain current ID and drain to source voltage VDS in the observation table. o Repeat above procedure for different gate to source voltages VGS = -1, o -2, -3, -4 etc. Note down reading of Gate to source voltage at which drain current remains zero. This is cut-off voltage VGS(off). o Note down pinch-off voltage for all values of VGS. o Draw output characteristics curve. Plot VDS on X axis and ID on Y axis.

3 Observation Table: FET:.. S. No. Vgs=0V Vgs=-1V Vgs=-2V Vgs=-4V Conclusion: Vds Id Vds Id Vds Id Vds Id Precaution:

4 Government Polytechnic Muzaffarpur Name of the Lab: Applied Electronics Lab Subject Code: Experiment-4 Aim: To Study RC phase shift oscillator. Apparatus required: o OP amp IC 741 o Dual power supply o Resistors o Capacitors o Diode IN 4001 o CRO o Bread board o Connecting wires Theory: An oscillator is a circuit, which generates ac output signal without giving any input ac signal. This circuit is usually applied for audio frequencies only. The basic requirement for an oscillator is positive feedback. An oscillator consists of an amplifier and a feedback network. (i) (ii) Active device i.e. op amp is used as an amplifier. Passive component such as R-C or L-C combinations are used as feedback network. To start the oscillation with the constant amplitude, positive feedback is not the only sufficient condition. Oscillator circuit must satisfy the following two conditions known as Barkhausen conditions: (i) The first condition is that the magnitude of the loop gain (Aβ)=1 A= amplitude gain and β= feedback gain. (ii) The second condition is that the phase shift around the loop must be or 0 0. RC phase shift oscillator: Phase-shift oscillator is a simple electronic oscillator. It contains an inverting amplifier, and a feedback filter which 'shifts' the phase of the amplifier output by 180 degrees at the oscillation frequency. The filter produces a phase shift that increases with frequency. It must have a maximum phase shift of considerably greater than at high frequencies, so that the phase shift at the desired oscillation frequency is The most common way of achieving that kind of filter is using three identical cascaded resistor-capacitor filters, which together produce a phase shift of zero at low frequencies & at high frequencies. At the oscillation frequency each filter produces a phase shift of 60 0 & the whole filter circuit produces a phase shift of Design: 1 f 0 = 62πRC R f 29R 1 R 1 10R Choose C=0.1µF F0=500Hz 1 R = 62πf 0 C = 1 62πx500x0.1x10 6

5 R=1.3KΩ Choose R=1.5KΩ R1 15KΩ (to prevent loading) Therefore, R1=10R=15KΩ Rf=29R1=29X15KΩ=435KΩ (use 1MΩ port) Tabulation: Input Output Amplitude Time period frequency Amplitude Time period frequency Model graph:

6 Procedure: Design the circuit for f0=500hz. Calculate R1, R2, and Rf Connect the circuit as shown in the figure with the designed value. Switch on the power supply. Note down the amplitude and time period. Plot the wave form on a graph sheet. Result: Thus the RC phase shift oscillator is constructed. Precaution:

7 Government Polytechnic Muzaffarpur Name of the Lab: Applied Electronics Lab Subject Code: Experiment-7,8,9 Aim: To design and study the following circuits using 555 timer. (1) Monostable multivibrator. (2) Astable,multivibrator. (3) Bistable multivibrator or Schmitt trigger. Apparatus required: (i) (ii) (iii) (iv) (v) (vi) IC555 Resistors Capacitors CRO AFO RPS Theory: 555 is a very commonly used IC for generating accurate timing pulse. It is an 8 pin timer IC. The 555 timer has 3 operating modes: o Monostable mode o Astable free running mode o Bistable mode or Schmitt trigger The input/output relationship for the various multivibrators are shown in figure. Monostable multivibrator: Monostable multivibrator often called a one shot multivibrator is a pulse generating circuit in which the duration of this pulse is determined by the RC network connected externally to the

8 555 timer. In a stable or standby state, the output of the circuit is approximately zero or a logic-low level. When external trigger pulse is applied output is forced to go high ( VCC). The time for which output remains high is determined by the external RC network connected to the timer. At the end of the timing interval, the output automatically reverts back to its logiclow stable state. The output stays low until trigger pulse is again applied. Then the cycle repeats. The monostable circuit has only one stable state (output low) hence the name monostable. Design of monostable multivibrator: Time period of the pulse=t=1.1rc=10ms Let C=100f T=1.1RC 10ms=1.1*R*100f R=100K Tabulation: Input output Amplitude Time period Amplitude Time period

9 Model graph: Procedure: (1) Connections are made as per the circuit diagram. (2) A trigger pulse is given to pin 2. (3) Note the time for which the LED glows and note down TON. Astable multivibrator: The astable multivibrator generates a square wave, the period of which is determined by the circuit external to IC 555. The astable multivibrator does not require any external trigger to change the state the external output. Hence the name free running oscillator. The time during which the output is either high or low is determined by the two resistor and a capacitor which are externally connected to the 555 timer. Circuit diagram:

Tabulation: Input Output Amplitude Time period Amplitude Time period ON time OFF time Charging time Discharging time Model graph: Output voltage and capacitor voltage Procedure: i.

10 Tabulation: Input Output Amplitude Time period Amplitude Time period ON time OFF time Charging time Discharging time Model graph: Output voltage and capacitor voltage Procedure: i. Connections are made as per circuit diagram. ii. A supply voltage of 5V to be given. iii. The output waveforms at pin 3 & pin 2 are observed on a CRO. iv. Measure TON and TOFF of a waveform. Schmitt trigger: In the bistable mode or Schmitt trigger, the 555 can operate as a flip flop, if the DIS pin is not connected & no capacitor is used. Uses include bounce free latched switches. The trigger and reset inputs (pins 2 & 4 respectively on a 555) are held high via pull-up resistors while the threshold input is simply grounded. Thus, configured, pulling the trigger momentarily to ground acts as a set & transition the output pin to VCC. Pulling the reset input to ground acts as a reset & transition the output pin to ground. No capacitors are required in a bistable configuration. Pin 5 & 7 are left floating. Bistable signifies two stable states- high and low. In the bistable mode, the555 acts as a Schmitt trigger. A Schmitt trigger produces an output when the input exceeds a specified level. The output continues until the input falls below a specified level. With the 555 a trigger at one input sets the output to HIGH; a trigger at another input sets the output to low. The output retains its value until the input changes sufficiently to trigger a state change.

Circuit diagram: Tabulation: Input Output Amplitude Time period Amplitude Time period ON time OFF time Model graph: Procedure: i. Construct the circuit as shown in the figure. ii.

11 Circuit diagram: Tabulation: Input Output Amplitude Time period Amplitude Time period ON time OFF time Model graph: Procedure: i. Construct the circuit as shown in the figure. ii. Observe the output waveform of Schmitt trigger circuit by giving sine wave as input. iii. Note down the amplitude and time period and draw the output wave form. Results: Thus the monostable multivibrator, astable multivibrator and bistable multivibrator circuits are designed and constructed and the output waveforms are drawn.

12 Government Polytechnic Muzaffarpur Name of the Lab: Applied Electronics Lab Subject Code: Experiment-10 Aim: To study UJT relaxation Oscillator. Apparatus required: I. UJT II. Resistors III. Capacitors IV. CRO V. DC power supply Design: Take Vp= 10 V and f =1 KHZ Vp= η VBB+ Vd (Vd can be neglected) VBB=15V (Assume η = 0.62) From data sheet valley point specifications are Vv=1.5 V and Iv =4 ma and Ip= 5 ma Combination of R2 and R4 is indicated as R. R max= (VBB-Vp)/Ip =1 M R min = (Vbb-Vv)/Iv =3.2 K Take the GM of the two values R= 60 K (For this use a 100 K pot in series with 10 K Now T =RC ln[1/(1-η)] So C=0.004 uf (use 0.01 uf) Use 100 Ω resistors at the two bases to provide low discharging path THEORY UJT is the Uni Junction Transistor. It is a three terminal device. They are: a) emitter b) base1 c) base2. The equivalent circuit is shown with the circuit diagram. So there are two resistors. One is a variable resistor and other is a fixed resistor. The ratio of internal resistances is referred as intrinsic standoff ratio (η).it is defined as the ratio of the variable resistance to the

13 total resistance. Due to the existing pn junction, there will be a voltage drop. If we apply a voltage to the emitter, the device will not turn on until the input voltage is less than the drop across the diode plus the drop at the variable resistance R1.When the device is turned on holes moves from emitter to base resulting in a current flow. Due to this sudden increase in charge concentration in base1 region conductivity increases. This causes a drop at base1.this region in the graph is known as negative resistance region. If we further increase the emitter voltage the device undergoes saturation. So a UJT has 3 operating regions: 1. Cut off region 2. Negative resistance region 3. Saturation region In a relaxation circuit there is an RC timing circuit. When the supply is turned on, the capacitor starts charging. When the voltage across the capacitor reaches the pinch off voltage, the UJT turns on. After discharging of capacitor,again it starts charging, and this process continues till power supply is turned off. PROCEDURE 1. Test the components and identify the leads of UJT 2. Switch on the power supply. 3. Observe the wave forms at bases and emitter of UJT. 4. Plot the graphs WAVE FORMS RESULT A relaxation oscillator using UJT was designed. Output obtained. Waveforms were plotted.

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET REV. NO. : REV.

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. ISSUE NO. : ISSUE DATE: July 200 REV. NO. : REV.