# For input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec

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1 Inverting amplifier: [Closed Loop Configuration] Design: A CL = V o /V in = - R f / R in ; Assume R in = ; Gain = ; Circuit Diagram: RF +10V F.G ~ + Rin IC v0-10v CRO Model Graph Inverting amp Vin (V) t(sec) Vo (V) t(sec) Observation: For input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz 1

2 EX. NO: 1 DATE: / / 2010 Inverting, Non inverting and differential amplifiers. AIM To design Inverting, Non inverting amplifier & Differentiator using op-amp and test its performance APPARATUS REQUIRED S.No Components Range Quantity 1. Op-amp IC Dual trace supply (0-30) V 1 3. Function Generator (0-1) MHz 2 4. Resistors 5. Capacitors 6 CRO (0-30) 1 MHz THEORY INVERTING AMPLIFIER The inverting amplifier is the most widely used of all the op-amp circuits. The output voltage V 0 is fed back to the inverting input terminal through the R f -R 1 network where R f is the feedback resistor. Input signal V i is applied to the inverting input terminal through R 1 and non-inverting input terminal of op-amp is grounded. V 0 = - (R f /R 1 ) Vi A CL = V 0 /Vi = -R f /R 1 The negative sign indicates a phase shift of between V i and V 0. 2

3 Inverting amplifier Design 3

4 NON-INVERTING AMPLIFIER The non-inverting amplifier circuit amplifies without inverting the input signal. In this circuit, the input is applied the non-inverting input terminal & inverting input terminal is grounded. Such a circuit is called non-inverting amplifier. It is also a negative feedback system as output is being fed back to the inverting input terminal. Vo = ( 1 + R f /R 1 ) Vi A CL =Vo/Vi = 1 + R f /R 1 Non inverting amplifier Design 4

5 Non inverting amplifier: [Closed Loop Configuration] Design: A CL = V o / V in = 1 + R f / R in; Assume R in = ; Gain = ; Circuit Diagram R F +10V Rin v0 F.G ~ + -10V CRO Model Graph Non-Inverting amp Vin (V) t(sec) Vo (V) t(sec) Observation: For input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz 5

6 DIFFERNTIAL AMPLIFIER The differential amplifier has a unique feature that many circuits don t have - two inputs. This circuit amplifies the difference between its input terminals. Many circuits that have one input, actually have another input the ground potential. The differential amp rejects the noise common to both signals and rescues the signal difference between the input terminals. Design of Differential amplifier R 1 =R 2 =R 3 =R f = R = V O = R f / R [V 2 V 1 ] 6

7 Circuit Diagram Observation: For input 1: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For input 2: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz For output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz 7

8 Procedure: 1. Connect the components as per the circuit diagram. 2. Set the input voltage using F.G 3. observe the output waveform at Pin no.6 4. Connect CRO at Pin no.6 and measure 0/p voltage and note it down. 5. Plot the output waveforms RESULT: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature with Date Result (10) Post Lab Test (20) Total (100) 8

9 Circuit Diagram Model Graph: Observation: For sine wave input: Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz For square wave input: Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz 9

10 EX. NO: 2 DATE: / / 2010 AIM INTEGRATOR AND DIFFERENTIATOR To design an integrator & Differentiator using op-amp and test its performance. APPARATUS REQUIRED S.No Components Range Quantity 1. Op-amp IC Dual trace supply (0-30) V 1 3. Function Generator (0-1) MHz 1 4. Resistors 5. Capacitors 6 CRO (0-30) 1 MHz DIFFERENTIATOR: A circuit in which output waveform is the derivative of the input waveform is known as the differentiator or the differentiation amplifier. Such a circuit is obtained by using operational amplifier in the inverting configuration connecting a capacitor, C1 at the input V 0 = - R f C 1 dvi/dt INTEGRATOR: The circuit performs the mathematical operation of Integration, that is, the output waveform is the integral of input waveform. V 0 (t)= -1/R 1 C f V i (t)dt+v 0 (0) V 0 (0) = initial output voltage 10

11 Differentiator: Design: Step1: Select f a equal to the highest frequency of the input signal to be differentiated. Then assuming a value of C 1 < 1µF. calculate the value of R f. Step2: Choose f b = 20 f a and calculate the values of R 1 and C f so that R 1 C 1 = R f C f. f a = KHz ; f b = KHz ;C 1 = 0.1 µf; R COMP = R f ; R L = 10KΩ f a = 1/ [2πR f C 1 ]; R f = 1/2π C 1 f a ; f b = 1/ [2πR 1 C 1 ];R 1 = 1/2π C 1 f b; R 1 C 1 = R f C f ; C f = R1C1/ R f 11

12 Integrator: Design: Generally the value of the f a and in turn R 1 C f and R f C f values should be selected such that f a < f b. From the frequency response we can observe that f a is the frequency at which the gain is 0 db and f b is the frequency at which the gain is limited. Maximum input signal frequency = 1 KHz. Condition is time period of the input signal is larger than or equal to R f C f (i.e.) T R1Cf f b = KHz ; f a = f b /10; R f = 10R 1 ; R COMP = R 1; R L & R 1 = 10KΩ f a = 1/ [2πR f C f ]; Rf C f = 1msec &; Cf = 1msec/100K 12

13 Circuit Diagram: Cf R1 Rf +12V Vin R COMP Rom = R IC V RL V O = - [1/R 1 C f ] Vin dt Model Graph 0 Vin Model graph t t Vo t t Observation: For sine wave input: Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz For square wave input: Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz 13

14 Procedure: 1. Connect the components as per the circuit diagram. 2. Set the input voltage using F.G 3. observe the output waveform at Pin no.6 4. Connect CRO at Pin no.6 and measure 0/p voltage and note it down. 5. Plot the output waveforms RESULT: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature with Date Result (10) Post Lab Test (20) Total (100) 14

15 EX. NO: 3 DATE: / / 2010 INSTRUMENTATION AMPLIFIER AIM To design an instrumentation amplifier Using Op-Amp & test its performance. APPARATUS REQUIRED S.No Components Range Quantity 1. Op-amp IC Dual trace supply (0-30) V 1 3. Function Generator (0-1) MHz 2 4. Resistors 5. Capacitors 6 CRO (0-30) 1 MHz THEORY INSTRUMENTATION AMPLIFIER: An instrumentation (or instrumentational) amplifier is a type of differential amplifier that has been outfitted with input buffers, which eliminate the need for input impedance matching and thus make the amplifier particularly suitable for use in measurement and test equipment. Additional characteristics include very low DC offset, low drift, low noise, very high open-loop gain, very high common-mode rejection ratio, and very high input impedances. Instrumentation amplifiers are used where great accuracy and stability of the circuit both short- and long-term are required. The electronic instrumentation amp is almost always internally composed of 3 opamps. These are arranged so that there is one op-amp to buffer each input (+, ), and one to produce the desired output with adequate impedance matching for the 15

16 function.consider all resistors to be of equal value except for R gain. The negative feedback of the upper-left op-amp causes the voltage at point 1 (top of R gain ) to be equal to V 1. Likewise, the voltage at point 2 (bottom of R gain ) is held to a value equal to V 2. This establishes a voltage drop across R gain equal to the voltage difference between V 1 and V 2. That voltage drop causes a current through R gain, and since the feedback loops of the two input op-amps draw no current, that same amount of current through R gain must be going through the two "R" resistors above and below it. This produces a voltage drop between points 3 and 4 equal to: The regular differential amplifier on the right-hand side of the circuit then takes this voltage drop between points 3 and 4, and amplifies it by a gain of 1 (assuming again that all "R" resistors are of equal value). Though this looks like a cumbersome way to build a differential amplifier, it has the distinct advantages of possessing extremely high input impedances on the V 1 and V 2 inputs (because they connect straight into the noninverting inputs of their respective op-amps), and adjustable gain that can be set by a single resistor. Manipulating the above formula a bit, we have a general expression for overall voltage gain in the instrumentation amplifier: Though it may not be obvious by looking at the schematic, we can change the differential gain of the instrumentation amplifier simply by changing the value of one resistor: R gain. The overall gain can be changed by changing the values of some of the other resistors, but this would necessitate balanced resistor value changes for the circuit to remain symmetrical. Please note that the lowest gain possible with the above circuit is obtained with R gain completely open (infinite resistance), and that gain value is 1. 16

17 Circuit Diagram Observation For input 1: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For input 2: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz 17

18 Instrumentation amplifier Design:, R=, R gain = - 18

19 Procedure: 1. Connect the components as per the circuit diagram. 2. Set the input voltage using F.G. 3. observe the output waveform at Pin no.6 4. Connect CRO at Pin no.6 and measure 0/p voltage and note it down. 5. Plot the output waveforms 19

20 RESULT: Contents Marks obtained Signature Prelab test(20) Postlab test(20) Simulation(25) Circuit connection and result(35) Total 20

21 Circuit diagram Model graph 21

22 EX. NO: 4 DATE: / / 2010 ACTIVE LOWPASS, HIGHPASS AND BANDPASS FILTERS. AIM To design an active low pass, high pass and band pass filter Using Op-Amp & test its performance. APPARATUS REQUIRED Thoery S.No Components Range Quantity 1. Op-amp IC Resistors 3. Capacitor O.01µf 2 4. CRO 1 5. Power Supply ± 15V 1 6. Probe 2 7. Bread Board 1 LPF: A LPF allows only low frequency signals up to a certain break-point f H to pass through, while suppressing high frequency components. The range of frequency from 0 to higher cut off frequency f H is called pass band and the range of frequencies beyond f H is called stop band. Design Procedure: 1. Choose the cutoff frequency w c or f c 2. Pick c 1, choose value <=0.1 µf 3. Make C2=2C 1 4. Calculate R=0.707/w c C 1 5. Choose R f =2R 22

23 LPF Design: Procedure: LPF: 1. Connections are given as per the circuit diagram. 2. Input signal is connected to the circuit from the signal generator. 3. The input and output signals of the filter channels 1 and 2 of the CRO are connected. 4. Suitable voltage sensitivity and time-base on CRO is selected. 5. The correct polarity is checked. 6. The above steps are repeated for second order filter 23

24 Tabulation Second order LPF Vin= S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin) 24

25 HPF: A high-pass filter, or HPF, is an LTI filter that passes high frequencies well but attenuates (i.e., reduces the amplitude of) frequencies lower than the filter's cutoff frequency. The actual amount of attenuation for each frequency is a design parameter of the filter. It is sometimes called a low-cut filter or bass-cut filter. Design Procedure: 1.Choose a cutoff frequency w c or f c. 2. Let C 1 =C 2 =C and choose a convenient value. 3. Calculate R 1 from R 1 =1.414/w c C 4. Select R 2 =(1/2)R 1 5. To minimize dc offset, let R f =R 1 Design of HPF 25

26 Circuit diagram: Model graph: 26

27 Tabulation Second order HPF Vin= S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin) Procedure: 1. Connections are given as per the circuit diagram. 2. Input signal is connected to the circuit from the signal generator. 3. The input and output signals of the filter channels 1 and 2 of the CRO are connected. 4. Suitable voltage sensitivity and time-base on CRO is selected. 5. The correct polarity is checked. 6. The above steps are repeated for second order filter. 27

28 Circuit diagram: Model graph 28

29 BPF: A band-pass filter is a device that passes frequencies within a certain range and rejects (attenuates) frequencies outside that range. BPF Design: 29

30 Circuit diagram: Model graph: 30

31 Tabulation:- BPF Vin= S.No Frequency (Hz) Vo(volts) Gain=20log(Vo/Vin) Procedure: BPF:- 1. The input signal is connected to the circuit from the signal generator. 2. The input and output signals are connected to the filter. 3. The suitable voltage is selected. 4. The correct polarity is checked. 5. The steps are repeated. 31

32 RESULT: Contents Marks obtained Signature Prelab test(20) Postlab test(20) Simulation(25) Circuit connection and result(35) Total 32

33 Circuit Diagram 10KΩ C 0.05µf R +10V IC V 6 R1 11.6Ω CRO V O R2 10 kω Observation Output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz. 33

34 Ex. No 5 DATE: / / 2010 Astable,Monostable Multivibrators and Schmitt trigger using op-amp Aim To design Astable, monostable Multivibrators and Schmitt trigger using opamp and plot its waveforms. Apparatus Required: S.No Component Range Quantity 1. Op amp IC DTS (0-30) V 1 3. CRO 1 4. Resistor 1 5. Capacitors 6. Diode IN Probes 1 THEORY: ASTABLE MULTIVIBRATOR: Multivibrators are a group of regenerative circuits that are used extensively in timing applications. It is a wave shaping circuit which gives symmetric or asymmetric square output. It has two states either stable or quasi- stable depending on the type of multivibrator. Astable multivibrator is a free running oscillator having two quasi-stable states. Thus, there is oscillations between these two states and no external s i g n a l a r e required to produce the change in state. 34

35 Astable Multivibrator: Design: T = 2RC R 1 = 1.16 R 2 Given f o = KHz Frequency of Oscillation fo = 1 / 2 RC if R 1 = 1.16R 2 Let R 2 = 10 K R 1 = 10 Let C = 0.05 F R = 1 / 2 fc = 1/ (2 35

36 MONOSTABLE MULTIVIBRATOR: Monostable multivibrator is one, which generates a single pulse of specified duration in response to each external trigger signal. It has only one stable state. Application of a trigger causes a change to the quasi-stable state. An external trigger signal generated due to charging and discharging of the capacitor produces the transition to the original stable state Design: Monostable Multivibrators: β = R 2 /R 1 +R 2 [ = 0.5 & R 1 = 10 K] Find R 2 = ; R3 = 1K; R4 = 10K; Let F = KHz ; C= 1mfd; C4 = 0.1mfd Pulse width, T = 0.69RC Find R = 36

37 Circuit Diagram R +10V D1 C VC IC R 3 VO R1-10V CRO C4 D2 Vβsat R 2 V in R4 Model graph: V in T P t VD V C t Vβsat Vsat t VO V sat T 37

38 Observation Input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz Output: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz Procedure: Astable multivibrator 1. Make the connections as shown in the circuit diagram 2. Keep the CRO channel switch in ground and adjust the horizontal line on the x axis so that it coincides with the central line. 3. Select the suitable voltage sensitivity and time base on the CRO. 4. Check for the correct polarity of the supply voltage to op-amp and switch on power supply to the circuit. 5. Observe the waveform at the output and across the capacitor. Measure the frequency of oscillation and the amplitude. Compare with the designed value. 6. Plot the Waveform on the graph. Monostable Multivibrator: 1. Make the connections as shown in circuit diagram. 2. A trigger pulse is given through differentiator circuit through pin no.3 3. Observe the pulse waveform at pin no.6 using CRO and note down the time period. 4. Plot the waveform on the graph. 38

39 Circuit Diagram +12V Vin R1 4-12V R2 RL = 10K 0 Model Graph 39

40 SCHMITT TRIGGER: If the input to a comparator contains noise, the output may be erractive when v in is near a trip point. For instance, with a zero crossing, the output is low when v in is positive and high when v in is negative. If the input contains a noise voltage with a peak of 1mV or more, then the comparator will detect the zero crossing produced by the noise. This can be avoided by using a Schmitt trigger, circuit which is basically a comparator with positive feedback. Because of the voltage divider circuit, there is a positive feedback voltage. When OPAMP is positively saturated, a positive voltage is feedback to the noninverting input; this positive voltage holds the output in high stage. (v in < v f ). When the output voltage is negatively saturated, a negative voltage feedback to the inverting input, holding the output in low state. Schmitt Trigger: Design V CC = 12 V; V SAT = 0.9 V CC ; R1= 47KΩ; R2 = 120Ω V UT = + [V SAT R 2 ] / [R 1 +R 2 ] & V LT = - [V SAT R 2 ] / [R 1 +R 2 ] & HYSTERESIS [H] = V UT - V LT 40

41 Observation: For sine wave input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For square wave input: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz Upper Threshold voltage, V UT = Lower Threshold voltage, V LT = Hysteresis voltage, V H = Procedure 1. Connect the circuit as shown in the circuit 2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than V cc ) 3. Note down the output voltage at CRO 4. To observe the phase difference between the input and the output, set the CRO in dual Mode and switch the trigger source in CRO to CHI. 5. Plot the input and output waveforms on the graph. 41

42 RESULT: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature with Date Result (10) Post Lab Test (20) Total (100) 42

43 Wein Bridge Oscillator:- Circuit Diagram:- R1=10 kω R f =20 kω +10V ICY V CRO V O R = 3.2kΩ C 0.05µf 3.2kΩ R C 0.05 µf Model Graph: V O + Vp t Vp Observation: Peak to peak amplitude of the output = volts. Frequency of oscillation = Hz. 43

44 EXP.NO.6:- DATE: / / 2010 Aim: Phase shift and Wien bridge oscillators To design the following sine wave oscillators a) Wein Bridge Oscillator with the frequency of 1 KHz. b) RC Phase shift oscillator with the frequency of 200 Hz. Components Required: S.No Components Range Quantity 1. Op-amp IC Dual trace supply (0-30) V 1 3. Function Generator (0-2) MHz 1 4. Resistors 5. Capacitors 6 CRO (0-30) MHz 1 7 Probes THEORY: WEIN BRIDGE OSCILLATOR: A Wien bridge oscillator is a type of electronic oscillator that generates sine waves. The bridge comprises four resistors and two capacitors. It can generate a large range of frequencies. The frequency of oscillation is given by: F = 1/2 RC 44

45 Circuit Diagram:- R1 1 mω DRB 33kΩ Rf +10V 32kΩ IC µf 0.01µf -10V 0.01µf CRO VO C C C R 3.3kΩ R 3.3kΩ R 3.3kΩ Model Graph: VO t Observation: Peak to peak amplitude of the sine wave = Volts Frequency of Oscillation (obtained) = Hz. 45

46 RC Phase Shift Oscillators: Design: Frequency of oscillation fo = 1/( 6*2*Π*RC) Av = [Rf/R1] = 29 R 1 = 10 R R f = 29 R 1 Given fo = 200 Hz. Let C = 0.1µF ( ) 6 ( ) R = 1 / 6 * 2 π * fo * C = 1 / 6 * 2 * π * 200 * 0.1 *10 = KΩ To prevent the loading of amplifier by RC network, R1 10R R1 = 10 * = KΩ Since Rf = 29R1 Rf = 29 * = MΩ 46

47 RC PHASE SHIFT OSCILLATOR: A phase-shift oscillator is a simple sine wave electronic oscillator. It contains an inverting amplifier, and a feedback filter consisting of an RC network which 'shifts' the phase by 180 degrees at the oscillation frequency. The filter must be designed so that at frequencies above and below the oscillation frequency the signal is shifted by either more or less than 180 degrees. This results in constructive superposition for signals at the oscillation frequencies, and destructive superposition for all other frequencies The most common way of achieving this kind of filter is using three cascaded resistor-capacitor filters, which produce no phase shift at one end of the frequency scale, and a phase shift of 270 degrees at the other end. At the oscillation frequency each filter produces a phase shift of 60 degrees and the whole filter circuit produces a phase shift of 180 degrees. The mathematics for calculating the oscillation frequency and oscillation criterion for this circuit are surprisingly complex, due to each R-C stage loading the previous ones. Equations Related to the Experiments: a) Wein Bridge Oscillator Closed loop gain A v = (1+R f /R 1 ) = 3 Frequency of Oscillation f a = 1/(2πRC) b) RC Phase shift Oscillator: Gain A v = [R f /R 1 ] = 29 Frequency of oscillation f a = 1 6 * 2 * π * RC 47

48 Wein Bridge Oscillator: Design: Gain required for sustained oscillation is A v = 1/β = 3 (PASS BAND GAIN) (i.e.) 1+R f /R 1 = 3 Frequency of Oscillation f o = 1/2π R C Given f o = 1 KHz Let C = 0.05 µf R = 1/2 π f o C R = 3.2 KΩ R f = 2R 1 Let R1 = 10 KΩ Rf = 2 * 10 KΩ 48

49 Procedure: Wein Bridge Oscillator 1. Connect the components as shown in the circuit. 2. Switch on the power supply and CRO. 3. Note down the output voltage at CRO. 4. Plot the output waveform on the graph. 5. Redesign the circuit to generate the sine wave of frequency 2 KHz. 6. Compare the output with the theoretical value of oscillation. RC Phase shift Oscillator 1. Connect the circuits as shown in the circuit 2. Switch on the power supply. 3. Note down the output voltage on the CRO. 4. Plot the output waveforms on the graph. 5. Redesign the circuit to generate the sine wave of 1 KHz. 6. Plot the output waveform on the graph. 7. Compare the practical value of the frequency with the theoretical value. Result: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature With Date Result (10) Post Lab Test (20) Total (100) 49

50 EXP.NO: 7 DATE: / / 2010 Astable and monostable multivibrators Aim: To design and test an astable and monostable multivibrators using ne555 timer. Apparatus Required: S.No Component Range Quantity TIMER 1 2. Resistors 3.3K, 6.8k 1 3. Capacitors 0.1 F 0.01 F 2 4. Diode In CRO 1 6. Power 15 V 1 supply 7. Probe 2 8. Bread Board 1 Astable Multivibrators using 555 Fig shows the 555 timer connected as an Astable Multivibrators. Initially, when the output is high. Capacitor C starts charging towards V cc through R A and R B. As soon as capacitor voltage equals 2/3 V cc upper comparator (UC) triggers the flip flop and the output switches low. Now capacitor C starts discharging through R B and transistor Q 1. 50

51 Circuit Diagram Vcc +5 V RA 6.8k D RB 3.3k V O µF 0.01µF Model Graph Vc VUT VUT t(ms) VO t high tlow t(ms) 51

52 Observation: For output at pin no.3:peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For capacitor input: Peak to peak amplitude of the output = volts. Charging time = sec Discharging time = sec Time period for 1 full cycle = sec Frequency of the output = Hz DESIGN: Design an Astable Multivibrators for a frequency of KHz with a duty cycle ratio of D = 50 fo = 1/T = 1.45 / (R A +2R B )C Choosing C = 1 F; R A = 560 D = R B / R A +2R B = 0.5 [50%] R B = 52

53 When the voltage across C equals 1/3 V cc lower comparator (LC), output triggers the flip-flop and the output goes high. Then the cycle repeats. The capacitor is periodically charged and discharged between 2/3 V cc and 1/3 V cc respectively. The time during which the capacitor charges form 1/3 V cc to 2/3 V cc is equal to the time the output is high and is given by T c = 0.69(R A +R B )C (1) Where R A and R B are in Ohms and C is in farads. Similarly the time during which the capacitor discharges from 2/3 V cc to 1/3 V cc is equal to the time the output is low and is given by T d = 0.69 R B C (2) The total period of the output waveform is T = T c + T d = 0.69 (R A + 2R B ) C (3) The frequency of oscillation f o = 1 / T =1.45 / (R A +2R B )C (4) Eqn (4) shows that f o is independent of supply voltage Vcc The duty cycle is the ratio of the time t d during which the output is low to the total time period T. This definition is applicable to 555 Astable Multivibrators only; conventionally the duty cycle ratio is defined as the ratio as the time during which the output is high to the total time period. Duty cycle = td T 100 R B + R A + 2R B 100 To obtain 50 % duty cycle a diode should be connected across R B and R A must be a combination of a fixed resistor and a potentiometer. So that the potentiometer can be adjusted for the exact square waves 53

54 Circuit Diagram: Vcc +5 V RA 10k 0.01µF VO Trigger i/p µF 0.01µF Model Diagram: Vcc (i) Trigger input 0 V Vcc 0 V (ii) Output 0 V (ii)capacitor Voltage 54

55 Observation For trigger input: Peak to peak amplitude of the input = volts. Time period for 1 full cycle = sec Frequency of the input = Hz For output at pin no.3: Peak to peak amplitude of the output = volts. Time period for 1 full cycle = sec Frequency of the output = Hz For capacitor voltage: Peak to peak amplitude of the output = volts. Charging time = sec Discharging time = sec Monostable Multivibrator: Design: Given a pulse width of duration of 100 s Let C = 0.01 mfd; F = KHz Here, T= 1.1 R A C So, R A = 55

56 Monostable Multivibrators using 555 Monostable Multivibrators has one stable state and other is a quasi stable state. The circuit is useful for generating single output pulse at adjustable time duration in response to a triggering signal. The width of the output pulse depends only on external components, resistor and a capacitor. The stable state is the output low and quasi stable state is the output high. In the stable state transistor Q1 is on and capacitor C is shorted out to ground. However upon application of a negative trigger pulse to pin2, Q1 is turned off which releases the short circuit across the external capacitor C and drives the output high. The capacitor C now starts charging up towards V cc through R A. However when the voltage across C equal 2/3 V cc the upper comparator output switches form low to high which in turn drives the output to its low state via the output of the flip flop. At the same time the output of the flip flop turns Q1 on and hence C rapidly discharges through the transistor. The output remains low until a trigger is again applied. Then the cycle repeats. The pulse width of the trigger input must be smaller than the expected pulse width of the output. The trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc. The width of the output pulse is given by, T = 1.1 R A C 56

57 Procedure: 1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value of components. 2. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing capacitor. Set suitable voltage sensitively and timebase on the CRO. 3. Switch on the power supply to CRO and the circuit. 4. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the voltage levels at which the capacitor starts charging and discharging, output high and low timings and frequency. 5. Switch off the power supply. Connect a diode across R B as shown in dashed lines in fig to make the Astable with 50 duty cycle ratio. Switch on the power supply. Observe the output waveform. Draw to scale on a graph sheet. Procedure: Monostable Multivibrator: 1. Rig-up the circuit of 555 monostable Multivibrators as shown in fig with the designed value of components. 2. Connect the trigger input to pin 2 of 555 timer form the function generator. 3. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing capacitor. Set suitable voltage sensitively and timebase on the CRO. 4. Switch on the power supply to CRO and the circuit. 5. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the voltage levels at which the capacitor starts charging and discharging, output high and low timings along with trigger pulse. 57

58 Result: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature With Date Result (10) Post Lab Test (20) Total (100) 58

59 BLOCK DIAGRAM Circuit diagram 59

60 EXP.NO: 8 DATE: / / 2010 PLL characteristics and its use as Frequency Multiplier. Aim: To design a PLL characteristics and its use as Frequency Multiplier. Apparatus Required: S.No Component Range Quantity 1. IC NE565,74c Resistors 3. Capacitors 5. CRO 1 6. Power 15 V 1 supply 7. Probe 2 8. Bread Board 1 Theory Phase locked loops are used for frequency control. They can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. Each of these applications demands different characteristics but they all use the same basic circuit concepts. The block diagram consist of a feedback control system that controls the phase of a voltage controlled oscillator(vco). The input signal is applied to one input of phase detector. The other input is connected to the output of a divide by N counter. Normally the frequencies of both signals will be nearly the same. The output of the phase detector is a voltage, proportional to the phase difference 60

61 between the two inputs. This signal is applied to the phase difference between the two inputs, this signal is applied to the loop filter. The loop filter determines the dynamic characteristics of the PLL. The filtered signal controls the VCO. Note that the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase detector via a divided by N counter. Normally the loop filter is designed to match the characteristics required by the application of the PLL. If the PLL is to acquire and track a signal bandwidth of the loop filter will be greater than if it expects a fixed input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal the range of frequencies that the PLL will follow is called track range. Generally the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the filters bandwidth the smaller the achievable capture range. 61

62 Circuit Diagram 62

63 PLL characteristics: Free running Mode Peak to peak amplitude of free running = Frequency of free running = Time = Locked mode Peak to peak amplitude of locked mode = Frequency of locked mode = Time = Output Peak to peak amplitude of output = Frequency of output = Time = Frequency Multiplier Input: Peak to peak amplitude of input = Frequency = Time period = Output: Peak to peak amplitude of output = Frequency = Time period = 63

64 Result: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature With Date Result (10) Post Lab Test (20) Total (100) 64

65 CIRCUIT DIAGRAM: Low Voltage Regulator 0.1 UF Unregulated DC Power Supply R1 R k 6 5 Vref V+ Vc Vo CL NI CS LM723 INV V- 7 COMP N3055 TIP Rsc + - A Load V pF DESIGN: Output voltage V O Reference voltage Vref Rprotect Minimum Resistance to protect the output from short circuit. Low Voltage Regulator: Given: Vo=5V, Vref = 7.15 V To calculate R1, R2, R3 and Rsc. Vo = Vref ( R2 / ( R1 + R2 ) ) 5 / 7.15 = ( R2 / ( R1 + R2 ) ) (R1 + R2) 0.699= R R1 = R2, R1 = R2 Select R2 = 1 KΩ R1 = 1 KΩ * = 430Ω R1 = 430Ω R3 = R1 * R2 / (R1 + R2), R3 = *1000 / ( ) R3 = 300Ω Rsc = V sense / I limit = 0.5 /1A = 0.5Ω, Rsc = 0.5Ω 65

66 EXP.NO.9: DATE: / / 2010 AIM: DC power supply To design a DC power supply using LM317 and LM723 COMPONENTS REQUIRED: S.NO COMPONENTS SPECIFICATION QUANTITY 1. Transistors TIP122,2N each 2. Integrated Circuit LM Digital Ammeter ( 0 10 ) A 1 4. Digital Voltmeter ( 0 20 ) V 1 5. Variable Power Supply ( 0 30 ) V-2A 1 6. Resistors 300Ω,430Ω,1KΩ,678KΩ,678Ω 1Ω 1 each 2 7. Capacitors 0.1µF,100pF 1 each 9. Rheostat ( ) Ω 1 THEORY GENERAL PURPOSE REGULATOR IC is a general purpose regulator, which can be adjusted over a wide range of both positive and negative regulated voltage. Though the IC is a low current device, current can be boosted to provide 5 amps or more. 66

67 CIRCUIT DIAGRAM: High Voltage Regulator: High Voltage Regulator: Given : Vo=12V, Vref = 7.15 V To calculate R1, R2, R3 and Rsc. Vo = Vref ( 1 + (R1 / R2) ) 12 / 7.15 = 1+ (R1 / R2) (12 / 7.15) - 1 = (R1 / R2) (R1 / R2) = Select R2 = 1 KΩ R1 = 1 KΩ * = 678Ω R1= 678Ω Rsc = V sense / I limit = 0.5 /1A = 0.5Ω Rsc = 0.5Ω 67

68 It has short circuit protection and no short circuit current limits. It can operate with an input voltage from 9.5V to 40V and provide output voltage from 2V to 37V. 723 IC has two sections. One section provides a fixed voltage of 7V at the terminal V ref. Other section consists of an error amplifier and two transistors. These two sections are not internally connected. LOW VOLTAGE REGULATOR V ref point is connected through a resistance to the non-inverting terminal and the output if feedback to the inverting terminal of the error amplifier. If the output voltage becomes low, the voltage at the inverting terminal of error amplifier also goes down. This makes the output of the error amplifier becomes more positive, thereby driving transistor more into conduction. This reduces voltage across the transistor and drives more current into the load causing voltage across load to increase. HIGH VOLTAGE REGULATOR If it is desired to produce regulated output voltage greater than 7V, a small change should be made in the circuit for low voltage regulator. The non-inverting terminal is connected directly to V ref. So the voltage at the non-inverting terminal is V ref. The error amplifier operates as a non-inverting amplifier. PROCEDURE: LOW VOLTAGE REGULATOR: Line Regulation: 1. Give the circuit connection as per the circuit diagram. 2. Set the load Resistance to give load current of 0.25A. 3. Vary the input voltage from 7V to 18V and note down the corresponding output voltages. 68

69 4. Similarly set the load current (IL) to 0.5A & 0.9A and make two more sets of measurements. Tabulation of the Measurements: LOW VOLTAGE REGULATOR: Line Regulation: S.No. Load Resistance R L1 = Load Resistance R L2 = Load Resistance R L3 = Input Output Input Output Input Output Voltage Voltage Voltage Voltage Voltage Voltage Vin(Volts) V L (Volts) Vin(Volts) V L Vin(Volts) V L (Volts) (Volts) 69

70 Load Regulation: S.No. Input Voltage V in1 = Input Voltage V in2 = Input Voltage V in3 = Output Output Output Output Output Output Current Voltage Current Voltage Current Voltage I L ( A ) V L (Volts) I L ( A ) V L (Volts) I L ( A ) V L (Volts) Load Regulation: 1. Set the input voltage to 10V. 2. Vary the load resistance in equal steps from 350Ω to 5Ω and note down the corresponding output voltage and load current. 3. Similarly set the input voltage (Vin) to 14V & 18V and make two more sets of measurements. Lab Report: 1. Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (V L ) along Y-axis for various load currents. 2. Plot the load regulation by taking load current (I L ) along X-axis and Output Voltage (V L ) along Y-axis for various input voltages. 3. Calculate its % Voltage Regulation using the formula. 70

71 HIGH VOLTAGE REGULATOR: Line Regulation: 1. Give the circuit connection as per the circuit diagram. 2. Set the load Resistance to give load current I L of 0.25A. 3. Vary the input voltage from 7V to 18V and note down the corresponding output voltages. 4. Similarly set the load current (IL) to 0.5A & 0.9A and make two more sets of measurements. Load Regulation: 1. Set the input voltage to 10V. 2. Vary the load resistance in equal steps from 350Ω to 15Ω and note down the corresponding output voltage and load current. 3. Similarly set the input voltage (Vin) to 14V & 18V and make two more sets of measurements. 71

72 HIGH VOLTAGE REGULATOR: Line Regulation: S.No. Load Resistance R L1 = Load Resistance R L2 = Load Resistance R L3 = Input Output Input Output Input Output Voltage Voltage Voltage Voltage Voltage Voltage Vin(Volts) V L (Volts) Vin(Volts) V L Vin(Volts) V L (Volts) (Volts) 72

73 Load Regulation: S.No. Input Voltage V in1 = Input Voltage V in2 = Input Voltage V in3 = Output Output Output Output Output Output Current Voltage Current Voltage Current Voltage I L ( A ) V L (Volts) I L ( A ) V L (Volts) I L ( A ) V L (Volts) Lab Report: 1. Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (V L ) along Y-axis for various load currents. 2. Plot the load regulation by taking load current (I L ) along X-axis and Output Voltage (V L ) along Y-axis for various input voltages. 3. Calculate its % Voltage Regulation using the formula. Calculation of % Voltage Regulation: % Voltage Regulation = ( V dc ( NL ) - V dc ( FL ) ) / V dc ( FL ) V dc (NL) = D.C. output voltage on no load V dc (FL) = D.C. output voltage on full load 73

74 Model Graph: Line Regulation: Input Voltage Vs Output Voltage: Load Regulation: Output Current Vs Output Voltage: V 0 Line regulation V 0 Load regulation V in I L 74

75 Result: Pre Lab Test (20) Remarks & Simulation (20) Circuit Connection (30) Signature With Date Result (10) Post Lab Test (20) Total (100) 75

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