NO RECOMMENDED REPLACEMENT

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1 HC-556 PCM Transcoder OBOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical upport Center at -888-INTERIL or DATAHEET FN2887 Rev.3. July 23 The HC-556 digital line transcoder provides encoding and decoding of pseudo ternary line code substitution schemes. Unlike other industry standard transcoders, the HC-556 provides four worldwide compatible mode selectable code substitution schemes, including HDB3 (High Density Bipolar 3), B6Z, B8Z (Bipolar with 6 or 8 Zero ubstitution) and AMI (Alternate Mark Inversion). The HC-556 is fabricated in CMO and operates from a single 5 supply. All inputs and outputs are TTL compatible. Application Note #573, The HC-556 Digital Line Transcoder, by D.J. Donovan is available. Part Number Information PART NUMBER Pinout TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HC to 7 2 Ld PDIP E2.3 FORCE AI MODE ELECT NRZ DAT CLK ENC MODE ELECT HC-556 (PDIP) TOP IEW 2 9 DD OUTPUT ENABLE 8 REET 7 OUT 6 OUT2 Features ingle 5 upply ma (Typ) Mode electable Coding Including: - AMI (T, TC) - B8Z (T) - HDB3 (PCM3) North American and European Compatibility imultaneous Encoding and Decoding Asynchronous Operation Loop Back Control Transmission Error Detection Alarm Indication ignal Replaces MJ44, MJ47 and TCM22 Transcoders Applications North American and European PCM Transmission Lines where Pseudo Ternary Line Code ubstitution chemes are Desired Any Equipment that Interfaces T, TC, T2 or PCM3 Lines Including Multiplexers, Channel ervice Units, (CUs) Echo Cancellors, Digital Cross-Connects (DXs), T Compressors, etc. Related Literature - AN573, The HC-556 Digital Line Transcoder LOOP TET ENABLE Functional Diagram REET AI AI CLOCK MODE ELECT 2 DD NRZ DAT CLK ENC TRANMITTER/ ENCODER CLOCK OUTPUT ENABLE OUT OUT 2 LOOP TET ENABLE WITCH RECEIER/ DECODER NRZ DATA OUT FORCE AI REET DETECT REET AI AI DETECT AI FN2887 Rev.3. Page of July 23

2 HC-556 HC-556 Absolute Maximum Ratings oltage at Any Pin GND -.3 to DD.3 Maximum DD oltage Operating Conditions Operating Temperature Range o C to 7 o C Operating DD % Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) PDIP Package Maximum Junction Temperature o C Maximum Junction Temperature (Plastic Package) o C torage Temperature Range o C to 5 o C Maximum Lead Temperature (oldering s) o Die Characteristics Transistor Count Die Dimensions mils x 33 mils ubstrate Potential Process AJI CMO CAUTION: tresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical pecifications Unless Otherwise pecified, Typical parameters at 25 o C, Min-Max parameters are over operating temperature range. DD = 5. PARAMETER YMBOL MIN TYP MAX UNIT TATIC PECIFICATION Quiescent Device Current l DD - - A Operating Device Current - - ma OUT, OUT2 Low (ink) Current ( OL =.4) All Other Outputs Low (ink) Current ( OL =.8) All Outputs High (ource) Current ( OH = 4) I OL ma I OL ma I OH ma Input Low Current I IL - - A Input High Current I IH - - A Input Low oltage ll Input High oltage lh Input Capacitance C ln pf Electrical pecifications Unless Otherwise pecified, Typical parameters at 25 o C, Min-Max parameters are over operating temperature range. DD = 5. PARAMETER YMBOL FIGURE MIN TYP MAX UNIT DYNAMIC PECIFICATION CLK ENC, Input Frequency f CL MHz CLK ENC, Rise Time (.544MHz) t RCL, 2-6 ns Fall Time t FCL, 2-6 ns Rise Time (2.48MHz) t RCL, 2-4 ns Fall Time t FCL, 2-4 ns Rise Time (6.322MHz) t RCL, 2-3 ns Fall Time t FCL, 2-3 ns Rise Time (8.448MHz) t RCL, 2-5 ns Fall Time t FCL, 2-5 ns FN2887 Rev.3. Page 2 of July 23

3 HC-556 Electrical pecifications HC-556 Unless Otherwise pecified, Typical parameters at 25 o C, Min-Max parameters are over operating temperature range. DD = 5. (Continued) PARAMETER YMBOL FIGURE MIN TYP MAX UNIT NRZ-Data In to CLK ENC Data etup Time t ns Data Hold Time t H ns, to Data etup Time t ns Data Hold Time t H ns CLK ENC to OUT, OUT2 t DD ns OUT, OUT2 Pulse Width (CLK ENC Duty Cycle = 5%) f CL =.544MHz t W ns f CL = 2.48MHz t W ns f CL = 6.322MHz t W ns f CL = 8.448MHz t W ns to NRZ-Data Out t DD ns etup Time to Reset Al t ns Hold Time of Reset Al = t H ns etup Time Reset Al = to t ns Reset Al to AI Output t PD ns to Error Output t PD ns Pin Descriptions PIN NUMBER FUNCTION DECRIPTION Force AI Pin 9 must be at logic to enable this pin. A logic on this pin forces OUT and OUT2 to all s. A logic on this pin allows normal operation. 2, 5 Mode elect, Mode elect 2 M M2 Functions As AMI B8Z B6Z HDB3 3 NRZ Data In Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC. 4 CLK ENC Clock encoder, clock for encoding data at NRZ Data In. 6 NRZ Data Out Decoded data from ternary inputs and. 7 Clock decoder, clock for decoding ternary data on inputs and. 8, 9 Reset AI, Al Logic on Reset AI resets a decoded zero counter and either resets AI output to zero provided 3 or more zeros have been decoded in the preceding Reset AI period or sets Al to if less than 3 zeros have been decoded in the preceding two Reset Al periods. A period of Reset Al is defined from the bit following the bit during which Reset Al makes a high to low transition to the bit during which Reset AI makes the next high to low transition. Ground reference. Error A logic indicates that a violation of the line coding scheme has been decoded. 2 Clock OR function of and for clock regeneration when pin 4 is at logic, OR function of OUT and OUT2 when pin 4 is at logic. 3, 5, Inputs representing the received PCM signal. = represents a positive going and = represents a negative going. and are sampled by the positive going edge of. and may be interchanged. FN2887 Rev.3. Page 3 of July 23

4 HC-556 HC-556 Pin Descriptions (Continued) PIN NUMBER FUNCTION DECRIPTION 4 LTE Loop Test Enable, this pin selects between normal and loop back operation. A logic selects normal operation where encode and decode are independent and asynchronous. A logic selects a loop back condition where OUT is internally connected to and OUT2 is internally connected to. A decode clock must be supplied. 6, 7 OUT, OUT2 Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT and OUT2 are in return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT and OUT2 is set by the length of the positive clock pulse. 8 Reset A logic on this pin resets all internal registers to zero. A logic allows normal operation of all internal registers. 9 Output Enable A logic on this pin forces outputs OUT and OUT2 to zero. A logic allows normal operation. 2 DD Power to chip. Functional Description The HC-556 TRANCODER can be divided into six sections: transmission (coding), reception (decoding), error detection, all ones detection, testing functions, and output controls. The transmitter codes a non-return to zero (NRZ) binary unipolar input signal (NRZ Data In) into two binary unipolar return to zero (RZ) output signals (OUT, OUT2). These output signals represent the NRZ data stream modified according to the selected encoding scheme (i.e., AMl, B8Z, B6Z, HDB3) and are externally mixed together (usually via a transistor or transformer network) to create a ternary bipolar signal for driving transmission lines. The receiver accepts as its input the ternary data from the transmission line that has been externally split into two binary unipolar return to zero signals ( and ). These signals are decoded, according to the rules of the selected line code into one binary unipolar NRZ output signal (NRz Data Out). The encoder and decoder sections of the chip perform independently (excluding loopback condition) and may operate simultaneously. The Error output signal is active high for one cycle of upon the detection of any bipolar violation in the received and signals that is not part of the selected line coding scheme. The bipolar violation is not removed, however, and shows up as a pulse in the NRZ Data Out signal. In addition, the Error output signal monitors the received and signals for a string of zeros that violates the maximum consecutive zeros allowed for the selected line coding scheme (i.e., 5 for AMI, 8 for B8Z, 6 for B6Z, and 4 for HDB3). ln the event that an excessive amount of zeros is detected, the Error output signal will be active high for one cycle of during the zero that exceeds the maximum number. In the case that a high level should simultaneously appear on both received input signals and a logical one is assumed and appears on the NRZ Data Out stream with the Error output active. An input signal received at inputs and that consists of all ones (or marks) is detected and signaled by a high level at the Alarm Indication ignal (Al) output. This is also known as Blue Code. The Al output is set to a high level when less than three zeros are received during one period of Reset AI immediately followed by another period of Reset Al containing less than three zeros. The AI output is reset to a low level upon the first period of Reset Al containing 3 or more zeros. A logic high level on LTE enables a loopback condition where OUT is internally connected to and OUT2 is internally connected to (this disables inputs and to external signals). In this condition, NRZ Data In appears at NRZ Data Out (delayed by the amount of clock cycles it takes to encode and decode the selected line code). A decode clock must be supplied for this operation. The output controls are Output Enable and Force Al. These pins allow normal operation, force OUT and OUT2 to zero, or force OUT and OUT2 to output all ones (AI condition). Line Code Descriptions AMl, Alternate Mark Inversion, is used primarily in North American T (.544MHz) and TC (3.52MHz) carriers. Zeros are coded as the absence of a pulse and ones are coded alternately as positive or negative pulses. This type of coding reduces the average voltage level to zero to eliminate DC spectral components, thereby eliminating DC wander. To simplify timing recovery, logic s are encoded with 5% duty cycle pulses. e.g., PCM CODE AMI CODE To facilitate timing maintenance at regenerative repeaters along a transmission path, a minimum pulse density of logic s is required. Using AMl, there is a possibility of long strings of zeros and the required density may not always exist, leading to timing jitter and therefore higher error rates. A method for insuring minimum logic density by substituting bipolar code in place of strings of s is called BNZ or Bipolar FN2887 Rev.3. Page 4 of July 23

5 HC-556 HC-556 with N Zero ubstitution. B6Z is used commonly in North American T2 (6.322MHz) carriers. For every string of 6 zeros, bipolar code is substituted according to the following rule: If the immediate preceding pulse is of (-) polarity, then code each group of 6 zeros as +- +-, and if the immediate preceding pulse is of (+) polarity, code each group of 6 zeros as One can see the consecutive logic pulses of the same polarity violate the AMI coding scheme. e.g., PCM CODE If the polarity of the immediate preceding pulse is (-) and there have been an odd (even) number of logic pulses since the last substitution, each group of 4 consecutive zeros is coded as -(++). 2. If the polarity of the immediate preceding pulse is (+) then the substitution is +(--) for odd (even) number of logic pulses since the last substitution. e.g., PCM CODE HDB3 (-) B6Z (-) HDB3 (+) = IOLATION B6Z (+) = IOLATION B8Z is used commonly in North American T (.544MHz) and TC (3.52MHz) carriers. For every string of 8 zeros, bipolar code is substituted according to the following rules: The 3 in HDB3 refers to the coding format that precludes strings of zeros greater than 3. Note that violations are produced only in the fourth bit location of the substitution code and that successive substitutions produce alternate polarity violations.. If the immediate preceding pulse is of (-) polarity, then code each group of 8 zeros as If the immediate preceding pulse is of (+) polarity then code each group of 8 zeros as e.g., 8 PCM CODE B8Z (-) B8Z (+) The BNZ coding schemes, in addition to eliminating DC wander, minimize timing jitter and allow a line error monitoring capability. Another coding scheme is HDB3, high density bipolar 3, used primarily in Europe for 2.48MHz and 8.448MHz carriers. This code is similar to BNZ in that it substitutes bipolar code for 4 consecutive zeros according to the following rule: = IOLATION FN2887 Rev.3. Page 5 of July 23

6 HC-556 HC-556 Application Diagram 5 FROM CODEC OR TRANCODER DD NRZ DAT ENCODER OUT + T, T2, TC, PCM 3 LINE OUTPUT ENCODER CLOCK CLK ENC OUT2 FORCE AI LTE CONTROL M M2 MODE ELECT LOGIC INPUT REET OUTPUT ENABLE CLOCK REET AI AI CLOCK RECOERY ALARM CLOCK ALARM MONITOR LINE INPUT DIFF AMP + DECODER TO CODED OR TRANCODER M M2 ELECT DECODER CLOCK AMI B8Z B6Z HDB3 Timing Waveforms f CL t RCL t FCL CLK ENC % 9% 5% t t H NRZ DAT 5% 5% OUT, OUT 2 t DD 5% 5% t W FIGURE. TRANMITTER (CODER) TIMING WAEFORM FN2887 Rev.3. Page 6 of July 23

7 HC-556 HC-556 Timing Waveforms (Continued) f CL t FCL % 9% t RCL 5% t t H, 5% CLOCK t DD 5% 5% FIGURE 2. RECEIER (DECODER) TIMING WAEFORM 5% 5% t H2 t 2 REET AI 5% 5% t 2 t PD5 AI OUTPUT 5% t PD4 OUTPUT 5% FIGURE 3. REET AI INPUT, AI OUTPUT, OUTPUT REET AI AI FIGURE 4. Two consecutive periods of Reset AI, each containing less than three zeros, sets AI to a logic and remains in a logic state until a period of Reset AI contains three or more zeros. FN2887 Rev.3. Page 7 of July 23

8 HC-556 HC-556 Timing Waveforms (Continued) REET AI AI FIGURE 5. Zeros which occur during a high to low transition of Reset AI are counted with the zeros that occurred before the high to low transition. NRZ DAT CLK ENC OUT AMI OUT 2 HDB3 OUT OUT 2 OUT B6Z OUT 2 OUT B8Z OUT 2 3 /2 CYCLE 5 /2 CYCLE FIGURE 6. ENCODE TIMING AND DELAY Data is clocked on the negative edge of CLK ENC and appears on OUT and OUT2. OUT and OUT2 are interchangeable. Bipolar violations and all other pulses inserted by the line coding scheme to encode strings of zeros are labeled with an. FN2887 Rev.3. Page 8 of July 23

9 HC-556 HC-556 Timing Waveforms (Continued) AMI HDB3 B6Z B8Z 4 CYCLE 6 CYCLE 8 CYCLE FIGURE 7. DECODE TIMING AND DELAY Data that appears on and is clocked by the positive edge of, decoded, and zeros are inserted for all valid line code substitutions. The data then appears in non-return to zero to zero form at output NRZ Data Out. and are interchangeable. E E E NRZ DATA OUT FIGURE 8. The signal indicates bipolar violations that are not part of a valid substitution. FN2887 Rev.3. Page 9 of July 23

10 HC-556 HC-556 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BAE PLANE EATING PLANE D B -C- -A- N 2 3 N/2 B D e D E NOTE:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANI Y4.5M ymbols are defined in the MO eries ymbol List in ection 2.2 of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge G D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of inch ( mm). -B- A. (.25) M C A A2 L B A e C E C L e A C e B E2.3 (JEDEC M--AD IUE D) 2 LEAD DUAL-IN-LINE PLATIC PACKAGE INCHE MILLIMETER YMBOL MIN MAX MIN MAX NOTE A A A B B C D D E E e. BC 2.54 BC - e A.3 BC 7.62 BC 6 e B L N Rev. 2/93 Copyright Intersil Americas LLC 23. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing IO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN2887 Rev.3. Page of July 23