1 Form C (SPDT) devices

Transcription

1 Frm C (SPDT) devices Single Ple Duble Thrat Relays Single Ple Duble Thrat Switches ide Switches ½ Bridge drivers NC/NO SPDT relay High ltage, NanSecnds Rise/Fall time, Push-Pull Driver Fuzzy Lgic DIN-driver Electrnic Design & Research Inc Under management s Hlding LLC wwwvshldingcm Data Sheet 7, Page Made in USA

2 Cntents: Electrnic Design & Research Inc manufactures vast varieties f Slid State Relays, Breakers, ide Switches, ½ Bridge Drivers, H-Bridge Drivers, Push-Pull Drivers, etc Here is ne mre family f drivers, the way they wrk, applicatins and a data sheets fr sme f them General Intrductin f the T family switches Functinal Diagram f the SPDT switches Typical Applicatins SPDT Relays/Switches with a fuzzy-lgic cntrl input 7 EDR9 - fuzzy-lgic high-speed driver EDR9 - pwerful, high-speed driver 9 EDR9 - fuzzy-lgic, DC, A, ½ driver - EDR - /A KHz ½ driver - EDR7 - DC, A, SPDT r ½ driver ERR7-7DC/AC/A driver -7 EDR7 - pwerful, ½-bridge driver -9 EDR77 - DC, A SPDT relay - EDR9 - H, NanSecnd Rise/Fall time push-pull - EDR99 - fuzzy lgic DIN-driver -7 Ordering Instructin NOTES: We are bringing, in an average fur new devices t the market per mnth Abve is just an eample f switches/drivers that we keep in ur stck in small quantities and ready t ship them at nce Fr yur unique applicatin that required a different vltage, current r speed, Ordering Instructin (please see page #) culd be rather useful D nt hesitate t send us an t: inf@vshldingcm fr any additinal infrmatin, delivery schedule and prices Thank yu, ladimir A Shvartsman, PhD President & CEO _Shvartsman@vshldingcm Data Sheet 7, Page Made in USA

3 Electrnic Design & Research Technlgy fr peple's ideas Features: Push-pull utput stage fr up t, A peak Wide Analg Signal Range +/-, Chpping frequencies up t KHz Lw ON resistance (MOSFET) Millihms Lw ce saturatin (IGBT) average High Current Capability, AC/DC switching: DS-package up t A DS-package up t 7 A Custm packaging up t A Available -- Unidirectinal and bi-directinal relays/switches, r fr a DC r AC pwer Available SPDT ( pins) and DPST (NO/NC r pins) Shrt prpagatin delay input-utput ns Try-state utputs input flating Break-Befre Make Delay (Typ) ns Fast Switching Actin: Tn ns Tff ns TTL, CMOS and LMOS Cmpatible Three-State PWM input fr OFF/OFF utput terminals Single Pwer Supply DC, DC r DC Fussy Lgic Input: ON fr NO -7 ON fr NO - High input-utput islatin,7 The T family f Relays/Switches Islated, SPDT/DPST, break-befre-make switches Designed t switch a DC-MHz signal in nansecnds Fuzzy-lgic cntrlled relays ffered with a varius utput vltage and current t satisfy many industrial applicatins, up t relays made with MOSFET s and up t with IGBT The T family als features a three-state PWM input that wrks well tgether with mst multiphase PWM cntrllers Sht-thrugh prtectin is integrated t prevent bth utputs frm cnducting simultaneusly The T relay des the best interfaces with three-state lgic Applicatins: Bi-directinal switch ½ bridge driver fr AC and DC mtrs ide signal terminatin High Energy pulse frmatin Tw relays cmbined fr H-bridge driver High pwer, High frequency driver Latch and High-speed slenid driver High Energy, Bi-plar pulse frmatin A switch fr redundant supply systems High Frequency Analg Switch Audi Switching Autmatic Test Equipment Cmmunicatin Systems Analg Selectr Switch AC and DC pwer switch Audi Signal Multipleing Serv-Mtr driver Pulse-Width mdulatin High Frequency Cnverters High Input ltage Cnverters Flash-lamp supply fr pumping slid-state laser Driver fr a pwerful IGBT and large mdules Plasma and Electrstatic Paint The EDR s Slid State Relays (SSR) use prprietary and unique design t deliver fast, reliable, bunce-free switching in a cmpact SIP package They are an ideal slid-state replacement fr large reed and electrmechanical (EM) relays Cmpared t this ld electrmagnetic technlgy, the EDR s SSRs ffer significantly lwer drive current, small package size, superb speed, high pwer DC cmmutatin, n susceptibility t magnetic interactin and slid state reliability All f these are key requirements fr the design f tday s cmple lw-pwer, fast and lng-lasting prducts EDR s family f T type Slid State Relays/Switches designed fr speed, the TSD and mre pwerful T7SD relays/switches have the capacity t efficiently switch DC r AC and can deliver a single lesser than 7 µs pulse width The T family SSR, a half-bridge MOSFET/IGBT driver is designed t perate at frequencies up t KHz ( KHz PWM fr % t % duty cycle) and is an ideal chice fr high-speed applicatins such as mtr cntrl, SMPS (switch mde pwer supplies), laser dide driver r a high frequency ultrasund cleaner The T relay/switch can be used in pairs fr a full-bridge peratin, r triplets in three-phase brushless DC mtr driver applicatins A MHz relay/switch is als available with ability t deliver a pwerful a > ns pulse Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

4 The EDR s family f the T relays Functinal diagrams f the T family EDR s slid-state relays cmbined ur state-f-the-art SIP, SIP7 and SIP9 (a custm and with screw-type terminals enclsures are available) encapsulated, vertical-cnstructin packaging with high perfrmance t give ur custmers a reliable prduct with a significant saving in bard space cmpare t ther relays EDR rates relays by the maimum current and n heat sink required We believe that remves cnfusin abut relay capability, cst and space requirements Belw is a functinal diagram f the T family and we supply relays with any reasnable vltage and current We can supply relays with any reasnable vltage and current specificatins It is a FORM C r SPDT relay TGvvvDaa A D is fr DC nly applicatins vvv shuld be replaced with a required vltage, aa shuld be replaced with a required current DUAL OUTPUT CONERTER LOGIC & SHOOT-THROUGH PROTECTION FUNCTIONAL DIAGRAM hc lc hc lc LOGIC SW SW /cc OFF OFF OFF ON ON OFF LOGIC DIAGRAM It is a FORM A&B (NO & NC) r DPST/SPDT -- TGvvvDaa and DGvvvDaa DUAL OUTPUT CONERTER hc lc hc LOGIC DIAGRAM vvv shuld be replaced with a required vltage, aa shuld be replaced with a required current 7 LOGIC & SHOOT-THROUGH PROTECTION FUNCTIONAL DIAGRAM lc LOGIC SW SW /cc OFF OFF OFF ON ON OFF hc It is a FORM C r SPDT relay TGvvvAaa A is fr DC and AC applicatins DUAL OUTPUT CONERTER LOGIC & SHOOT-THROUGH PROTECTION lc hc vvv shuld be replaced with a required vltage, aa shuld be replaced with a required current lc LOGIC SW SW /cc OFF OFF OFF ON ON OFF LOGIC DIAGRAM FUNCTIONAL DIAGRAM It is a FORM A&B (NO & NC) r DPST relay -- TGvvvAaa and TGvvvAaa/ A A is fr a dual either DC r AC applicatins 7 DUAL OUTPUT CONERTER LOGIC & SHOOT-THROUGH PROTECTION hc lc hc LOGIC DIAGRAM vvv shuld be replaced with a required vltage, aa shuld be replaced with a required current FUNCTIONAL DIAGRAM lc LOGIC SW SW /cc OFF OFF OFF ON ON OFF CAUTION: These devices are sensitive t electrstatic discharges; fllw prper IC Handling Prcedures ---EDR (fr sales) r -9- ; EDR and SHOLDING are a register trademarks f S Hlding Inc, 9 and 99 respectively All Rights Reserved Data Sheet 7, Page Made in USA

5 Typical applicatins The EDR s family f the T relays SIGNAL SQ +DC SIGNAL SQ SW +DC SW U +DC SSR DFvvTD A FORM C r SPDT relay TGvvvDaa can be use as a general-purpse mtr driver with a dual-pwer supply Capable f perating in etremely harsh envirnments, this device can withstand high ambient temperature, utput verlad, and repeated pwer supply transient vltages withut damage The relay can be used in triplets in three-phase brushless DC mtr-driver applicatins MO M +Pwer -Pwer C C BT BT +DC SSR DFvvTD SSR DFvvTD +Pwer SIGNAL SQ +DC SW C BT SIGNAL SQ +DC U MO M +DC U SW -Pwer EDR s T relays used in pairs t drive bth windings f a biplar stepper mtr r bi-directinal cntrl fr full-bridge peratin with a single-utput pwer surce +Pwer SIGNAL SQ +DC SW U +DC SSR DFvvTA Rcurrent SSR DFvvTA +DC C feed-back +DC Stepper-Mtr Driver +DC AC Surce SSR DGvvTA S U BT U SIGNAL SQ SW -Pwer DC/AC t DC Pwer Cnverter LOAD S BT +DC AC and DC pwer management in systems with a battery back-up Data Sheet 7, Page Made in USA

6 The EDR s family f the T relays G Cntrl Signal Typical applicatins (cn t) +Pwer +DC LOAD SSR DGvvTD R7 K U T C R C K S -Pwer +DC Lw-nise, high-pwer driver fr cnverter and high frequency ultrasunds BT BT + + +DC SSR DFvvTA BT - 7 SIGNAL SQ U BT LOAD S +DC - Generating a high-speed, bi-plar signal fr electrstatic painting, plasma and etching DFT IRGBT DFvvTD Q NPN BCE -in COM +in + R PAU- -ut GND COM +in +ut R Drive fr a pwerful, high-speed IGBT and bi-plar transistr EDR s the T family f cst-effective Slid State Relays/Switches has pened endless pssibilities and especially significant in view f the increased use f micrprcessr-based cntrls The simplicity f interfacing f a micr-level f cntrlling pwer with a multi-kilwatt lad gives an engineer the tl fr designing tday and tmrrw s equipment EDR s high-speed relay/switches are cmpatible with many direct driving integrated devices and input-utput galvanic islatin has made them imprtant and valuable cmpnents in new designs Electrnic Design & Research is the frnt-runner in develping slid-state relays and breakers Since 99, we cnsistently ffer superir devices t a grwing custmer based Frm lwcst DL-type relays t a sphisticated S9PA//NN, an intelligent breaker, EDR ffers pwer devices t meet yur frward-lking prject requirements Data Sheet 7, Page Made in USA

7 The EDR s family f the T relays SPDT Relays/Switches with a fuzzy-lgic cntrl input A unique feature f the T type relay/driver is a fuzzy-lgic cntrl The cntrl input designed fr the maimum applicatin fleibility and simplicity in interfacing It is a high impedance input and any CMOS lgic can be used t cntrl it The best result can be btained with tri-state utput lgic, like bus-driver IC chips r CPUs The cntrl input has three defined levels, as that can be seen n the figure, belw: -7, 9-, and - That vltage variatin allws targeting cntrl any ne f terminals r turn OFF the driver (terminals) all tgether If the cntrl signal remains within the shutdwn windw (9-), the utputs (pins, and ) are disabled (NO/NO) When the cntrl signal mves n either side f the shutdwn windw, it is belw 7, r abve, the pair f terminals - and - will change a state frm NO t NC respectively Otherwise, the cntrl signal s rising and falling threshlds utline in the Electrical Specificatins determine when the lwer and upper gates are enabled =m,=m,=7m - 7 Jan : Figure shws a cntrl signal (upper r blue) and a vltage n a lad (belw r red) When a cntrl signal (a tth-wave was selected fr a better illustratin) rises abve it enables ne pier and when it falls blw ther pair f terminals cnducts =ns,=ns,=ns Jan : - Figure shws break-befre-make prperties f the T type driver The dead time f that driver is abut ns and it set during the prductin Duratin f the dead time varies and selected based n a pwer prperty A high-pwer and high-vltage switches have the dead time as lnger as ms All vide-switches and lw pwer drivers have the dead set at abut ns Please let us knw if the dead time is yur cncern and what is required Data Sheet 7, Page Made in USA

8 Electrnic Design & Research EDR9 - DC/AC, A High speed SPDT Relays/Switches Technlgy fr peple's ideas Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t A pulse in a miniature package High sensitivity, even at high switching frequencies Input Specificatins: A surge current and nly Ohms n-state resistance Input Cntrl ltage (pin ) see page # Nminal Current ma Please specify pwer supply and cntrl vltage Pwer Supply +cc (pin ) see the rder page fr selectin Output Specificatins: Operating DC vltage range DC p-p Maimum cntinuus current 9 Arms Maimum surge current (IDM) - ms A Cntinuus current (ID) A Maimum n-state resistance Ohm Rising time 7 µs Delay-n time µs Falling time 7µS Delay-ff time 9 µs Maimum switching frequency KHz * Test perfrmed with a DND/ General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput - C t 7 C - C t C,AC Mechanical Specificatins: Weight (z) Encapsulatin Epies Etc -RFR / -CFR 7" ( mm) " (mm) Islated, a break-befre-make switches The EDR9 (TFA/) belngs t the T family f a fuzzy-lgic cntrlled relays ffers needed fleibility that required in many industrial applicatins =-9ns,=-9ns,=-99ns - - A sample f chpping f MHz, signal - Cntrl Lad wwwvshldingcm G +cc +CS EDR9/ TFA// A, DC NO COM NO "( mm) (mm) " (mm) " (mm) ( mm) All Dimensins are in inches (millimeters) Dimensins fr SIP package H 7 L W Terminals /slder fr SIP package cntrl -, pwer PIN : NO PIN : COM PIN : NO " (9 mm) PIN : + Cntrl Signal PIN : + cc PIN GND " (7 mm) DFT Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bidirectinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

9 Electrnic Design & Research Technlgy fr peple's ideas Input Specificatins: Input Cntrl ltage (pin ) see page selectin Nminal Current ma Pwer Supply +cc (pin ) see the rder page fr selectin Output Specificatins: Operating DC vltage range DC Maimum cntinuus current A rms at KHz Maimum cntinuus current A rms at KHz Maimum surge current (IDM) - ms A Cntinuus current (ID) A Maimum ce 9 Rising time µs Delay-n time µs Falling time µs Delay-ff time µs Maimum switching frequency KHz General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput - C t C - C t C,AC Mechanical Specificatins: Weight (z) Encapsulatin Epies Etc -RFR / -CFR Heat Sink Pwerful Fast, Slid-State ½ Driver DC, A, KHz ½ driver/swirhc Designed t deliver KW f pwer in a micrsecnd Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t a A pulse at µs pulse r KHz High sensitivity, even at high switching frequencies At A current nly 9 ce saturated A pulse and A cntinuusly at C Please specify pwer supply and cntrl vltage =9ns,=ns,=9ns - - Pulse train (frequency) abut KHz - Cntrl Lad TFD/ EDR9/ wwwvshldingcm A, DC G +cc GS/F - C + PIN : + LOAD, + PIN : cmmn LOAD, C PIN : - LOAD, - " (9 mm) PIN : Cntrl Signal, CS/F PIN : +cc PIN : Pwer Supply return, GND 7 (mm) (mm) " (mm) " (mm) ( mm) ( mm) " (7 mm) All Dimensins are in inches (millimeters) Dimensins fr SIP package H 7 L W Terminals /slder fr SIP package cntrl -, pwer Pulse width ns, A - 7 Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bi-directinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA =7ns,=ns,=-ns -

10 Electrnic Design & Research EDR9 - DC, A High speed SPDT Relay// Bridge Driver Technlgy fr peple's ideas Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t A pulse in a miniature package High sensitivity, even at high switching frequencies Input Specificatins: 9 A surge current and nly Ohms n-state resistance Input Cntrl ltage (pin ) see page # Nminal Current ma Please specify pwer supply and cntrl vltage Pwer Supply +cc (pin) see the rder page fr selectin Output Specificatins: Operating DC vltage range DC Maimum cntinuus current Arms rms Maimum surge current (IDM) - ms 9 A Cntinuus current (ID) - Pulsed A Maimum n-state resistance Ohm Rising time 7 µs Delay-n time µs Falling time 7µS Delay-ff time 9 µs Maimum switching frequency 7 KHz All specificatins were giving withut any heatsink at rm temperature General Specificatins: Ambient perating temperature range - C t 7 C Ambient strage temperature range - C t C Dielectric Strength input-t-utput,ac Mechanical Specificatins: Islated, a break-befre-make switches The EDR9 (TFD/) belngs t the H family f a fussy-lgic cntrlled relays ffers needed fleibility that required in many industrial applicatins Weight (z) A sample f driving a lad at KHz Encapsulatin Epies Etc -RFR / -CFR 7" ( mm) " (mm) PIN : NO PIN : COM PIN : NO EDR9/ PIN : Cntrl Signal (CS) TFD/ " (9 mm) PIN : Enable (EN) wwwvshldingcm PIN : + DC A, DC PIN 7 GND 7 NO COM NO " (7 mm) DFET =99ns,=9ns,=977ns - Jan : Cntrl Lad "( mm) (mm) " (mm) " (mm) ( mm) All Dimensins are in inches (millimeters) Dimensins fr SIP7 package H 7 L W Terminals /slder fr SIP7 package cntrl -, pwer 7 Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bidirectinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

11 Input Electrical Characteristics (Ta = C) fr TFA/, p/n EDR9/ Characteristic Test Cnditin Min Typ Ma Unit Cntrl ltage, lw level threshld 7 Cntrl ltage, high level threshld Enable (EN) threshld (pin ) Input Current ma Input Electrical Characteristics (Ta = C) Pwer Supply (pins ), cc ( ma maimum) 9 Maimum cc current at DC KHz ma Maimum cc Current at 7 KHz ma Switching time test Lad Ohm & A =ns,=ns,=-79ns Jan : Cntrl Lad Jan : Figure Turn -n delay is 79 ns Figure Turn-ff delay is 77 ns =7ns,=99ns,=-77ns Cntrl Lad =9ns,=7ns,=-ns =7ns,=9ns,=ns - - Cntrl - - Cntrl Lad Lad Jan : - - Jan : - Figure Rising Time is ns Figure Fall Time is ns FUNCTIONAL TABLE EN CS NO NO L X OFF OFF H OFF OFF H ON OFF (CS) ENABLE (EN) +DC 7 TFD CO NT RO L NO NO LOAD C9 C7 + BT BT H OFF ON C C - Fig Switching Time Test Circuit The enable is cnnected t +DC via a K resistr and can be left flating Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

12 Functin Table f the EDR9 INPUT (cntrl, pin ) Output terminals - Output terminals - X OFF OFF - ON OFF - OFF OFF - OFF ON Switching time test: Pwer is +DC r +/-DC, a nn-inductive lad is Ohm & A =-ns,=ns,=-ns ch A: Frequency (MHz) Nt enugh data =-9ns,=-ns,=-99ns ch A: Frequency (MHz) Nt enugh data Maimum turn n delay is ms Rising slp is nly 99 ms =ns,=ns,=-ns ch A: Frequency (MHz) Nt enugh data Turn-ff delay is ms =-7ns,=ns,=ns ch A: Frequency (Hz) Nt enugh data Test f the time-delay with a bi -plar pwer - - =ns,=ns,=ns ch A: Frequency (Hz) Nt enugh data - - =ns,=99ns,=7ns ch A: Frequency (Hz) Nt enugh data The dead time is set t abut ns fr that particular part Please cntact us if yu wuld need a shrter r lnger delay - - =ns,=ns,=ns ch A: Frequency (Hz) Nt enugh data =ns,=ns,=ns ch A: Frequency (Hz) Nt enugh data Data Sheet 7, Page Made in USA

13 DC, A, KHz, ½ driver/switch Electrnic Design & Research Technlgy fr peple's ideas Input Specificatins: Input Cntrl ltage (pin ) see specificatins Nminal Cntrl Signal Current ma Pwer Supply +cc (pin ) see the rder page fr selectin Output Specificatins: Operating DC vltage range t + DC Maimum cntinuus current A rms at KHz Maimum cntinuus current A rms at KHz Maimum surge current (IDM) - ms A Cntinuus current (ID) A Pulsing current A Maimum resistance 7 Ohm Rising time 7 ns Delay-n time 7 ns Falling time (depended n a lad) 7 ns ( Ohm) Delay-ff time ns Maimum switching frequency KHz General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput - C t C - C t C,AC Mechanical Specificatins: Weight (z) Encapsulatin Epies Etc -RFR / -CFR Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t a A pulse at µs pulse High sensitivity, even at high switching frequencies A pulse and A cntinuusly at C Please specify pwer supply and cntrl vltage =7ns,=ns,=77ns ch A: Frequency (khz) 7 Pulse train (frequency) at KHz Cntrl Lad TFD/ EDR/ wwwvshldingcm A, +/-DC G +cc GS/F - C + PIN : + LOAD, +, PIN : cmmn LOAD, C PIN : - LOAD, -, " (9 mm) PIN : Cntrl Signal, CS/F PIN : +DC PIN : Pwer Supply return, GND 7 (mm) (mm) " (mm) " (mm) ( mm) ( mm) All Dimensins are in inches (millimeters) Dimensins fr SIP package H 7 L W Terminals /slder fr SIP package cntrl -, pwer " (7 mm) A single Pulse ns - - =ns,=ns,=ns ch A: Frequency (Hz) Nt enugh data Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nninductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bi-directinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

14 Input Electrical Characteristics (Ta = C) fr TFD/, p/n EDR/ Characteristic Test Cnditin Min Typ Ma Unit Cntrl ltage, lw level threshld 7 Cntrl ltage, high level threshld Input Current ma Input Electrical Characteristics (Ta = C) Pwer Supply (pins ), cc ( ma maimum) 9 Maimum cc current at DC KHz ma Maimum cc Current at KHz ma Switching time test: Lad Ohm & A =-ns,=ns,=ns =-ns,=ns,=9ns ch A: Frequency (Hz) Nt enugh data ch A: Frequency (Hz) Nt enugh data - Turn-n delay is ns Turn-ff delay is 9 ns =ns,=-77ns,=ns =99ns,=ns,=9ns ch A: Frequency (Hz) Nt enugh data ch A: Frequency (Hz) Nt enugh data Turn-n delay is ns Turn-ff delay is 9 ns =-ns,=-9ns,=ns =ns,=ns,=7ns ch A: Frequency (khz) ch A: Frequency (khz) 9 A dead zne n the rising frnt is ns Dead zne n the falling frnt 7 ns =-9ns,=ns,=7ns ch A: Frequency (Hz) Nt enugh data - =-7ns,=-77ns,=7ns ch A: Frequency (Hz) Nt enugh data Rising slpe is 7 ns A free Falling slpe is 7 ns Time depended n the lad impedance Data Sheet 7, Page Made in USA

15 EDR7 -- DC, A, KHz ½ driver/switch Fuzzy-lgic input high pwerful driver Electrnic Design & Research Technlgy fr peple's ideas Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t a A pulse at µs pulse High sensitivity, even at high switching frequencies Fuzzy-lgic input allws individual cntrl f each pair f utputs Input Specificatins: Input Cntrl ltage (pin ) Nminal Current Pwer Supply +cc (pin ) Output Specificatins: see rdering page ma see the rder page fr selectin Operating DC vltage range DC Maimum cntinuus current A rms at KHz Maimum cntinuus current A rms at KHz Maimum surge current (IDM) - ms A Cntinuus current (ID) 9A Pulsing current A Maimum resistance Ohm Rising time µs Delay-n time µs Falling time 9µS (Ohm lad) Delay-ff time µs Dead time (it can be set t any) µs (please request a different) Maimum switching frequency KHz General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput - C t C - C t C,AC Mechanical Specificatins: Weight (z) Encapsulatin Epies Etc -RFR / -CFR Please specify pwer supply and cntrl vltage =,=9ns,= ch A: Frequency (khz) 7 Pulse train (frequency) abut 7 KHz Cntrl Lad TFD/ EDR7/ wwwvshldingcm A, DC G +cc GS/F - C + 7 (mm) (mm) " (mm) " (mm) PIN : + LOAD, + PIN : cmmn LOAD, C PIN : - LOAD, - " (9 mm) PIN : Cntrl Signal, CS/F PIN : +DC PIN : Pwer Supply return, GND ( mm) ( mm) " (7 mm) All Dimensins are in inches (millimeters) Dimensins fr SIP package H 7 L W Pulse-width Terminals /slder fr SIP package cntrl -, pwer ch A: Frequency (khz) Nt enugh data Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nninductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bi-directinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA =ns,=ns,=ns

16 7DC/AC, A, KHz ½ driver/switch Electrnic Design & Research Technlgy fr peple's ideas Input Specificatins: Input Cntrl ltage (pin ) Nminal Current Pwer Supply +cc (pin ) Output Specificatins: see ma see the rder page fr selectin Operating DC vltage range +/-7DC (AC) Cntinuus current (DC- KHz) A rms Cntinuus current (at KHz) A rms Maimum surge current (IDM) - ms A Cntinuus current (ID) A at C Pulsing current 7A Maimum resistance Ohm Rising time 9 µs Delay-n time, µs Falling time 9µS ( Ohm) Delay-ff time µs Maimum switching frequency KHz General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput - C t C - C t C,AC Mechanical Specificatins: Weight (z) Encapsulatin Epies Etc -RFR / -CFR Features: Utilizes nly sq in f PCB area and nly tall A cntinuusly r up t a 7A pulse at µs pulse High sensitivity, even at high switching frequencies A pulse and A cntinuusly at C Please specify pwer supply and cntrl vltage =7ns,=,=9ns - - ch A: Frequency(kHz) ch B: Frequency(kHz) Dec7 : Pulse train (frequency) abut KHz Cntrl Lad TF7A/ EDR7/ wwwvshldingcm A 7DC/AC G +cc GS ~ C ~ 7 (mm) PIN : + LOAD, ~ PIN : cmmn LOAD, C PIN : - LOAD, ~ " (9 mm) PIN : Cntrl Signal, CS PIN : +DC PIN : Pwer Supply return, GND " =7ns,=,=9ns (mm) " (mm) " (mm) - - ( mm) ( mm) All Dimensins are in inches (millimeters) Dimensins fr SIP package H 7 L W Terminals /slder fr SIP package cntrl -, pwer ch A: Frequency(kHz) ch B: Frequency(kHz) Dec7 : Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nninductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bi-directinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

17 Input Electrical Characteristics (Ta = C) fr TF7A/, p/n EDR7/ Characteristic Test Cnditin Min Typ Ma Unit Cntrl ltage, lw level threshld 7 Cntrl ltage, high level threshld Input Current ma Input Electrical Characteristics (Ta = C) Pwer Supply (pins ), cc ( ma maimum) 9 Maimum cc current at DC KHz ma Maimum cc Current at KHz ma Switching time test Lad Ohm & A =ns,=ns,=ns =ns,=ns,=ns Dec7 : ch A: Frequency(Hz) Nt enugh data ch B: Frequency(Hz) Nt enugh data Dec7 : Turn-n delay is ns Turn-n slpe (Tr) is ns (dual supply) =7ns,=ns,=9ns =ns,=ns,=ns Dec7 : Dec7 : - A dead zne n the rising frnt is 9 ns Turn-n slpe (Tr) is ns (single supply) =ns,=ns,=ns =ns,=7,= Dec7 : Dec7 : - Dead zne n the falling frnt ns An eample f chipping high-frequency Data Sheet 7, Page Made in USA

18 Electrnic Design & Research Technlgy fr peple's ideas Input Specificatins: Input Cntrl ltage (pin ) see page # Nminal Current ma Pwer Supply +cc (pin) see the rder page fr selectin Output Specificatins: EDR7 - DC, 7A High speed, / Bridge Driver Fast, pwerful break-befre-make switch Operating DC vltage range - DC Rated current, n heatsink 7 Arms rms Current with a heatsink A Maimum surge current (IDM) - ms A Cntinuus current (ID) - A Maimum n-state resistance Ohm Rising time 7 µs =79ns,=ns,=ns Delay-n time µs Falling time 7µS Delay-ff time 9 µs - Maimum switching frequency KHz All specificatins were giving withut any heatsink at rm temperature General Specificatins: Ambient perating temperature range - C t 7 C - Ambient strage temperature range - C t C - Dielectric Strength input-t-utput,ac ch A: Frequency (khz) Mechanical Specificatins: Oct : Weight (z) Encapsulatin Epies Etc -RFR / -CFR A sample f driving a lad at KHz () The EDR7 (T7GD7) belngs t the T family f a fuzzy-lgic cntrlled relays ffers needed fleibility that required in many industrial applicatins Features: Utilizes nly sq in f PCB area and nly tall 7A cntinuusly r up t A pulse in a miniature package High sensitivity, even at high switching frequencies A surge current and nly Ohms n-state resistance Cntrl Lad EDR7 T7GD7 PIN : +OUT PIN : COM PIN : -OUT PIN : Cntrl Signal (CS) PIN : Enable (EN) PIN : +dc 7 () PIN 7 GND 7 All Dimensins are in inches (millimeters) Dimensins fr SIP7 package Output Terminals H 7 L W screw types Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bidirectinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

19 Input Electrical Characteristics (Ta = C) fr T7GD/, p/n EDR7/ Characteristic Test Cnditin Min Typ Ma Unit Cntrl ltage, lw level threshld 7 Cntrl ltage, high level threshld Enable (EN) threshld (pin ) Input Current ma Input Electrical Characteristics (Ta = C) Pwer Supply (pins ), cc ( ma maimum) 9 Maimum cc current at DC KHz ma Maimum cc Current at 7 KHz ma Switching time test Lad Ohm & A =ns,=ns,=-79ns =7ns,=99ns,=-77ns Jan : Cntrl Lad Jan : Cntrl Lad Figure Turn -n delay is 79 ns Figure Turn -ff delay is 77 ns =9ns,=7ns,=-ns - Cntrl Lad =7ns,=9ns,=ns - Cntrl Lad - - Jan : Jan : - Figure Rising Time is ns Figure Fall Time is ns FUNCTIONAL TABLE EN CS NO NO L X OFF OFF H OFF OFF H ON OFF (CS) ENABLE (EN) +DC DFET 7 CO NT RO L NO NO LOAD C9 C7 + BT BT H OFF ON C C - Fig Switching Time Test Circuit The enable is cnnected t +DC via a K resistr and can be left flating Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

20 Electrnic Design & Research Technlgy fr peple's ideas Input Specificatins: Input Cntrl ltage (pin ) Nminal Current Pwer Supply +cc (pin ) Output Specificatins: see rder page ma see the rder page fr selectin Operating DC vltage range -- DC Maimum cntinuus current A Maimum surge current (IDM) - ms A Cntinuus current (ID) 7 A Maimum n-state resistance 7 Ohm Rising time µs Delay-n time µs Falling time µs Delay-ff time µs Maimum switching frequency Hz Dead Time ms General Specificatins : Ambient perating temperature range Ambient strage temperature range Dielectric Strength input-t-utput Mechanical Specificatins: Weight (z) EDR77 - DC, A SPDT Relay - C t C - C t C, AC Encapsulatin Epies Etc -RFR / -CFR A sample f chpping f a bi-plar pwer wwwvshldingcm G +dc +CS " (mm) " (mm) EDR77/7 TLD/ - A, DC NC COM N,O PIN : NO (nrmal pen) PIN : COM PIN : NC (nrmal clse) " PIN : + Cntrl Signal PIN : + dc (-) PIN GND " "( mm) (mm) " (mm) " All Dimensins are in inches (millimeters) Dimensins fr SIP package H L W Terminals /slder fr SIP package cntrl -, pwer The EDR77 is a lw cst and belngs t the family f a DC & AC/DC a subminiature ½ drivers, and analg switches Features: Utilizes nly 7 sq in f PCB area and nly tall A cntinuusly current and n heat sink is required up t A pulse in a miniature package CMOS input 7A is a maimum cntinues current and nly Ohms n-state resistance Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bidirectinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm =9,=-7,= Apr : ms DLT Cntrl Lad Data Sheet 7, Page Made in USA

21 Input Electrical Characteristics (Ta = C) fr TLD, p/n EDR77 Characteristic Test Cnditin Min Typ Ma Unit Cntrl vltage range +dc 7 Maimum Turn-On ltage, dc=dc Maimum Turn-Off ltage, dc=+dc Input Current < ma Input Electrical Characteristics (Ta = C) fr TLD, p/n EDR Pwer Supply, cc 7 Pwer Supply Current ma Switching time test, DC & 7A; Lad Ohm, vltage attenuatin : =-,=7,=977 Cntrl =9,=,=9 Cntrl Lad Lad ms Apr : ms Apr : Figure Turn-n delay is ms Figure Turn-ff delay is ms =,=9,= =7,=,= ms Apr :9 Cntrl Lad ms Apr : Cntrl Lad Figure Rising Time is µs Figure Fall Time is µs + + +DC SSR DLvvTD BT - 7 SIGNAL SQ U BT LOAD S +DC - Figure Switching unsymmetrical bi-plar pwers Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

22 Electrnic Design & Research Technlgy fr peple's ideas, EDR9 Input Specificatins: Input Cntrl ltage (pin ) see page # Nminal Current ma/dc Pwer Supply +cc (pin) see page # Output Specificatins: Operating vltage range (p) --, DC Maimum cntinuus current Arms rms Maimum surge current (IDM) - ms A Cntinuus current (ID) - Pulsed A Maimum n-state resistance Ohm Rising time ns Delay-n time ns Falling time 9 ns Pulse width range 7 ns t infinity Maimum switching frequency KHz All specificatins were giving withut any heat sink at rm temperature General Specificatins: Ambient perating temperature range - C t C Ambient strage temperature range - C t C Dielectric Strength input-t-utput,ac Mechanical Specificatins: NanSecnds rise/fall time, High-ltage push-pull switches A switch belngs t the family f push-pull switches cnsists f tw alternately cntrlled slid-state switches, which in turn are made up t a large number f high-speed MOSFETs islated each ther cnnected in series The rise and fall times at the switch utput are virtually the same and that allw generating an etremely precise, high-vltage, true square-wave pulses Applicatins: Replacement f thyratrns, ignitrns, cld cathde tubes, electrn tubes, spark gaps and electrmechanical high-vltage relays Pulsed particle acceleratr/deflectin Mass spectrmetry & high energy physics Radar and micrwave mdulatin Laser electrnics and electr-ptics Medical shck wave generatrs Weight (z) A sample f MHz burst frequency Encapsulatin Epies Etc -RFR / -CFR =9ns,=ns,=-9ns - 7 Aug : - Cntrl Lad 7" ( mm) " (mm) PIN : NO PIN : COM PIN : NO EDR9/ PIN : Cntrl Signal (CS) TFD/ " (9 mm) PIN : Enable (EN) wwwvshldingcm PIN : + DC A, DC PIN 7 GND 7 NO COM NO "( mm) (mm) " (mm) " (mm) ( mm) All Dimensins are in inches (millimeters) Dimensins fr SIP7 package H 7 L W Terminals /slder fr SIP7 package cntrl -, pwer " (7 mm) 7 F T DC/D C CO NT RO L Transient Prtectin: All lads are inductive, even nes that are nt s bvius r labeled An inductive lad prduces a harmful transient vltage, which is much higher than the applied vltage, when it is turned n and ff A SSR built with a MOSFET utput acts as an ideal switch and can prduce a seemingly nn-inductive lad, which can cause damage if nt suppressed A transient vltage suppressr, which is bidirectinal fr AC applied vltage and unidirectinal fr DC applied vltage, shuld be used t clamp ecessive spikes Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

23 Input Electrical Characteristics (Ta = C) fr TFD/, p/n EDR9/ Characteristic Test Cnditin Min Typ Ma Unit Cntrl ltage, lw level threshld 7 Cntrl ltage, high level threshld Enable (EN) threshld (pin ) Input Current ma Input Electrical Characteristics (Ta = C) Pwer Supply (pins ), cc ( ma maimum) 9 Maimum cc current at DC KHz ma Maimum cc Current at KHz ma Switching test +/-, Lad Ohm & A =ns,=ns,=ns - Cntrl Lad =9ns,=ns,=-ns - - Cntrl Lad Aug : Aug : - Figure Turn -n delay is ns Figure Turn-ff delay is ns =ns,=ns,=ns =ns,=ns,=-ns - Cntrl - Cntrl Lad - - Lad Aug : Aug : - Figure Rising time is ns Figure Fall time ns Figure Rising Time is ns Figure Fall Time is ns FUNCTIONAL TABLE EN CS NO NO L X OFF OFF H OFF OFF H ON OFF H OFF ON (CS) ENABLE (EN) 7 +DC FT CO NT RO L NO LOAD NO C9 C7 + BT BT C C - Fig Switching Time Test Circuit A switch can be cntrlled via the enable (EN) input ( L / H ), if nly + r - pwer needs t be applied n a lad, r via the cntrl (CS) when a biplar pwer must applied nt the lad Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; vshlding@vshldingcm Data Sheet 7, Page Made in USA

24 Test Circuit fr frming a fast rising/falling pulse Figure Basic applicatin fr generating varius plarity pulses Figure 7 Test Circuit fr generating a single plarity pulse NOTES: Wiring shuld be as shrt as pssible Capa citr Cp shuld be at least times f Cl fr shrtest transitin times Cnnected in series resistrs R and R used fr dumping and shrt prtectin All measurements refer t Ohm Accrding t a specific applicatin, resistrs can be between (zer) and Mhm and shuld be selected the highest pssible t avid ringing A lw impedance linkage between lgic GND and earth is very imprtant fr interference free peratin with a high switching speed A sample f TF- relays/switches fr and high with similar specificatins Mdel Number Package p Ir (A) avg Id (A) Idm (A) Enb p/n TFD SIP7 -- DC M 9 Y EDR TFD SIP -- DC M 9 N EDR TFA SIP +/-DC (7AC) M 9 N EDR9 TFA SIP +/-DC (7AC) M N EDR9 TFD SIP -- DC M N EDR TFD SIP7 -- DC M Y EDR9 TFD SIP DC M N EDR TFA SIP +/-DC (AC) M N EDR TFD SIP DC M N EDR TFA SIP +/-DC (7AC) M N EDR TFD SIP DC I N EDR9 TFD SIP DC I N EDR Please call fr ther parts, with a different vltage and current We d nt charge any set-up fee even if yu wuld need a ne switch if utput MOSFETs culd be use in the same design Data Sheet 7, Page Made in USA

25 Electrnic Design & Research Technlgy fr peple's ideas P/N EDR99 is a fuzzy lgic DIN-driver Designed fr DG-, DF- and DS- families relays/switches EDR s DIN-driver designed fr varius industrial applicatins and easy interfaced with a PLC, I/O cards and cntrl switches The DIN RAIL is especially useful with a high-speed Slid State Relay, and a high pwer analg switch applicatins, as a ½ r a full (H) bridge driver The EDR99/B designed t driver tw and EDR99/F drives fur f EDR s DGand DF-types relays in a ½ and H-bridge (full bridge) cnfiguratins It used as a pwerful analg, high frequency switch t prvide a break-befre-make cmmutatin The EDR99 is a high frequency driver and ptimized t drive tw r fur Slid State Relays in the breakbefre-make synchrnized sequences EDR has made switches and the EDR99 allws creating a A rms driver The EDR99 als features a three-state PWM input will prevent a negative transient n the utput vltage when the input is being shut dwn The EDR99 has the capacity t switch efficiently at frequency up t KHz The DIN RAIL has an internal lgic circuitry that prevents sht-thrugh current even at a high switching frequency A dead time is adjustable by tw capacitrs, ne f each cycle The timing culd the same r different based n the value f each capacitr t meet variety applicatins and R&D INPUT ENABLE OUTPUT Z X st "OFF," nd "OFF" HIGH HIGH st "OFF," nd "ON" LOW HIGH st "ON", nd "OFF" X LOW st "OFF," nd "OFF" Z - flating input (9K) LM7LA OUT IN GND st Relay DF-type relay +CC - - =ns,=ns,=-ns GND +cc +DC ut ENABLE INPUT LOGIC SHOOT-THROUGH PROTECTION nd Relay DF-type relay LOAD Pwer Surce Pwer Surce p/n EDR99/B -CC Simplified schematic f the EDR99/B and a lad hk-up in a ½ bridge driver applicatin Prduct Highlights Drives tw (EDR99/B) and fur (EDR99/F) EDR s made DG and DF- types Slid State Relays/Switches Electrical islatin input/utput is r Switching frequency DC t KHz Switching current frm A till A rms Switching vltage frm till Duty cycle: % Input and enable inputs are lw pwer, CMOS Sht-Trugh Prtectin Three-State PWM Input fr Pwer Stage Shutdwn Nn f relays activates when the input if flating A single pwer supply Matching Delay Between Inverting and N-inverting utputs Fussy lgic r a three-state input allws easy cntrl f either relay The enable can be use fr PWM and sht-ff The input can be use t indented cntrl f either relay Add-n p/n EDR9 allws a precise utput pwer cntrl Applicatins Inverters A lw cst Mtr driver Cnverter Pwer engineering Laser driver and radilgy RF pwer driver Analg switch Pwer Switching Pwer-Supply Mdules ½ bridge and full-bridge driver Frmatting a bi-plar pulse Assembling a SPDT and a dual SPDT cnfiguratin Data Sheet 7, Page Made in USA

26 The DIN-driver as a full-bridge driver with fur EDR s relays INPUT ENABLE OUTPUT Z X st "OFF," nd "OFF" HIGH HIGH st "OFF," nd "ON" LOW HIGH st "ON", nd "OFF" X LOW st "OFF," nd "OFF" Z - flating input (9K) GND +cc +DC ut ENABLE INPUT LOGIC LM7LA OUT IN GND SHOOT-THROUGH PROTECTION st Relay DF-type relay nd Relay DF-type relay +CC st Relay LOAD DF-type relay nd Relay DF-type relay Pwer Surce p/n EDR99/F Simplified schematic f the EDR99/B and a lad hk-up in a full-bridge driver applicatin Functinal Pin Descriptin GND (pin ) GND is the grund pin All cntrl signal and pwer supply t relays are reference t this nde cc (pin ) Cnnect the cc pin t a + f a bias supply The cc depends n what type f relays being used It culd be DC r DC +DC utput (pin ) The +DC is the utput frm an internal vltage regulatr when +DC applied nt cc (pin) It is a lw pwer surce and can be used nly fr eternal applicatins An aggregated lad current cannt eceed ma There is n limit set fr the current if cc (pin ) is DC because it passed thrugh Enable (pin ), the lw threshld is and the high is It is a dual use cntrl (enable) input Cnnect this pin t HIGH (+DC) r left uncnnected t enable the DIN-driver The LOW is disabled the driver This input can be use fr PWM applicatins INPUT (pin), frm 7 t is ff The INPUT is the fuzzy r three-state input and cntrls utput relays An applied signal can enter three distinct states during peratin, t 7, 7 t and t cc, as it shwn n the vltage diagram belw This input can be used t reverse plarity (directin) f a DC Mtr =7m,=9m,=m Oct : - ltage-timing diagram f the INPUT signal (tp) and relays utput (bttm), fr demnstrating purpse slpes f the input signal set t a slw rise and fall transitins Data Sheet 7, Page Made in USA

27 Ordering Infrmatin EDR99//XX ** replace with B fr a tw relays t implement ½ bridge driver, and with F fr a fur relays t implement a full-bridge driver ** replace XX with a, 9,,, r with the required pwer supply (cc) The pwer supply has t be chsen by the type f relay t be installed n the DIN-driver Recmmended Operating Cnditins MIN TYP MAX Supply ltage, cc fr EDR99// DC +/-% Supply ltage, cc depended n the mdule XX +/-% Supply Current Icc, ma (n relay installed), cc=dc Ambient Temperature Range - C t 9 C Input (pin ) ma The first threshld (pin ), 7 The secnd threshld (pin ), Enable (pin ), LOW threshld, Enable (pin ), HIGH threshld, Sht-Trugh Prtectin, adjustable and set by tw capacitrs, fr pf µs Tw DG-type relays munted n the EDR99 fr a high frequency chpping Data Sheet 7, Page Made in USA

28 Selectin and Ordering Instructin fr EDR s made Slid State Mdules such as Relays, Switches, Breakers, ½ and Full-bridge Drivers, etc Ntes: During past ten years rapid develpment f new and additinal [prducts gave us n chice but t epend, mdify and unify part descriptins Belw represent the third mdificatin Our mdules descriptin will be marked accrding t the specificatins belw but p/n EDR will stay the same fr already items in circulatin (already sld) Part descriptin: H L D / / X A B C F H /E /I H-Driver size = Speed L = lw ltage = Current = DC Current = A CS= cc= X mdule type D Slid State Relay, SPST-NO and SPST-NC switches T Driver, such as ½-bridge r a SPDT relay which can wrk as a ½ driver M Driver, such as a switch with built-in PWM cntrller H Full-bridge (H-bridge) Driver C Relay with built-in de-buncing r a turn-n/ff delay B Slid State Breaker and brakes cntrl mdules A package dimensins H L 9 W H 7 L W H 7 L W H L 9 W H L W DIP, 7 H 9 L W 7 panel munt, H 7 L W DIN type enclsure, H W, fr mm DIN Rail 9 P panel munt, 7 7 B Speed - A device s ability t turn ON/OFF utput terminal(s) times per secnd L a lw speed relay/switch, rated DC - Hz, direct driving cntrl A a lw speed relay/switch, AC input relays N a medium speed relay/switch, rated DC - KHz, direct driving cntrl G a medium speed relay/switch, rated DC - KHz, lw current cntrl and pwer F a fast relay/switch, rated up t DC - KHz, lw current cntrl and pwer S a super-fast relay/switch, rated DC - MHz, lw current cntrl and pwer U a super-fast relay/switch, rated DC MHz, direct driving cntrl Fast, High ltage Slid-State Switches with Nansecnds rise time C Output ltage - A maimum allwed vltage between utput terminals, up t k It must be replace with required vltage and we ffer the clsest and highest value available Nte: In an AC -relay a vltage specified a peak-t-peak maimum vltage and the maimum AC can be calculated by multiplying a maimum allwed vltage by factr f 7 F A relay can be use t cntrl either AC, DC r AC/DC pwer A - a relay/switch designed t switch/chp an AC/DC pwer D - a relay/switch designed t switch/chp a DC pwer nne - relay with a SCR r TRIAC n the utput t cntrl nly AC pwer H A maimum allwed RMS CURRENT (Ampere) withut a heat sink A maimum current limited t a size f the enclsure (b) We can prduce a device fr any required current in a custmer enclsure I Sme f ur prducts use an internal cnverter n prvide a pwer t the internal electrnics arieties vltages are available: DC+/-%, DC+/-%, DC+/-% and DC+/-% Fr a wider input pwer vltage swing, please add W after the vltage Fr an eample, W is fr +/- E We ffer several standard cntrl vltages DC, DC, DC, DC, -DC and DC Please specify the input cntrl vltage, as fr eample DLD/ Replace with a,,,,, - and that is fr DC, DC, DC, DC, DC, -DC and DC Respectful cntrl vltage represented at the end f part number in the fllwing way, fr an eample EDR/ and EDR/ Bth relays are almst the same and difference is nly an applied cntrl vltage, if fr DC and is fr DC; Cntrl ltage Representatin Cntrl ltage Representatin Cntrl ltage Representatin DC DC DC DC DC DC -DC 7 DC 9-AC 9 Z A relay/switch built with fllwing standard islatins L r nne type relay is N type relay is, DC ( H ) and ( H ) DC T Turn-n delays; S fr secnds, M fr millisecnds, U fr micrsecnds, M ms turn-ff delay, M ms turn-n delay Electrnic Design & Research Inc ** 7 Intermdal Dr ** Luisville ** KY Tel: -9; Fa: -9-; Sales: --7; website: inf@vshldingcm Data Sheet 7, Page Made in USA