CD4518BMS, CD4520BMS. CMOS Dual Up Counters. Features. Pinout. Functional Diagram. Applications. Description. December 1992

Transcription

1 58BMS, 5BMS ecember Features High Voltage Types (V ating) 58BMS ual B Up ounter 5BMS ual Binary Up ounter Medium Speed Operation - MHz Typical lock Frequency at V Positive or Negative Edge Triggering Synchronous Internal arry Propagation % Tested for uiescent urrent at V 5V, V and V Parametric atings Maximum Input urrent of µa at 8V Over Full Package Temperature ange; na at 8V and +5 o Noise Margin (Over Full Package/Temperature ange) - V at V = 5V - V at V = V -.5V at V = V Standardized Symmetrical Output haracteristics Meets All equirements of JEE Tentative Standard No. B, Standard Specifications for escription of B Series MOS evices Applications Multistage Synchronous ounting Multistage ipple ounting Frequency ividers escription 58BMS ual B Up ounter and 5BMS ual Binary Up ounter each consist of two identical, internally synchronous -stage counters. The counter stages are -type flip-flops having interchangeable LOK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the LOK. The counters are cleared by high levels on their ESET lines. The counter can be cascaded in the ripple mode by connecting to the enable input of the subsequent counter while the LOK input of the latter is held low. The 58BMS and 5BMS are supplied in these -lead outline packages: Braze Seal IP HS Frit Seal IP HF eramic Flatpack HP HW 58B Only 5B Only Pinout LOK A ENABLE A Functional iagram MOS ual Up ounters 58BMS, 5BMS TOP VIEW A A A A ESET A VSS V ESET B B B B B ENABLE B LOK B LOK A / ENABLE A 5 ESET A 7 A A A A B LOK B / B ENABLE B B B ESET B VSS = 8 V = AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTESIL or -7-7 opyright Intersil orporation 7- File Number

2 Specifications 58BMS, 5BMS Absolute Maximum atings Supply Voltage ange, (V) V to +V (Voltage eferenced to VSS Terminals) Input Voltage ange, All Inputs V to V +.5V Input urrent, Any One Input ±mA Operating Temperature ange o to + o Package Types, F, K, H Storage Temperature ange (TSTG) o to + o Lead Temperature (uring Soldering) o At istance / ± / Inch (.5mm ±.7mm) from case for s Maximum eliability Information Thermal esistance θ ja θ jc eramic IP and FIT Package o /W o /W Flatpack Package o /W o /W Maximum Package Power issipation (P) at + o For T A = -55 o to + o (Package Type, F, K) mW For T A = + o to + o (Package Type, F, K)......erate Linearity at mw/ o to mw evice issipation per Output Transistor mw For T A = Full Package Temperature ange (All Package Types) Junction Temperature o TABLE. ELETIAL PEFOMANE HAATEISTIS GOUP A LIMITS PAAMETE SYMBOL ONITIONS (NOTE ) SUBGOUPS TEMPEATUE MIN MAX UNITS Supply urrent I V = V, VIN = V or GN +5 o - µa + o - µa V = 8V, VIN = V or GN -55 o - µa Input Leakage urrent IIL VIN = V or GN V = +5 o - - na + o - - na V = 8V -55 o - - na Input Leakage urrent IIH VIN = V or GN V = +5 o - na + o - na V = 8V -55 o - na Output Voltage VOL V = V, No Load,, +5 o, + o, -55 o - 5 mv Output Voltage VOH V = V, No Load (Note ),, +5 o, + o, -55 o.5 - V Output urrent (Sink) IOL5 V = 5V, VOUT =.V +5 o.5 - ma Output urrent (Sink) IOL V = V, VOUT =.5V +5 o. - ma Output urrent (Sink) IOL V = V, VOUT =.5V +5 o.5 - ma Output urrent (Source) IOH5A V = 5V, VOUT =.V +5 o ma Output urrent (Source) IOH5B V = 5V, VOUT =.5V +5 o ma Output urrent (Source) IOH V = V, VOUT =.5V +5 o - -. ma Output urrent (Source) IOH V = V, VOUT =.5V +5 o ma N Threshold Voltage VNTH V = V, ISS = -µa +5 o V P Threshold Voltage VPTH VSS = V, I = µa +5 o.7.8 V Functional F V =.8V, VIN = V or GN 7 +5 o VOH > VOL < V V = V, VIN = V or GN 7 +5 o V/ V/ V = 8V, VIN = V or GN 8A + o V = V, VIN = V or GN 8B -55 o Input Voltage Low (Note ) VIL V = 5V, VOH >.5V, VOL <.5V,, +5 o, + o, -55 o -.5 V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VIH V = 5V, VOH >.5V, VOL <.5V,, +5 o, + o, -55 o.5 - V VIL VIH V = V, VOH >.5V, VOL <.5V V = V, VOH >.5V, VOL <.5V. All voltages referenced to device GN, % testing being implemented.. Go/No Go test with limits applied to inputs.,, +5 o, + o, -55 o - V,, +5 o, + o, -55 o - V. For accuracy, voltage is measured differentially to V. Limit is.5v max. 7-7

3 Specifications 58BMS, 5BMS TABLE. A ELETIAL PEFOMANE HAATEISTIS GOUP A LIMITS PAAMETE SYMBOL ONITIONS (NOTE, ) SUBGOUPS TEMPEATUE MIN MAX UNITS Propagation elay TPHL V = 5V, VIN = V or GN +5 o - 5 ns lock to Output TPLH, + o, -55 o - 75 ns Propagation elay TPHL V = 5V, VIN = V or GN +5 o - 5 ns eset to Ouput, + o, -55 o ns Transition Time TTHL V = 5V, VIN = V or GN +5 o - ns (Note ) TTLH, + o, -55 o - 7 ns Maximum lock Input FL V = 5V, VIN = V or GN +5 o.5 - MHz Frequency, + o, -55 o. - MHz NOTES:. L = 5pF, L = K, Input T, TF < ns o and + o limits guaranteed, % testing being implemented. TABLE. ELETIAL PEFOMANE HAATEISTIS LIMITS PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply urrent I V = 5V, VIN = V or GN, -55 o, +5 o - 5 µa + o - µa V = V, VIN = V or GN, -55 o, +5 o - µa + o - µa V = V, VIN = V or GN, -55 o, +5 o - µa + o - µa Output Voltage VOL V = 5V, No Load, +5 o, + o, - 5 mv -55 o Output Voltage VOL V = V, No Load, +5 o, + o, - 5 mv -55 o Output Voltage VOH V = 5V, No Load, +5 o, + o,.5 - V -55 o Output Voltage VOH V = V, No Load, +5 o, + o,.5 - V -55 o Output urrent (Sink) IOL5 V = 5V, VOUT =.V, + o. - ma -55 o. - ma Output urrent (Sink) IOL V = V, VOUT =.5V, + o. - ma -55 o. - ma Output urrent (Sink) IOL V = V, VOUT =.5V, + o. - ma -55 o. - ma Output urrent (Source) IOH5A V = 5V, VOUT =.V, + o - -. ma -55 o - -. ma Output urrent (Source) IOH5B V = 5V, VOUT =.5V, + o - -. ma -55 o - -. ma Output urrent (Source) IOH V = V, VOUT =.5V, + o - -. ma -55 o - -. ma Output urrent (Source) IOH V =V, VOUT =.5V, + o - -. ma -55 o - -. ma Input Voltage Low VIL V = V, VOH > V, VOL < V, +5 o, + o, - V -55 o Input Voltage High VIH V = V, VOH > V, VOL < V, +5 o, + o, +7 - V -55 o 7-8

4 Specifications 58BMS, 5BMS Propagation elay lock to Output Propagation elay eset to Output Transition Time Maximum lock Input Frequency Maximum lock ise and Fall Time Minimum Enable Pulse Width Minimum eset Pulse Width TABLE. ELETIAL PEFOMANE HAATEISTIS (ontinued) PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE TPHL TPLH V = V,, +5 o - ns V = V,, +5 o - ns TPHL V = V,, +5 o - 5 ns V = V,, +5 o - 7 ns TTHL V = V,, +5 o - ns TTLH V = V,, +5 o - 8 ns FL V = V,, +5 o - MHz V = V,, +5 o - MHz TL TFL V = 5V,,, +5 o - µs V = V,,, +5 o - 5 µs V = V,,, +5 o - 5 µs TW V = 5V,, +5 o - ns V = V,, +5 o - ns V = V,, +5 o - ns TW V = 5V,, +5 o - 5 ns V = V,, +5 o - ns V = V,, +5 o - 8 ns Minimum lock Pulse TW V = 5V,, +5 o - ns Width V = V,, +5 o - ns V = V,, +5 o - 7 ns Input apacitance IN Any Input, +5 o pf NOTES:. All voltages referenced to device GN.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. L = 5pF, L = K, Input T, TF < ns.. If more than one unit is cascaded, TL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. MIN LIMITS MAX UNITS TABLE. POST IAIATION ELETIAL PEFOMANE HAATEISTIS LIMITS PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply urrent I V = V, VIN = V or GN, +5 o - 5 µa N Threshold Voltage VNTH V = V, ISS = -µa, +5 o V N Threshold Voltage VTN V = V, ISS = -µa, +5 o - ± V elta P Threshold Voltage VTP VSS = V, I = µa, +5 o..8 V P Threshold Voltage VTP VSS = V, I = µa, +5 o - ± V elta Functional F V = 8V, VIN = V or GN +5 o VOH > VOL < V V = V, VIN = V or GN V/ V/ Propagation elay Time TPHL TPLH V = 5V,,, +5 o -.5 x +5 o Limit ns NOTES:. All voltages referenced to device GN.. L = 5pF, L = K, Input T, TF < ns.. See Table for +5 o limit.. ead and ecord 7-

5 Specifications 58BMS, 5BMS TABLE 5. BUN-IN AN LIFE TEST ELTA PAAMETES +5 o PAAMETE SYMBOL ELTA LIMIT Supply urrent - MSI- I ±.µa Output urrent (Sink) IOL5 ± % x Pre-Test eading Output urrent (Source) IOH5A ± % x Pre-Test eading TABLE. APPLIABLE SUBGOUPS ONFOMANE GOUP MIL-ST-88 METHO GOUP A SUBGOUPS EA AN EO Initial Test (Pre Burn-In) % 5, 7, I, IOL5, IOH5A Interim Test (Post Burn-In) % 5, 7, I, IOL5, IOH5A Interim Test (Post Burn-In) % 5, 7, I, IOL5, IOH5A PA (Note ) % 5, 7,, eltas Interim Test (Post Burn-In) % 5, 7, I, IOL5, IOH5A PA (Note ) % 5, 7,, eltas Final Test % 5,, 8A, 8B,, Group A Sample 55,,, 7, 8A, 8B,,, Group B Subgroup B-5 Sample 55,,, 7, 8A, 8B,,,, eltas Subgroups,,,,, Subgroup B- Sample 55, 7, Group Sample 55,,, 8A, 8B, Subgroups, NOTE:. 5% Parameteric, % Functional; umulative for Static and. TABLE 7. TOTAL OSE IAIATION ONFOMANE GOUPS MIL-ST-88 METHO TEST EA AN EO PE-IA POST-IA PE-IA POST-IA Group E Subgroup 55, 7, Table, Table TABLE 8. BUN-IN AN IAIATION TEST ONNETIONS OSILLATO FUNTION OPEN GOUN V V ± -.5V 5kHz 5kHz Static Burn-In Note Static Burn-In Note ynamic Burn- In Note Irradiation Note -, -,, 7-, -, - 8,, 7,,,, - 7, 8,,, -, -, -, - 8,, 7,,,, NOTES:. Each pin except V and GN will have a series resistor of K ± 5%, V = 8V ±.5V. Each pin except V and GN will have a series resistor of 7K ± 5%; Group E, Subgroup, sample size is dice/wafer, failures, V = V ±.5V 7-

6 58BMS, 5BMS Logic iagrams V / / 5/ / ALL INPUTS AE POTETE BY MOS POTETION NETWOK ESET 7/ VSS ENABLE / LOK / FIGUE. EAE OUNTE (58BMS) LOGI IAGAM FO ONE OF TWO IENTIAL OUNTES V / / 5/ / ALL INPUTS AE POTETE BY MOS POTETION NETWOK ESET 7/ VSS ENABLE / LOK / FIGUE. BINAY OUNTE (5BMS) LOGI IAGAM FO ONE OF TWO IENTIAL OUNTES TUTH TABLE LOK ENABLE ESET ATION Increment ounter Increment ounter X No hange X No hange No hange No hange X X thru = X = on t are High State Low State 7-

7 58BMS, 5BMS Typical Performance urves OUTPUT LOW (SINK) UENT (IOL) (ma) 5 5 AMBIENT TEMPEATUE (T A ) = +5 o GATE-TO-SOUE VOLTAGE (VGS) = V V 5V OUTPUT LOW (SINK) UENT (IOL) (ma) AMBIENT TEMPEATUE (T A ) = +5 o GATE-TO-SOUE VOLTAGE (VGS) = V V 5V 5 AIN-TO-SOUE VOLTAGE (VS) (V) FIGUE. TYPIAL OUTPUT LOW (SINK) UENT HAATEISTIS 5 AIN-TO-SOUE VOLTAGE (VS) (V) FIGUE. MINIMUM OUTPUT LOW (SINK) UENT HAATEISTIS AIN-TO-SOUE VOLTAGE (VS) (V) AMBIENT TEMPEATUE (T A ) = +5 o GATE-TO-SOUE VOLTAGE (VGS) = -5V -V -V OUTPUT HIGH (SOUE) UENT (IOH) (ma) AIN-TO-SOUE VOLTAGE (VS) (V) AMBIENT TEMPEATUE (T A ) = +5 o GATE-TO-SOUE VOLTAGE (VGS) = -5V -V -V OUTPUT HIGH (SOUE) UENT (IOH) (ma) FIGUE 5. TYPIAL OUTPUT HIGH (SOUE) UENT HAATEISTIS FIGUE. MINIMUM OUTPUT HIGH (SOUE) UENT HAATEISTIS POPAGATION ELAY TIME (tplh, tphl) (ns) 5 AMBIENT TEMPEATUE (T A ) = +5 o SUPPLY VOLTAGE (V) = 5V 5 V V LOA APAITANE (L) (pf) POPAGATION ELAY TIME (tphl, tplh) (ns) 5 AMBIENT TEMPEATUE (T A ) = +5 o SUPPLY VOLTAGE (V) = 5V 5 V V LOA APAITANE (L) (pf) FIGUE 7. TYPIAL POPAGATION ELAY vs LOA APA- ITANE, LOK O ENABLE TO OUTPUT FIGUE 8. TYPIAL POPAGATION ELAY TIME vs LOA APAITANE, ESET TO OUTPUT 7-

8 58BMS, 5BMS Typical Performance urves TANSITION TIME (tthl, ttlh) (ns) AMBIENT TEMPEATUE (T A ) = +5 o SUPPLY VOLTAGE (V) = 5V V V 5 8 LOA APAITANE (L) (pf) FIGUE. TYPIAL TANSITION TIME vs LOA APAITANE MAXIMUM LOK FEUENY (fl MAX) (MHz) 5 AMBIENT TEMPEATUE (T A ) = +5 o LOA APAITANE (L) = 5PF 5 SUPPLY VOLTAGE (V) (V) FIGUE. TYPIAL MAXIMUM LOK FEUENY vs SUPPLY VOLTAGE POWE ISSIPATION /ONVETE (P) (µw) SUPPLY VOLTAGE (V) = V 8. L = 5pF L = pf 5V V V AMBIENT TEMPEATUE (T A ) = +5 o FEUENY (f) (khz) FIGUE. TYPIAL POWE ISSIPATION HAATEISTIS Timing iagrams 58BMS 5BMS LOK ENABLE ESET FIGUE. TIMING IAGAMS FO 58BMS AN 5BMS 7-

9 58BMS, 5BMS LOK INPUT V 7 7 LOK ENABLE ESET A A A LOK ENABLE ESET B B B LOK ENABLE ESET A A A LOK ENABLE ESET B B B A A A A B B B B A A A A B B B B BMS/BMS 58BMS/BMS FIGUE. IPPLE ASAING OF FOU OUNTES WITH POSITIVE EGE TIGGEING LOK INPUT 7 7 LOK ENABLE ESET A A A LOK ENABLE ESET B B B LOK ENABLE ESET A A A LOK ENABLE ESET B B B A A A A B B B B A A A A B B B B 5 5 5BMS 5BMS A A A 5BMS For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at pf and the transition time of the output driver stage for the estimated capacitive load. FIGUE. SYNHONOUS ASAING OF FOU BINAY OUNTES WITH NEGATIVE EGE TIGGEING 7-

10 hip imensions and Pad Layouts 58BMS, 5BMS 58BMS 5BMS imensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (- inch). METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BON PAS:. inches X. inches MIN IE THIKNESS:.8 inches -.8 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO quality systems certification. Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see web site Sales Office Headquarters NOTH AMEIA Intersil orporation P. O. Box 88, Mail Stop 5- Melbourne, FL TEL: () 7-7 FAX: () 7-7 EUOPE Intersil SA Mercure enter, ue de la Fusee Brussels, Belgium TEL: ().7. FAX: ().7..5 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-, No. Fu Hsing North oad Taipei, Taiwan epublic of hina TEL: (88) 7 FAX: (88) 7