A Continuous-Time Incremental Analog to Digital Converter

Transcription

1 A Continuous-Time Incremental Analog to Digital Converter Ricardo Doldán, Alberto Yúfera and Adoración Rueda Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla, Edificio CICA, c/ Tarfia s/n, SEVILLA, SPAIN. s: {rdoldan, yufera, Abstract In this paper, an incremental Analog-to-Digital Converter (ADC) designed as part of the signalconditioning circuitry for tissue impedance measurement system is pented. Continuous-time design techniques has been used for that which a modified implementation of the conversion algorithm, with pect to its discrete-time counterpart, has been developed. In order to reduce the influence of the noidealities, analog and digital corrections has been also implemented. A first prototype in 0.8µm CMOS technology has been fabricated and tested. Simulation and experimental ults are reported. 1. Introduction Now days, most of Low-Voltage and Low Power (LV/LP) analog signal processing circuits are implemented using Continuous Time (CT) circuits techniques instead of the traditional Switchedcapacitor (SC) approach. The main reason for that derives from the limited performance of switches under low voltage operation. Additional reasons can exist from noise and specific application considerations. In this paper, we pent the design and implementation of a first order Incremental Analogto-Digital Converter (ADC) using the continuous-time approach. In particular, the OTA-C technique is applied to design the main analog signal processing functions, such as integrator and adders. This work is part of a project aimed at establishing a design procedure for tissue impedance measurement with application in measure of biological parameter [1]. The proposed measurement system is shown in Fig. 1. It is based on a four-electrodes configuration (Z E1 to Z E4 ), in which two of them (Z E1, Z E4 ) are employed to stimulate the tissue sample (SUT) of unknown impedance Z x, and the other two (Z E2, Z E3 ) take the SUT ponse. The excitation part consists of a Voltage Controlled Oscillator (VCO) giving a sinusoidal current, while a signal acquisition circuitry processes the SUT ponse. This signal acquisition and processing circuitry consists of an Instrumentation Amplifier (IA), two demodulators and two Analog-to-Digital converters (A/D). The final outputs of the circuit are two digital signals corponding to the real and imaginary parts of the tissue complex impedance, Z x. clock-quad Demodulator A/D I+ tissue model b(i) Z x Imaginary VCO S Z x Z E1 Z E4 I- SUT Z E2 Z E3 V x electrode model clock-phase - IA + Demodulator Z x Real b(r) A/D Fig.1. Blocks involved on the real and imaginary impedance measurement system Accurate methods for impedance measurements have been already developed [2]. We use the twophase reference coherent demodulation method, which gives simultaneously the real (Re(Z x )) and

2 imaginary (Im(Z x )) component of a complex impedance, Z x, as DC signals. They are digitally codified for parallel transmission. Incremental converters based on sigma-delta modulation, double-ramp principle, or multivibrator are normally used in these applications [3-6], providing high accuracy, good linearity, and reduced offset levels. In our case, a first order incremental converter with a bit parallel digital output has been considered. The paper is organized as follows. The conversion algorithm is described in Section 2. The design of the basic building blocks are pented in Section 3. Basic digital control circuits are explained in Section 4. Section 5 shows simulation and experimental ults. Finally, some conclusions are given in Section The Analog to Digital Converter Algorithm The operation principle of an incremental ADC relies on changing voltage-olution for timeolution, performing the integration of the analog input to obtain a bit-stream output [3]. This output is easily transformed into a digital word by basic digital circuits. The block diagram of the ADC is illustrated in Fig. 2. This incremental converter works as a sigma-delta modulator with a et signal at the beginning of each conversion. Its main blocks are the integrator and the comparator. Other blocks are the input signal multiplexer, the control block to et and to invert integrator output, and the digital output signal processing, basically a counter. V p V n Signal Input Clock p + - n Reset and Inversion Digital Control Fig.2. Conceptual schematic of an incremental ADC. V comp DSP COUNTER N con The input multiplexer determines the inverting and non-inverting integrator inputs (p, n, pectively) as function of the converter inputs V p and V n, and it is directly controlled by the digital hardware and the comparator output. The sign of the differential integrator output,, is obtained by the comparator, giving as output the digital signal V comp. When > 0, V comp is 1, and for < 0 it is 0. The role of the et and inversion blocks is to initialize the converter to zero when a conversion starts, and to invert the integrator output signal at a defined instant of the conversion time. To avoid errors due to mismatching between the ADC reference voltage and its inverted version - [3], a differential output OTA is used, whose function will be explained later on. The conversion process of an analog differential input, *= V p - V n, is based on the addition/ subtraction of a reference signal,. This reference repents the half of converter Full Scale, so that the LSB is given by / 2 n-1 for a converter of n bits. The decision to add/subtract depends on the comparator output. The conversion time is fixed by the number of bits. A discrete-time realization of the converter requi five operation modes: et, sample, positive conversion, inversion, and negative conversion. A description of these follows. In the first clock period, Reset Mode, the integrator is autozeroed. Next, in Sample Mode, the analog input signal is connected to the integrator positive input, giving = *. The Positive Conversion Mode (PCM) interval is 2 n T (where T is the clock period), during which the comparator performs 2 n discrimination. Initially, depending on the positive or negative sign of *, is subtracted from or added to *, pectively. Adding or subtracting means to put the signal into the integrator positive or negative input terminal pectively, thus avoiding the need of two voltage reference and -. Adding and subtracting moves the counter state up and down. With N u1 and N d1 repenting the number of up and down counts, pectively, the integrator output after 2 n clock periods will be:

3 and, (1) (2) The analog-to-digital conversion is thus realized, and N repents the state of the output counter obtained as the difference between the up and down counts. The accuracy of the digital repentation of * is n bits. One extra bit can be obtained by detecting the sign of (2 n ). Due to the high number of integration steps, this type of conversion can be critical to the integrator input equivalent offset. A digital correction technique, as proposed in [3], can be used. In this case, two additional operation modes are necessary: inversion and negative conversion modes. After the first 2 n-1 positive conversion cycles, the signal at the integrator output is inverted. The integrator output in the next clock period will be - 1, where 1 = (2 n-1 ) is given by (1) using n-1 instead of n. This is the Inversion Mode. During the following 2 n-1 clock cycles the Negative Conversion Mode (NCM) operates similarly to PCM, but now the - * input signal is sampled and compared to zero. Up and down counts are decided inversely as in PCM. At the end, the signal accumulated at the integrator output is, and, ( 2 n ) = ( N d1 N u1 ) + ( N u1 + N d1 ) N N u1 N d1 2 n ( 2 n ) = = ( 2 n ) = V 2 n 1 op1 V + ( N N ) u2 d2 Ref ( 2 n ) = 2 n + 2N (3) (4) where 2N=(N u2 -N d1 +N n1 -N d2 ) is an n-bit digital word. In this case, the extra sign bit (d) will be 1 if (2 n+1 ) < 0 and 0 otherwise. The final digital word, N con, will be obtained as 2N+d. The described ADC has the advantage that its olution does not depend on the integrator gain errors, and furthermore, the integrator non-signal dependent offset is cancelled. An important property that must be perved is the use of an unique. The reason for this is that mismatching between and - generates output errors which increase with the number of bits. The same considerations apply to the input signals. We propose a modification for the algorithm explained before. The basic idea is to divide each integration period, T, into two intervals, in such a form that the input signal, *, and the reference signal,, will be integrated in different times: the input in (0,T/2), and the reference in (T/2,T), pectively. This is illustrated in Fig. 3, where a conceptual interpretation of the two algorithms is shown. In this algorithm, a comparison by cycle is carried out at T/2. Analysing the final ult the output digital code is obtained as, (5) being the integer part operator. Using this modified algorithm is of great importance for a CT implementation of the integrator since in other case, linear integration will be degraded by the influence of the finite transconductor output istance. This effect is more evident when inputs are near the FS. Vop N = con 0 T/2 T V LSB Vop~Vin Vop~Vref Fig.3. Integrator output evolution in the proposed algorithm. 3. Continuous-Time Implementation: Analog Basic Blocks The specifications for the targeted ADC are: 12bits, a 50kHz clock, a voltage supply below 3V, and an input range of 0.5 bipolar conditions. The block diagram of the analog part is shown in Fig. 4. It includes a controlled two-input integrator and a comparator. The functionality of each block is briefly explained in the following. The input mux block is controlled by the S vin digital signal, which selects when the ADC input is going to be processed by the t

4 S vin S inv S inv S inv V dd = 3V + V 1 V 2 + V + in- MUX INV OTA V INV INV V ut ground V 1 V o- 2 C - b M3 M2 M33 M6 M10 OTA I ref RES V ground + - M1 M4 M22 M11 M M7 V ground Ibias = 500 na S vref Q I ref Fig.4. ADC analog blocks. integrator or it processes a zero input. The INV block applies for signal inversions. Both blocks are implemented with CMOS analog switches, whose onistance must be optimized when they are in the signal path. The RES block discharges the capacitor when the conversion ends. For the reference signal integration the same OTA than for the input is used, whose operation is now controlled by the S vref digital signal, sourcing/sinking current at the integrating capacitor C. The more challenging analog block is the OTA. Its input voltage range must be 0.5V bipolar, so a linearized architecture has to be chosen. We have employed the circuit reported in [7] which allows to increase the input linear range by properly designing M2 and M22 transistors. Its schematic including the common-mode feedback circuit is shown in Fig. 5. In order to guaranty the linearity of the OTA-C integrator, the selection of the transconductance value is realized taken into account the integrator capacitor value, the OTA output istance, and the integration time. In the proposed algorithm, the input voltage at the integrator will be a step signal from zero to the pent input sample value. So, considering an ideal integrator as illustrated in Fig. 6, transient time evolution of the capacitor voltage can be described as, M5 M55 Fig.5. Schematic of the OTA. R out C must be dimensioned to perve the output linearity range. Since we have a T/2 = 10µs, and a 7.5ms time constant value has been considered enough to work always in the linear region. This leads to a R out = 500MΩ for a C=15pF. Table 1: Transistor sizes for the OTA Transistor (µm/µm) Transistor (µm/µm) M1, M11 4/20 M5,M55,M9 6/2 M2, M22 2/64 M6, M10 20/5 M3, M33 20/5 M7 4/20 M8 M4, M44 1.5/13.8 M8 1.5/ V g in m i C - 0 i t Fig.6. Ideal step ponse of the linearized OTA. M9 = g m V in t C (6) i The maximum value for should be, that integrated in a T/2 period of time will give us the maximum output range. For a C=15pF, we have chose g m =0.338µS. The corponding transistor sizes are in Table 1. The linearized OTA ponse is illustrated in Fig. 7, where an 1V pp input range can be appreciated for a g m linearity error below 0.9%. For a real integrator, the situation is the shown in Fig. 8 where the OTA output istance influencing the transient ponse is considered. The time constant given by I o [na] [V] Fig.7. I o / linearized OTA characteristic

5 + _ g m 0 t r 4. Digital Circuits g m R out R out Fig.8. Exponential integrator output ponse to input step due to R out. C + _ t are very time expensive due to the high conversion time when the number of bit increases. A suitable agreement with the expected codes was obtained in most of the cases. Figure 10 plots the simulation performed for (5+1)-bit conversion of =135mV (V ref =500mV). In Fig. 10(a) it can be seen the digital control signal and the counter output delivering the digital conversion output. A waveform of the integrator output corponding to the before simulation conditions is shown in Fig. 10(b). The same waveform is shown in Fig. 11 for (11+1)-bits. The 0.8µm CMOS prototype has been integrated and is being actually tested. Its layout is shown in Fig. 12. It spends a silicom area of 2265µm x 2012µm. A firts set of data obtained is shown in Fig. 13, where the transfer function for n=(8+1)bits illustrates the good functionality of the prototype. The input signal has been taken in the range [-500mV, 500mV], with = 500mV. Complete ults will be ready at the conference. The general block descriptions for the digital control and processing parts are described in Fig. 9. It comprises two 14bits counters, and a more specific control block that will be described now. The input for these blocks are: the clock (clk), an external et (_ext), the number of bits for the ADC (n) that has been parametrized in the range (2,13), and finally, the bit-stream (b) from the comparator output. The generated outputs must drive the conversion algorithm. These are: S vin, S inv, S vref, Q and for control analog blocks, also feed the counters, and finally ud y ce to feed counter2. The circuits has been implemented using standard cell from a VHDL whole function description. N con cont (V) _ext (V) S vin (V) S vref (V) S inv (V) Transient Response time (s) (a) S vin S inv S vref Q (V) Transient Response clk cont1 ce Counter1 b n Control ud Counter2 N con inversion of end of conversion clk _ext clk (b) Fig.9. Digital blocks involved in the ADC. 5. Experimental Results Exhaustive simulations have been performed for a number of bits below 12. Time domain simulations time (s) Fig.10. Simulation for =135 mv and n=6b. Digital control signals: (a) integrator output and (b) waveforms.

6 N con cont1 Transient Response Conclusions In this paper, the design of a first order Continuous Time Analog to Digital Converter has been pented. A modification of the classical conversion algorithm has been proposed in order to facilitate its continuoustime implementation. A silicon prototype has been integrated for a 12-bit olution. Preliminary test ults allows us to expect a good agreement with the specified performance. 7. References time(s) Fig.11. Simulation for =135mV and n=12b. Integrator output waveforms. Fig.12. Photograph of the ADC. [1] A. Yúfera, G. Leger, E. O. Rodriguez-Villegas, J. M. Muñoz, A. Rueda, A. Ivorra, R. Gomez, N. Noguera and J. Aguiló: An Integrated Circuit for Tissue Impedance Measured. Proceeding of IEEE EMBS Specific Topic Conference on Microtechnologies in Medicine & Biology, Wisconsin. USA, May [2] R. Pallás-Areny and J. G. Webster: Analog Signal Processing. John Wiley and Sons, Inc [3] J. Robert, G. C. Temes, V. Valencic, R. Dessoulavy and P. Deval: A 16-bit Low-Voltage CMOS A/D Converter. IEEE Journal of Solid-State Circuits, Vol SC-22, N 2, Apr., pp [4] A. Yúfera and A. Rueda: A S2I First Order Incremental A/D Converter. Proceeding of IEE Part- G: Circuits, devices and system, Vol. 145, Nº2, pp [5] A. Haberli, P. Malcovati, H. Baltes, and F. Maloberti: An Incremental A/D Converter for Accurate Vector Probe Measurements. Proceeding of IEEE International Symposium on Circuits and Systems. pp [6] F. R. Riedjij and J. H. Huising: An integrated absolute temperature sensor with sigma-delta A-D conversion. Sensors and Actuators. A34. pp [7] F. Krummenacher and N. Joehl, A 4-Mhz CMOS continuous-time filter with on-chip automatic tuning, IEEE Journal of Solid-State Circuits, Vol. SC-20, pp , Dec Code [N] [V] Fig.13. Experimental transfer function for n=9bits, and V ref =500mV.