A SI Incremental A/D Converter for IC Sensor Interfaces

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1 EEE nstrumentation and Measurement Technology Conference Brussels, Belgium, June 4-6, 1996 A S ncremental A/D Converter for C Sensor nterfaces Albedo Yilfera r2 and Adoracion Rueda Dpto. de Diseiio de Circuitos Analogicos, Centro Nacional de Microelectronica, Edificio CCA, Avda. Reina Nlercedes s/n, Sevilla, SPAllN Dpto. de Tecnologia Electronica, Universidad de Sevilla Campus de Reina Mercedes, Sevilla, SPAN. Tf: , E-nnail: yufera@cnm.us.es Abstract - n this paper an lncrementad Analog-to- Digital Converter (ADC) designed as part of the signalconditioning circuitry of a pressure sensor interface is presented. For technological compatibility the Switched-Current (S) technique has been used, which does not need double polysilicon CMOS process. To overcome the lack of precision of this iechnique a conversion algorithm with digital correction has been chosen and circuit enhancements has been sought. Electrical simulations show the correct error cancellation performed by the proposed converter. Resolution of 10 bits is achieved for a 4MHz master clock. A lpm CMOS prototype is being tested and some experimental results are given.. NTRODUCTON The Switched-Current (S) technique becomes a design option to include analog functions into standard CMOS technology process [l]. Potentially, S technique increases both the dynamic range ancl maximum operation frequency, and decreases the design cost. n this paper we present the implementation of an ncremental Analog-to-Digital Converter wilh S circuits. This work is supported in part by the DEMAC ESPRT project funded by the CEC. The project intends to establish a procedure design for sensor cells based on standard foundry technology and to use standard postprocessing technology in order to fabricate them. n this context, specific integrated circuits cells must be developed for sensor signal processing, and make them compatible with the sensor post-processing steps. The ADC we designed is part of a pressure semor interface system shown in Fig. 1. The system has a piezoresistive pressure sensor, providing a differential input to the post-processing part, a signal level shifter, which generates the ADC Full Scale current, and the A/D Converter. Biasing signals are generated by the same circuit, which incorporates a temperature compensation technique. ncremental converters based on sigma-delta modulation, double-ramp principle, or multivibrator are normally used in this applications [3-41, giving high accuracy, good linearity ancl reduced offset levels. We chose an incremental converter with a bit stream output because of the simplicity of the required post processing digital circuit, that makes easy the communication with on-chip digital signal processing [2]. The paper is organized as follows. The conversion algorithm used is described in section. The design of the basic S building blocks are presented in section ll. Section V shows simulation and experimental results. Finally, some conclusions are given in section V. BAS CRCUT, 1 Fig. 1: Block diagram of the pressure sensor interface system.. ANALOG-TO-DGTAL CONVERTER OPERATON The operation principle of a current-mode incremental ADC is based on changing current-resolution for timeresolution, performing the integration of the analog input to obtain a bit-stream output, easily transformed into a digital word by a counter. The block diagram of the A/D converter is illustrated in Fig. 2. This incremental converter works as a sigma-delta modulator with a reset signal at the beginning of each conversion [3-41. ts main blocks are the integrator and the comparator. The auxiliary blocks are the input signal O /96/$ EEE

2 multiplexer, the block to reset and to invert integrator output, and the counter. To avoid current mismatching effects, we propose an integrator with two input terminals whose function will be explained later. The single integrator output, lop, is compared with zero by the comparator, which giving as output the digital signal Vcomp. When qp z 0, Vcomp is " ", and for, < 0 it is "U. The input multiplexer determines the integrator inputs, and is directly controlled by the digital hardware and the comparator output. The role of the reset and inversion block is to initialize the converter to zero when a conversion starts, and to invert the integrator output signal at a defined instant of the conversion time. The conversion process of an analog input, i,,*, is based on the addition /subtraction of a reference signal, Ref (for simplicity, we use only one converter input, but the analysis can be applied to differential inputs) This reference represents the full scale of the converter, so the LSB is given by ReP/r, being n the number of bits of the converter. The decision to add or to subtract is depending on the comparator output. The conversion time is fixed by the number of bits. A discrete-time realization of the converter requires five operation modes: reset, sample, positive conversion, inversion, and negative conversion. A description of these follows. n the first clock period, Reset Mode, the integrator is autozeroed. Next, in Sample Mode, or second clock period, the analog input signal is connected to the integrator positive input, giving op=/in*. The Positive Conversion Mode (PCM) interval is 2"T (where T is the clock period), during which the comparator performs F discriminations. nitially, depending on the positive or negative sign of lin*, lref is subtracted or added to,,,*, respectively. Adding or subtracting means to put the Ref signal into the integrator positive or negative input terminal, respectively. Thus avoiding the need of two reference currents lref and -Ref. Adding and subtracting Refmoves the counter state up and down. With Nul and Nd7 representing the number of up and down counts, respectively, the integrator output after 2" clock periods will be: already realized. However, due to the high number of integration steps, this type of conversion can be critical to the equivalent offset at the integrator input. A digital correction technique, as proposed in [3], can be used, needing two more operation modes: inversion and negative conversion. After 2? positive conversion cycles, the signal at the integrator output must be inverted. Thus, the integrator output in the next clock period is -Op(2"), where Op(2") is given by (1). This is the nversion Mode. During the following 2" clock cycles the Negative Conversion Mode (NCM) operates similarly to PCM, but now the -in*input signal is sampled and compared to zero. Up and down counts are decided as in PCM. At the end, the signal accumulated at the integrator output is, and. where 2N=(Nu2-Nuf+Ndl-Nd2) is an n-bit digital word. n this case, the extra sign bit will be "7" if 10p(Zn+7) < 0 and "0' elsewhere. The described ND Converter has the advantage that its resolution is independent of errors in the realization of the integrator gain (this value has been taken as one) and also, the integrator non-signal dependent offset is cancelled. An important property that must be preserved is the use of a unique ReF This is because mismatching between /Ref and -Ref generates output errors that increase with the number of bits. The same considerations apply to the input signals. CLOCK and, jcounter n this way, M represents the output counter state obtained as the difference between the up and down counts. Since the most RHS term in (2) is limited by ZLSB, the accuracy of the digital representation of lin* is n-7 bits. One extra bit can be obtained by detecting the sign of lop(2"). Analog-to-Digital conversion has been Fig. 2: Block diagram of the incremental A/D Converter. 1030

3 ll. S CRCUT REALZATON The accuracy of the converter is strongly dependent on the accuracy of the integrator. t is known that the main drawbacks of the S technique are matching errors between MOS transistors and charge injection errors induced by analog switches, both generating dc offset, gain errors, and non-linear error terms [5]. Matching errors have a minor influence since the converter resolution relies more on the ratio /in*//ref than on the integrator gain. The effects of charge injection errors are stronger. These can be high, and what is worse, they are signal dependent. The following describes the S circuits used for the integrator and comparator. The S integrator design is based on a dynamic current memory cell as shown Fig. 3. This cell is free of matching errors, but not of charge injection ones. The later errors can be modeled as a gate-to-source voltage increment, AV, due to channel charge injection and overlap capacitance [4]. The influence of A y can be reduced using the Sk/ technique [6]. For k=2 reductions in Avf of up to 95% have been obtained for inputs in the range of 70@A. This is shown in Fig. 4, where the gateto-source voltage errors is plotted as a function of the input current for k values of 1, 2 and 3. Thus, output errors in this current memory cell will be less dependent on the input signal than in S, and consequently they can be corrected by the conversion algorithm. The input signal multiplexer decides the integrator positive a negative inputs, depending on the Converter Operation Mode and comparator output (V1,V2). The circuit and digital control signal are shown in Fig. 5. n the circuit, a current sink node (vi-dummy) has been included to lead those currents, whem they are not being used. This is necessary to reduce gliches and transient times when switching current:;. Circuit for reset and inversion are directly implemented by means of two unity gain current mirrors. vi-dummy Fig. 3: Current T/H Cell and clock signals. : Periods END OF CONVERSON Fig. 5: nput Signal Multiplexer Block. (a) Circuit. (b) Digital Control Signals Fig. 4: Gate-to-Source voltage error in (a) S, (b) S21 and (c) s3t memory cells. Fig. 6 shows the simplified schematic for a S2/ integrator. We have provided duplicated outputs (, and on) to establish the same capacitive conditions at sampling nodes (Via and Vib, with i=7,2). This means that charge injected by analog switches will be redistributed between the same parasitic capacitance, generating the same gate-to-source error voltage. The, output current will be not used. To reduce errors due to finite resistance at the integrator output, a low-impedance input comparator was chosen [7]. 1031

4 10 4 B OJ 1 vssl positive and negative conversion modes (PCM and NCM, respectively). As can be seen from the table, the accumulated error has different sign for positive and negative conversion modes. This means that errors generated in the PCM will add to those in the NCM's. However, in our case this means that total error is small enough (less than ZnA, which is much smaller than LSB) to do not be derived in error code. n both cases, 10b resolution is achieved and, even higher resolution are possible if the results in tables are extrapolated. A/D Conversion waveforms E O -O ' g lo 0.0 Fig. 6: Simplified schematic for: (a) the S2Z integrator -1.o used in the A/D Converter, and (b) the S' memory cell (c) Clock waveforms. '1-3.0; V. EXPERMENTAL RESULTS The converter designed in a 5V 7pm standard CMOS process has been simulated with HSPCE for a lmhz clock frequency. Regulated cascode current mirrors have been used to increase the outpub'input ratio impedance. Fig. 7 illustrates the simulated results for a conversion process of 5 bit, R,,=4qLA, and lin *= 1 +A. The integrator and comparator output waveforms (, and Vcomp) are plotted for the whole conversion period. The digital word resulting at the counter is: 2N= =- 76, which corresponds to U7000 digital code, and the extra sign bit is "1". Hence, the converter accuracy is 6 bit. Simulations performed for n=8 and 10 agreed with the expected operation. Q ; ' 3.0 ' '. 20 ' t [P Fig. 7: Waveforms obtained with HSPCE for lo,, and Vcomp corresponding to. n=5 bits, ir,+=40pa and,, *=O@. Table Mean Error Accumulated at, [nallntegration period. bits ntgstep LSB Mean Error [na] n P PCM NCM PCM NCM The main source of inaccuracy of the converter 8 5pA derives from the not exact cancellation of clock feedthrough errors with the S*/ technique. Table shows pA the limits imposed by these errors for two different values of the converter input current. The converter nA performance was measured as the mean error nA o,70 -o,69 -o,88 accumulated at the integrator current output during the n ~7

5 The layout of the prototype $1 A/D Converter is shown in Fig. 8. Testing of the chip is not yet complete. To illustrated the first experimental results Fig. 9 show!; the comparator output waveforms obtained for n=5, Ref =40.@A and in*=+2@a, for a 200KHz clock frequency. n the measurement setup, the input currents art? obtained from a voltage source with 700m series resistor. t can be appreciate in Fig. 9a that for in*=+2qla, the signal measured by the counter is 2N=& =-32, corresponding to digital code, and the extra bit "1', because of Vcomp ="1" at the end of the conversion. n Fig. 9b is shown the corresponding output waveforms for lin*=-2@a. The expected digital code output is obtained: 2N=32, with the same absolute value and different sign than for +2@A input current. 1 mm 4 B- To perform a first rapid test, the converter was reconfigured as a ZA modulator by activating only the PCM operation. The spectrum of the output pulse obtained for a 7KHz sinusoidal input and lmhz clock frequency is shown in Fig. 10. Fig. 10: Output Spectrum. V. CONCLUSONS Fig. 8: Layout of the S2/ A/D Converter prototype. A Switched-Current lncreimental A/D Converter with integrator offset correction has been presented. Source of errors have been strongly reduced by an adequate choice of S building blocks. The use of only one reference signal avoids matching errors and allows both unipolar and bipolar operation. Results obtained up to 70b resolutions agreed with 'the expected performance. Further improvements are forecast when S3/ integrators are used. REF ER Ei N C ES 5C@s/div 4 b 4 PCM NCM -- /jn=-2&a N,1=8, Ndl=24 N,2=24, Nd2=8 1 Fig. 9: Output waveforms of the converter Tor n=5b. /Ref4@4 and: (a) lin*=20pa, (b) /in*=-24la. [l] J. B. Hughes and W. Redman-White: "Switched-Current Limitations and Non-deal Behaviour". Chapter 4 in SWTCHED- CURRENTS: an analogue technique for digital technology, Peter Peregrinus Ltd., Eds. C. Toumazou, J. B. Hughes and N. Battersby, [2] F. R. Riedjij and J. H. Huising: "An integrated absolute temperature sensor with sigmadelta A-D conversion". Sensors and Actuators. A34 (1992) pp [3] J. Robert, G. C. Temes, V. Valencic, R. Dessoulavy and P. Deval: "A16-bit Low-Voltage CMOS AD Converter". /E JSSC, VOL SC-22, N"2, pp , Apr [4] A. Haberli, P. Malcovati, H. Bakes and F. Maloberti: "An ncremental AD Converter for Accurate Vector Probe Measurements". SCAS'95. pp [5] M. J. M. Pelgrom, A.J. Duinrnaijer, A. P. G. Welbers, "Matching Properties of MOS Transistors". / E JSSC, VOL. SC- 24, N.5, PP , Oct [6] C. Toumazou and S Xiao. "n-step charge injection cancellation scheme for very accurate switched current circuits". Electronics letters, Vol. 30, No. 6 pp Apr [7] R. Dominguez-Castro, A. Rodriguez-Vazquez, F. Medeiro and J. L. Huertas: "High Resolution CMOS Current Comparators '. ESSCRC'92, pp