ASWITCHED CAPACITOR BASED SINGLETON FUZZY CONTROLLER

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1 ASWITHED APAITOR BASED SINGLETON FUZZY ONTROLLER I. Baturone, S. Sánchez Solano, A. Barriga, J.L.Huertas. Instituto de Microelectrónica de Sevilla - entro Nacional de Microelectrónica Avda. Reina Mercedes s/n, (Edif. IA) E-40, Sevilla, Spain Third IEEE International onference on Fuzzy Systems (FUZZ-IEEE 94) Vol., pp , Orlando - Florida, June 6-9, IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. opyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author s copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

2 A Switched apacitor Based Singleton Fuzzy ontroller I. Baturone, S. Sánchez Solano, A. Barriga, J.L.Huertas. Dept. of Design of Analog ircuits. entro Nacional de Microelectrónica, Edificio IA, Avda. Reina Mercedes s/n, 40-Sevilla (Spain) Abstract This paper explores the solutions offered by Switched apacitor (S) techniques for the implementation of fuzzy circuits. The architecture of a microcontroller is presented to perform the simplified inference method and the circuit realizations of the different blocks are described. The design technique achieves high operation speed, typical in analog operation, and at the same time allows the programming ease which is characteristic of digital implementations. Finally, due to the defuzzifier used, the proposed microcontroller may interact with either an analog or digital system at the output. I. INTRODUTION The information used by a fuzzy system is basically continuous or multivalued, thus the use of analog techniques is especially appropriate to realize microelectronic circuits which implement fuzzy inference mechanisms. In addition, these techniques offer many advantages regarding area reduction and operation speed of the resulting circuits. In this sense, recent literature presents different architecture for fuzzy controllers [-4]. However, the particular characteristics of analog design (the need for finely adjusted parameters, specific layout strategies, etc.) together with its limited compatibility with existing control systems (mainly digital), may form a serious obstacle for the mass practical use of this type of approximations. Different engineering fields have successfully applied analog techniques based on the use of Switched apacitors. This type of techniques are very wellestablished. They are used to realize practical analog circuits in MOS technologies totally compatible with digital circuits. They also present other interesting advantages, such as the ability to work at high frequencies, and adding programmability in a very simple way. This paper describes the implementation of a singleton fuzzy controller via S techniques. The use of discrete time techniques enables the efficient realization of the division required in the final stage of the controller (a typical bottleneck in many realizations). The adopted solution eases the interface capability of the device, by giving the output in both analog and digital form. In addition, it allows to choose the required precision. The architecture of a general singleton fuzzy controller and circuits structures of its different stages are described in the following. All these ideas have been applied to the realization of a prototype implementing 4 rules. It has been designed in a.4µm MOS technology and its samples are in process. II. ONTROLLER ARHITETURE The previous considerations moved us to propose the use of S techniques in the design of a fuzzy controller [5]. The architecture reported in this reference is a sequential implementation of the conventional inference mechanism (based on the operations of Min and Max with consequents represented as fuzzy sets). The sequential approximation and the type of consequents used impose the limitations to the inference speed in this architecture. This inconvenience is now eliminated completely resorting to the use of the simplified inference method where the consequents of the rules correspond to singleton, rather than fuzzy, values [,3]. The gain factor in the operation speed of the new controller is similar to the number of intervals required to represent the fuzzy consequent in the conventional approximation (usually about 5). The architecture of the proposed microcontroller is shown in Figure. The system s operation cycle is divided in three stages. The first samples and main-

3 K K R R X i X j MF MF From other antecedents Operation ycle MIN x k Fig.: Architecture of proposed microcontroller. tains the input values, and processes them through the membership function circuits (MFs). The second stage calculates the minimum grade of membership for each input variable, to thus obtain the compliance factor for each rule. The third stage processes the conclusions of the rules, and the output is obtained from the calculation of two partial sums and their later division. Synchronization of the system is governed by a clock of two non-overlapping phases (K and K in the figure). In addition, a shift register, with outputs labelled as R i, generates the control signals for the different switches. III. BASI BLOKS A. Membership function ircuit From other control rules ( k V k ) ( V k ) Z The basic operator in the first stage of the controller performs a nonlinear transformation of the input variables. This transformation is called the membership function and is usually approximated by a symmetric piecewise linear function as shown in Figure a (indicating the four identifying parameters: V top, V h, V c and m). To implement this transformation, a serial or a parallel procedure may be chosen. The parallel realization, shown in Figure b, takes only one clock cycle for its operation. This is a typical S structure that inverts or not the value (X-V c ) depending on the comparison between the input variable X and the voltage parameter V c. In the first phase of the first clock cycle (R ), the comparator checks to see if the input X belongs to the positive or negative slope. The result of this comparison is maintained for the next two phases (R and R ) when the value m(x-v c ) or m(v c -X) is added to the precharged voltage V top. Since slope values (m) are determined from ratios between capacitors, the circuit is directly programmable. The two horizontal lines of the membership function are generated in the next stage, together with minimum operation. It is worth pointing out some considerations regarding membership values:.- The minimum value must be zero to not take into account inactive rules when the sums k V k and V k (in Figure ) are calculated..- The range of values V k must be large enough to allow a required precision but not so large that the sum V k saturates the operational amplifier. According to the first point, the inferior horizontal line in Figure a is chosen as ground (instead of using the voltage saturation -E sat of the amplifier). So that subsequent level shifters are not needed. There are no indeterminations in the division if the rules base is well defined, that is, at least a rule is always active for any input value. Regarding the second point, a fuzzy microcontroller typically works with 4 bits precision for the member- V top V h Output m V c m X X V c o R R /m R V top Output (a) (b) Fig.: (a) Typical trapezoidal membership function. (b) ircuit which implements the dashed lines in (a).

4 ship levels. The proposed MF circuit has a structure that is insensitive to parasitic capacitances and to the offset of the operational amplifier. hoosing MOS switches of minimal geometries reduces the problems of feedthrough. As a result, capacitors lower than pf and parameter V h below v achieve a sufficient precision for the membership levels. For resolution equivalent to 6 bits in the input variables, with a range of some 4v (biased to 5v), the comparator has a margin of error of up to 30mv, thus not requiring offset cancellation techniques which would complicate the design. B. MIN Operator The basic block in the second stage of the microcontroller is a minimum operator of multiple inputs. The structure that we have used is shown in Figure 3 for a particular case of two inputs. The input voltages values are compared sequentially with that stored in capacitor. If the input voltage is less than that stored, the corresponding switch is closed and the new value is stored. On the contrary, the stored voltage is not modified. The switches are controlled by the R i s, which are the outputs of the shift register previously mentioned. In addition, the horizontally located switches depend on the comparison results (S i ). If the comparison and resolution steps are performed during the same clock phase, the associated delay provokes significant errors. This also occurs in configurations that continuously actualize the voltage value in the capacitor. Thus, in our circuit we decided to use one phase for comparison and another for resolution. onsequently, the time invested in this stage is as many clock cycles as the maximum number of antecedents in the different rules. As occurs in the previous block, sufficient precision is obtained without offset cancellation in the comparator. The operation speed of this circuit may be very fast since the only time constants involved are those of load and unload of the capacitors. So, this circuit does not limit the clock period in the complete system. V V V h R R 3 S S 3 R R 4 R i S i Fig.3: MIN serial operator of two inputs. Out To implement the minor base of the trapezoidal membership function in Figure a, the capacitor is precharged to V h during the clock phase immediately before the use of this operator (R ). The minimum grade of pertenence (ground) is implemented by another comparator, which controls the transfer of the stored charge to the following stages.. Final stage The final stage of the controller evaluates the contribution of each rule (multiplying the degree of activation calculated in the previous stage by the value associated to its consequent) and calculates the global conclusion of the system according to the following equation: Z k V = k V () k This operation is similar to the defuzzifying process of the conventional inference method, consequently the circuit that implements it is no more than a particular defuzzifier. Figure 4 presents the schematic of the circuit used. The two sums are made with typical S summators. That which implements the numerator in equation () (called the consequents block) allows a digital programming since the value k is obtained as a ratio of capacitors. For the division, we resort to the operation performed by Analog/Digital and Digital/Analog converters. In an A/D converter, from an input signal V in and a reference signal V ref a binary code (b, b,..., b n ) is obtained, such that: V in = V ref n i= b i -i () On the other hand, in a D/A converter, from a reference signal V ref and a binary code (b, b,...,b n ) the resulting output signal is: V out = V ref n i= b i -i (3) An A/D converter with input V in = k V k and V ref = V k gives a code (b, b,...,b n ) which corresponds to the value V in /V ref in binary form. Using this code as the input V in for a D/A converter the analog division value is obtained, scaled by a factor V ref. One advantage of using this scheme in the controller is that it gives both an analog and a digital output. Numerous converter structures are reported in literature, with different performance regarding precision, operation speed, and occupied area. Parallel A/D con-

5 V k R 4 R 4 other rules R 4 other rules latch bn b k V k digital output R 4 V k R 4 V ref R 4 R 5 k V k analog output Fig.4: Schematic of the final stage circuit. verters are very fast since their speed is limited only by the logical circuitry and the comparators in their make up. Normally the conversion is made in one clock cycle. However, they occupy a large area. On the contrary, in serial converters the conversion time is proportional to the number of bits, but not to the area occupied. What must be taken into account is that the two converters are coupled, in the sense that they start converting at the same bit (the most or least significant), to simultaneously obtain the digital and analog output. Since a modular design allows a simple layout, we have opted for a scheme of successive approximations based on a binary-weighted capacitor array similar to that used in the consequents block. The only difference lies in the switch control. While control in the consequents array is determined by a user-specified code, in the converters, the switches are controlled by the results of the comparison in the A/D converter. IV. OPERATION HARATERISTIS When serial converters are used for the division, they are the blocks which restrict the total speed of the system, so that, applying pipeline, the controller supplies an output every ν cycles (ν being the number of bits). If parallel converters are used only one clock cycle is taken for the division, and (+α) cycles are needed for each inference, one used by the blocks MF and α by the MIN (where α is the maximum number of antecedents in the different rules and, normally, a value lower than ν). The maximum clock frequency at which an S circuit may operate is usually limited by the transient behavior of the selected amplifier. Bearing in mind that single stage amplifiers (e.g., folded cascode) have a great speed of response, the system could reach the range of MFLIPS. V. E XAMPLE OF IMPLEMENTATION A controller has to approximate the optimum control surface of the plant which it works together. In this sense, a fuzzy controller may be considered as a surface approximator. To test our proposed scheme, we have chosen an unidimensional example such as the fitting of a sinusoidal function. After searching in a design space with discrete values for V c, m and k, our optimizing algorithm gave us a solution with 4 rules. Figure 5a shows the antecedents of these rules. In general, the absolute fitness error is mainly caused by a short number of rules and the quantification in the converters. So, the resolution of converters must be chosen according to the precision given by the rules. Figure 5b illustrates the fitness obtained in our example. The absolute error is smaller than 3% with converters of 5 bits. We have used a typical two-stage Miller amplifier, which may work with a clock period of 0.8µs. This translates to a speed of 4µs/inference (50 KFLIPS). The layout of the circuit is simple because of its modularity, as can be seen in Figure 6. The technology is MOS of.4µm and double poly. Although the area has not been optimized, the circuit occupies 3.4mm (without pads). VI. ONLUSIONS A study has been made of the application of analog techniques based on Switched apacitors in the design of

6 (a) (b) Fig.5: (a) Antecedents of the used rules, (b) fitness obtained. fuzzy controllers, proposing an architecture to implement the simplified inference method and analyzing the required circuit structures. The result of this study was to fabricate a prototype in.4 µm MOS technology that allowed operating at hundreds of KFLIPS. The performance, together with the availability of well-established design methods for S grids in MOS technology, lead us to believe that the proposed solution may be amply accepted for the construction of fuzzy controllers for specific applications, compatible with a standard processing environment. REFERENES [] M. Sasaki, N. Ishikawa, F. Ueno, T. Inoue, urrent Mode Analog Fuzzy Hardware with Voltage Input Interface and Normalization Locked Loop, Proc. IEEE Int. onf. on Fuzzy Systems, pp , San Diego, 99. [] J. L. Huertas, S. Sánchez-Solano, A. Barriga, I. Baturone, Serial Architecture For Fuzzy ontrollers: Hardware Implementation Using Analog/Digital VLSI Techniques, Proc. nd. International onference on Fuzzy Logic and Neural Networks, pp , Iizuka, 99. [3] T. Miki, H. Matsumoto, K. Ohto and T. Yamakawa Silicon Implementation for a Novel High-Speed Fuzzy Inference Engine: Mega-Flips Analog Fuzzy Processor, Journal of Intelligent & Fuzzy Systems. Vol., N., pp. 7-4, 993. [4] J. L. Huertas, S. Sánchez-Solano, I. Baturone, A. Barriga, Building Blocks for urrent-mode Implementation of VLSI Fuzzy Microcontrollers, Proc. IFSA 93, pp , Seoul, 993. [5] J. L. Huertas, S. Sánchez-Solano, A. Barriga, I. Baturone, : A Fuzzy ontroller Using Switched- apacitor Techniques, Proc. nd. IEEE Int. onf. on Fuzzy Systems, pp , San Francisco, 993. Fig.6: Layout of a proptotype implementing four rules.