A Balanced Capacitive Threshold-Logic Gate

Transcription

1 Analog Integrated Circuits and Signal Processing, 40, 61 69, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands. A Balanced Capacitive Threshold-Logic Gate JAVIER LÓPEZ-GARCÍA, JOSÉ FERNÁNDEZ-RAMOS AND ALFONSO GAGO-BOHÓRQUEZ Departmento de Electrónica, Universidad de Málaga, Bulevard Louis Pasteur s/n, Málaga, Spain javierlg@ctima.uma.es Received October 22, 2001; Revised May 1, 2003; Accepted May 13, 2003 Abstract. In this paper a new threshold gate is proposed. Its main characteristics are high fan-in (128-inputs), low delay time (8.35 ns), low power consumption (<400 µw) and optimal implementation of any threshold function. The gate can evaluate multiple input vectors in the same evaluation phase with only one clock signal. Synchronous (pipe-line) and asynchronous operations are possible, which makes it very suitable to implement logic designs with reduced depth. HSPICE simulations and simulation with files extracted from a layout in 0.6 µm double-poly CMOS technology are presented, showing the validity of the proposed gate. Key Words: threshold logic, threshold gate, digital design, neural networks 1. Introduction Traditionally, digital circuits have been implemented by means of Boolean logic. However, Threshold logic (TL) is an alternative way to implement Boolean functions. A single threshold gate is able to implement complex Boolean functions. Therefore, threshold designs have fewer logic gates and/or fewer logic levels than classical logic-gate-based designs. On the other hand, it is easily proved that any Boolean function can be carried out by a two-level threshold circuit [1]. However, in order to take advantage of these characteristics it is necessary to use gate structures of much larger fan-in in comparison with conventional logic gates. The absence of efficient designs for this type of gates on silicon has strongly limited the application of TL. The size and depth give a measure of the amount of hardware and speed of the circuit, respectively; therefore threshold circuits are a good alternative for implementing digital circuits if there are physical implementations of threshold gates with a cost (in terms of delay and chip area) that is comparable to the cost of classical gates. A linear threshold gate computes a Boolean function f (x)ofits input variables x = (x 1, x 2,...,x n ) defined by f (x) = 1 n w i x i T and f (x) = 0 otherwise (1) where w i R, (i = 1,...,n) are called weights, T represents the threshold value of the function and n the fan-in of the gate. Without loss of generality, the weights and threshold can be considered as integers [1]. The vector formed by w 1,w 2,...,w n and T is called the threshold function structure and is represented as [w 1,w 2,...,w n ; T ]. Many threshold gate designs with low fan-in and/or high power consumption have been proposed [2 5]. These designs only can compute threshold functions with relatively low weights and low performance in real applications. In Ref. [6] a new design called Capacitive Threshold Logic gate (CTL) is proposed. CTL gates have a simple regular structure, and are able to implement large fan-ins. Therefore, it has been possible to increase the applications of TL to digital filters [7], counters [8], A/D converters [9], etc., with this novel design. These applications make use of threshold functions with higher weight values, that is, a large number of inputs must be handled. However, CTL gates require

2 62 López-García et al. many external control signals: a high precision external voltage source (a few mvolts) to fix the threshold value for every gate of the circuit, and two clock signals and their complemented values. In addition, the direct realisation of functions with threshold T = 0 and negative weights is not possible with the CTL gates [6]. Other types of gates based on a latch-type comparator (LTC) [10, 11] are able to implement threshold functions with negative weights and threshold T = 0, so that, it minimizes the number of inputs necessary when complements of the input variables are available, and it also reduces the power consumption because the gate has a balanced structure with two banks of inputs [11]. In addition these gates are fast, simple, and without static power consumption; however their maximum fan-in is quite low, about 20 inputs in each bank. The LTC gates operation is based on current comparators, which are relatively sensitive to noise and mismatch of process parameters. Clearly, increasing the number of inputs reduces the allowed mismatch. This paper proposes a new design for a balancedcapacitive threshold gate, which is based on CTL and LTC gates, both discussed previously. This new gate has the following characteristics: it only needs one clock signal; the requirement for a highly precise reference voltage is eliminated by implementing functions with threshold equal to 0; and it permits asynchronous and synchronous connection, high speed operation, relatively low power consumption and optimal implementation of any threshold function. 2. Description and Circuit Operation Figure 1 shows the proposed circuit, which operates from a single 3.3 V power supply. Note that the Fig. 1. Threshold logic gate structure. gate structure is divided into two banks of capacitors (Bank A and Bank B). Both banks are connected to a well-known single-stage operational transconductance amplifier (OTA) [12] working as a comparator that determines which bank of capacitors has a large number of inputs at logic one. Two CMOS inverter type amplifiers are connected to the OTA to a single ended amplifier to form a CMOS comparator. The number of inverters is variable with respect to the required gain and time response characteristics. These inverters have been used in the circuit to obtain the output of the gate and its complement at the same time as a higher gain and speed is achieved in these outputs. Finally, analog switches have been used to connect the digital inputs (x 1, x 2,...,x m and y 1, y 2,...,y m ) with the capacitor banks. These analog switches are implemented using only one NMOS device, unlike typical transmission gate, which is composed by N- MOS and P-MOS pair and the inverter. This reduces, to a great extent, the number of CMOS transistors in threshold gates with large fan-in and it also decreases the power consumption; but the N-MOS switch also reduces the voltage level of the digital input at logic one from 3.3 to 2.4 V approximately, due to a voltage drop across the switch. This means that the maximum voltage that can be reached in the common lines of both banks of capacitors ( Nr A and Nr B in Fig. 1) is 2.4 V when all the digital inputs of the bank are logic one, and the minimum voltage is 0 V when all the digital inputs of the bank are logic zero. The interval [0, 2.4 V] will be the input voltage range to the comparator. The balanced-capacitive threshold logic (B-CTL) gate operates from one clock that switches the gate between two phases: Reset and Evaluation. These phases are generated by just one clock signal e, which simplifies the layout in circuits with a large number of threshold gates. In the Reset phase ( e = 0), all capacitors are charged to zero volts and the gate is initialized. In the Evaluation phase ( e = 1), the binary input signals are forced into the capacitors, and consequently, the voltage at the common nodes (Nr A and Nr B )is perturbed from the reset level to a final level. We can obtain this final level voltage assuming common nodes charge conservation, as follows. Let x i and y i be the binary input signals, where x i, y i {0, 1}, (i = 1,...,m) and m is the maximum number of inputs in each bank. The voltage reached at the common nodes Nr A and Nr B in the evaluation phase, assuming charge conservation, can be expressed

3 A Balanced Capacitive Threshold-Logic Gate 63 as follows: m V (Nr A ) = C i x i (V DD V TN ) C T m V (Nr B ) = C i y i + CB0 (V DD V TN ) C T where C i is the capacitance value associated to x i input (y i in Bank B), V TN is the threshold voltage of the NMOS switch, and C T is the total capacitance of every bank, m m C T = C i + CA0 = C i + CB0. The voltage reached of every bank depends on the number of digital inputs set at a high level. The bank of capacitors having a large number of them will have a higher voltage in its common node, and the voltage difference between banks is turned into a binary output by means of the comparator. If the number of inputs at logic one is the same in both banks, Bank B will have higher voltage on its common line than Bank A, since Bank B has capacitor CB0 always connected to V DD, whereas capacitor CA0 in Bank A is always connected to GND. With these extra capacitors CA0 and CB0, the correct operation of the gate is ensured by unbalancing the voltage of the common nodes when the number of inputs at level one is the same in both banks. In other situations, capacitors CA0 and CB0 will have no influence because their capacitance is half of the digital input capacitor capacitances. Although capacitor CA0 is always connected to GND, it is necessary to equalize the capacitances of the two banks. The minimum voltage difference between banks will be: V (Nr B ) V (Nr A ) = CB0 V DD = C i V DD C T 2C T The function implemented by the circuit is: } f (x) = 1 V (Nr B ) > V (Nr A ) f (x) = 0 V (Nr B ) > V (Nr A ) (2) The above Eq. (2) is expressed by voltages, but it can be expressed by binary input signals as follows: f (x) = 1 y i x i and i i f (x) = 0 otherwise (3) Fig. 2. Threshold function implementation of f (x 1, x 2, x 3 ) = x 3 x 2 + x 3 x 1. Note that (1) and (3) are functionally equivalents expressions. The circuit proposed performs threshold functions with a fan-in of n = 2m at most, where m is the number of capacitors in each bank, excluding CA0 and CB0. In order to perform a threshold function using the proposed gate, it is necessary to use several rules, which establish the way to connect the input variables to banks of capacitors A and B. This depends of the value and the sign of the weights in addition to the threshold value. As an example we consider the function f (x 1, x 2, x 3 ) = x 3 x 2 +x 3 x 1.Athreshold structure that can perform this function is f (x 1, x 2, x 3 ) = [1, 1, 2; 1]. Weight values other than one are realised by simply connecting in parallel the number of inputs indicated by the weights as shown in Fig. 2. In order to implement this function, or any function, using our circuit it is necessary to use the following rules: The absolute value of the weight indicates the number of inputs that must be connected to the input variable associated with this weight. The sign of the weight indicates the bank at which the input variable must be connected. If it is a negative weight, its associated input variable must be connected to Bank A, and if the weight is positive its associated input variable must be connected to Bank B. The absolute value of the threshold indicates the number of inputs that must be connected to V DD. This is Bank B if the threshold is negative and Bank Aifthe threshold is positive. On the other hand, if the complement of the input variables is available, a minimal threshold circuit can be obtained by a simple modification of the gate structure which must have a threshold value T = 0. This modified structure has an optimal number of inputs. The implementation of the Boolean function previously considered by means of two new structures is shown in Table 1. The threshold function structure [1, 1, 2; 3] is turned into a new structure [1, 1, 2; 0] if the

4 64 López-García et al. Table 1. Structures of the function f (x 1, x 2, x 3 ) = x 3 x 2 + x 3 x 1. f (x 1, x 2, x 3 ) = x 3 x 2 + x 3 x 1 [1, 1, 2; 3] [1, 1, 2; 0] [1, 1, 2; 3] [1, 1, 2; 0] w 1 = 1,w 2 = 1,w 3 = 2, T = 3 w 1 = 1,w 2 = 1,w 3 = 2, T = 0 x 1 one input connected to Bank B. x 1 one input connected to Bank B. x 2 one input connected to Bank B. x 2 one input connected to Bank A. x 3 two inputs connected to Bank B. x 3 two inputs connected to Bank A. V DD three inputs connected to Bank A. GND two inputs connected to Bank B GND one input connected to Bank A to equalize to equalize capacitances between banks. capacitances between banks. 8 inputs (4 per bank) are necessary 6 inputs (3 per bank) are necessary complemented inputs of x 2 and x 3 are available. The first structure is implemented using a B-CTL gate with fan-in = 8 and the second one with fan-in = 6. The last component of the BCTL gate to analyse is the comparator, which is shown in Fig. 3. This circuit has a simple and basic structure consisting of two stages. The first stage has a configuration with differential input and differential output. The second is a gain stage with an output voltage range rail-to-rail. The performance of this comparator is highly dependant on the tail current I B. The common mode input range (CMR) is obtained from the condition that the voltage at the node C should be sufficiently high to maintain M11 in the saturation region: I B 2I B V G4(min) = V G6(min) = V TN + + (4) β 4 β 11 where V TN is the N-MOS transistor threshold voltage and β 4,β 6 are the MOS transistor gain factors of M4 and M11, respectively. V G4(min) represent the minimum gate voltage of the M4 (or M6) transistor. The small signal gain is important in determining the minimum input range possible for the comparator. The larger the gain, the smaller the input range, therefore the precision of the comparator is improved and the fan-in of the threshold gate can be increased. Assuming that all the transistors are in the saturation region, and that the device pairs M1, M3; M5, M7; and M2, M8 act as current mirrors. The small signal gain of the comparator has the following value: 2 β 4 A d (5) λ 1 + λ 2 I B where λ 1 and λ 2 represent channel modulation parameters of M1 and M2 (or M7, M8), respectively. Therefore, the minimum input range possible is: V i(min) (λ 1 + λ 2 ) V DD 2 I B β 4 (6) Fig. 3. (a) Schematics of the comparator and (b) Bias. The condition for M4 and M6 are in saturation region is: I B V G4(max) = V G6(max) = V DD + V TN V TP (7) β 3 If this condition is not verified, the gain decreases and the minimum allowable input range increases.

5 A Balanced Capacitive Threshold-Logic Gate 65 Expressions (4), (6) and (7) indicate that CMR and the minimum allowable input range are improved when I B decreases, as well as the power consumption. Nevertheless, it is clear that a reduction of I B also causes an increment in the propagation delay; therefore I B should be selected as a trade-off between the fan-in of the gate and the admitted propagation delay. For a fixed value of propagation delay, the fan-in of the gate can be increased with an increment in the gain by means of the addition of new stages in cascade, which can be implemented by CMOS inverters, as is shown in Fig. 1. On the other hand, the current source circuit (Fig. 3(b)) can be turned off by means of the system clock signal in order to save power consumption at the reset phase. Therefore, the gate only consumes power in the evaluation phase. 3. Design Restrictions and Discussion As mentioned above, the main drawback of the BCTL gate comes up when the current source I B (tail-current) of the comparator is implemented. If the input vector has few inputs at high value, the voltage at the common nodes is below the lower limit of Eq. (4). This causes a gate malfunction because the voltage levels are not compared correctly. It is necessary to validate the correct behaviour of the comparator in the whole comparison range. A solution to this problem which saves a new external reference source and also avoids further design complications is based on adding a number of inputs (with their respective capacitors) to the gate permanently connected to the high level. This adds an offset voltage (V offset )atthe common nodes of the capacitor banks. This offset voltage can be determined from the lower limit of the equation (4). We must set the condition (V offset ) V G4 (min). The number of necessary extra inputs per bank (ne) that must be connected to the high level is given as the following expression: V G4(min) ne = (Fan-in) + 1 V DD V G4(min) 2 Using the transistor dimensions listed in Table 2, we have determined the parameter ne = 30 for V DD = 3.3 V, I B = 110 µa, V G4(min) = 1.05 V and Fan-in = = 128. This value of ne can be reduced, at the cost of increasing the propagation delay of the gate, which Table 2. Transistors size in Fig. 3. Transistors W (µm) L (µm) M1, M3, M5, M M4, M M2, M M9 4 1 M M allows the transistor M11 to operate in the nonsaturation region. In this case it would be verified that V G4(min) = V TN = 0.72 V and I B < 110 µa. The result is ne = 18. To reduce the silicon area required, each group of extra capacitors can be replaced by a single capacitor whose area is equal to ne C i.however, if this capacitor is connected to V DD through a CMOS switch, which is composed by the respective NMOS and PMOS transistors and the inverter, the input reaches a higher voltage than the normal digital inputs because the switch causes a lower voltage drop, and so it is possible to reduce the size of this equivalent capacitor even more. It is analogous to reduce the number of extra inputs required. In order to evaluate the performance of the proposed circuit, we have simulated several circuit structures with different fan-in, but only the results of a 128-inputs BCTL threshold gate with ne = 20 are presented. This was simulated in a 0.6 µm double-poly CMOS technology, by using the HSPICE simulator. The CMOS transistor model was the BSIM3V3, with level = 49, from Austrian Micro Systems (AMS). To ensure correct behaviour under fabrication process variations, we have run 30 Monte Carlo simulations for every critical input vector. Variations around the nominal value of the following parameters have been taken into account: σ VT = 3% for the transistor threshold voltage and σ OX = 5% for the gate oxide thickness. Every digital input has been simulated with four parallelconnected unit capacitors of 8 ff each. Moreover, random and edge capacitor errors due to the fabrication process have been considered [13]. In the following, we will specify the digital input vectors by: (na + nb, Out), where na and nb are the number of digital inputs at high level in Bank A and Bank B, respectively, and Out represent the output digital value of the gate for that input vector. The critical input vectors simulated were: ( ,1), ( ,1),

6 66 López-García et al. Fig. 4. Monte Carlo simulations using HSPICE for input vectors ( ,1) ( ,0) & (2 + 0,0) (0 + 1,1). ( ,0), ( ,1), ( ,0), ( ,1), ( ,1), ( ,0), (0 + 0,1), (2 + 0,0), (1 + 0,0) and (0 + 1,1). Figure 4 shows Monte Carlo simulations for two cycles of the gate performance when the input vectors are changed on the reset phase. In the first simulation the input vector is ( ,1), which is changed on the reset phase to ( ,0), and in the second simulation the input vector is (2 + 0,0), which is changed to (0 + 1,1). The maximum delay was 7.15 ns for the most critical input vector (0 + 0,1). Input vectors with the same number of digital inputs at logic one in both banks have higher delays because the difference in voltage between banks is lower. Moreover, we have found that the larger the fan-in the smaller the step voltage for adjacent input vectors and, consequently, the smaller the voltage difference between banks when both banks have the same number of inputs at logic one. The operation of the B-CTL gate with fan-in = 128 (64 inputs per bank) has been analysed for different combinations of inputs at logic one. Figure 5 is shows the delay time versus na (number of inputs at logic one in Bank A) and versus nb (number of inputs at logic one in Bank B). As seen in Fig. 5, the higher delays are over the na = nb line. 4. Asynchronous and Synchronous Functioning The B-CTL gate is also capable of evaluating a large number of successive input vectors in between two consecutive reset phases because the evaluation process itself is non-destructive due to charge conservation. The stored charge changes slowly because of the leakage currents through the reset analog switches S A and S B (Fig. 1), therefore a reset phase is periodically required to avoid gate malfunctioning but the frequency of this operation is very low whatever the Fan-in. Figure 6 shows a simulation in which a continuous evaluation Fig. 5. Number of inputs (na, nb) at logic one versus delay time.

7 A Balanced Capacitive Threshold-Logic Gate 67 Fig. 6. Continuous evaluation of input vectors in the same evaluation phase. Fig. 7. Asynchronous connection of BCTL gates. of input vectors within the same evaluation phase is carried out. These input vectors are changed every 15 ns. Note that e signal is scaled. This last feature permits an asynchronous connection as is shown in Fig. 7. Note that the proposed gate only needs one clock signal. This means that all threshold gates in a circuit can be sharing the same system clock signal for all of them. Moreover, no other external control signal is necessary for the circuit functioning. These qualities produce an easier circuit layout. 5. Layout Considerations and Applications A layout of the 128-inputs BCTL gate with ne = 20 in 0.6 µm double-poly CMOS technology is shown in Fig. 8. The weight-implementing capacitors are built as multiples of minimum geometry cpoly (poly1- poly2) structures. The unit weight capacitance thus implemented has an estimated value of ff and each digital input uses four unit capacitors parallelconnected. The number of extra capacitors in every bank is equal to 20. The input switches of Bank A and Bank B are arranged on the left side and on the right side, respectively, of the layout. The layout area is µm. The HSPICE simulations described in Section 3 and other delay and power consumption estimations have been verified from files extracted generated with the CADENCE design framework software for the AMS- CUQ 0.6 µm CMOS process. The deviations between the two configurations are minimal except that the maximum delay time was increased from 7.15 to 8.35 ns for the most critical input vector (0 + 0,1). Applications using only one threshold gate have been also considered from layouts. An OR function implemented for B-CTL gates with different fan-in, where a single input rises to logic one while the remaining inputs are in logic zero. The results are shown in Table 3. Another two situations more have been evaluated. In the first one, all inputs in Bank A are connected simultaneously to V DD and the inputs in Bank B are connected simultaneously to GND. In the second situation, all inputs of the gate are connected simultaneously to V DD. The results are also shown in Table 3. Another application has been a Muller C-element [14], which is commonly used for joining signal transitions to indicate the completion of an operation, which is divided into smaller operations. An m-input C-element can be viewed as a logical and of m events, where an event can be a 0 1or1 0 transition. The output of a Muller C-element is made equal to the value of input after all the inputs reach the same value; otherwise, the output remains the same. A Muller C-element with 64 inputs can be implemented using a 128-inputs BCTL gate, where 63 Table 3. Delay times and power consumptions of the B-CTL gate. B-CTL gate Fan-in = 20 Fan-in = 30 Fan-in = 64 Fan-in = 128 OR function delay time ns 158 µw ns 163 µw ns 191 µw 6.85 ns 302 µw Inputs Bank A V DD 0.44 ns 165 µw 0.87 ns 181 µw 1.25 ns 219 µw 2.67 ns 394 µw Inputs Bank B GND Inputs Bank A V DD ns 172 µw 1.17 ns 194 µw 1.38 ns 196 µw 3.46 ns 375 µw Inputs Bank B V DD

8 68 López-García et al. Fig. 8. Layout of 128-inputs BCTL gate. inputs of Bank B are connected to the output of the gate and one input of this bank is connected to logic zero. The inputs of the Muller C-element are the inputs of the Bank A. The Muller C-element output changes between logic levels for (0 + 0,1) and ( ,0) input vectors. The maximum delay time of this Muller C-element is 8.35 ns, which coincides with the propagation delay of the input vector (0 + 0,1). 7. Conclusions A new CMOS threshold-logic gate has been proposed. Simulation results of 128-input gates indicate that this threshold gate can operate with high fan-in, low power consumption, and asynchronous/synchronous functioning. This design eliminates dependency on a highly precise external analog reference voltage. The gate developed is a generic threshold gate in which the threshold function is carried out by comparison between two capacitor arrays that perform the arithmetic operation of sum-of-products. OR-functions and Muller C-element applications have been considered for the proposed gate. Other possible applications are the design of efficient binary adders [15] and arithmetic circuits, in general, with high reliability, real-time digital signal processing, and neural networks on silicon. In these kinds of applications threshold functions with a low number of logic levels are necessary, but this means threshold gate structures with high weight values. Therefore, threshold gates with high fan-in are required. Acknowledgment The authors wish to thank the anonymous referees for their constructive comments. References 1. S. Muroga, Threshold Logic And its Applications. Wiley Interscience: New York, S.L. Hurst, An introduction to threshold logic: A survey of present theory and practice. The Radio and Electronic Engineer, pp , A.L. Larson, A TTL compatible threshold gate. IEEE Journal of Solid-State Circuits, vol. SC-8, pp , K.J. Schultz, R.J. Francis, and K.C. Smith, Ganged CMOS: Trading standby power for speed. IEEE J. Solid-State Circuits, vol. 25, no. 6, pp , 1990.

9 A Balanced Capacitive Threshold-Logic Gate T. Shibata and T. Omi, A functional MOS transistor featuring gate-level weighted and threshold operations. IEEE Transactions on Electron Devices,vol. 39, no. 6, pp , H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Çilingiroglu, A capacitive threshold-logic gate. IEEE J. Solid- State Circuits, vol. 31, no. 8, pp , I. Hatirnaz, F.K. Gurkaynak, and Y. Leblebibi, Realisation of a programmable rank order filter architecture using capacitive threshold logic gates. ISCAS99, 1999 IEEE International Symposium on Circuits and Systems, Y. Leblebibi, H. Özdemir, A. Kepkep, and U. Çilingiroglu, A compact parallel (31,5)-counter circuit based on capacitive threshold-logic gates. IEEE Journal of Solid-State Circuits, vol. SC-31, pp , A. Schmid, D. Bowler, R. Baumgartner, and Y. Leblebibi, A novel analog-digital flash converter architecture based on capacitive threshold logic gates. ISCAS99, 1999 IEEE International Symposium on Circuits and Systems, M.J. Avedillo, J.M. Quintana, A. Rueda, and E. Jiménez, Low power CMOS threshold logic gate. Electronics Letters, vol. 31, no. 25, pp , J. Fernandez-Ramos, J.A. Hidalgo-López, M.J. Martín, J.C. Tejero, and A. Gago, A threshold-logic gate based on clocked coupled inverters. International Journal of Electronics, vol. 84, no. 4, pp , F. Krummenacher, High voltage gain CMOS OTA for micropower SC filters. IEE Electronic Letters, vol. EL-17, no. 4, p. 170, J.B. Shyu, G.C. Temes, and K. Yao, Random errors in MOS capacitors. IEEE J. Solid-State Circuits, vol. SC-17, pp , D.E. Muller, W.S. Bartky, A theory of asynchronous circuits. Proc. Int. Symp. on Theory of Switching, vol. 29, pp , J. Fernandez Ramos and A. Gago, Two operand binary adders with threshold logic. IEEE Transactions on Computers, vol. 48, no. 12, pp , circuits design with Threshold Logic and low-voltage high-speed analog integrated circuit design. José Fernández-Ramos received the degree of Licenciado en Ciencias Físicas (Branch of Electronics) from the University of Seville, Spain, in From 1984 to 1990, he worked as a design engineer in electronics of the R&D department of INFESA, Spain. In January of 1991, he joined the University of Málaga as an assistant professor in informatic and electronic engineering. He received the Ph.D. degree in March of 1998 with the dissertation on the design of arithmetic circuits with Threshold Logic. His current research interests include arithmetic circuits design with Threshold Logic and analog mixed-signal integrated circuit design for threshold gates, digital signal processing, and electronic hearing aids. Javier López-García received the M.Sc. and Ph.D. (with honors) degrees in Computer Science Engineering from the University of Málaga, Spain, in 1995 and 2001 respectively. Since 1992, he has been working at the Department of Electronic in the University of Málaga, where he is currently a Chief of Laboratories and Associate Professor of Computer Science from His current research interests include arithmetic Alfonso Gago-Bohórquez received the degree of Licenciado en Ciencias Físicas (Branch of Electronics) from the University of Seville, Spain, in In September of 1975, he joined the University of Seville as an assistant professor in physics and electronic engineering. He received the Ph.D. degree in November of 1979 with the dissertation on the design of nonlinear networks. Since 1989, he has been a professor of electronic and computer engineering with the Department of Electronics of the University of Málaga, Spain, where the heads a research group on analog and digital integrated circuit design. His current research interests include computer arithmetic, digital signal processing and electronic hearing aids.