MODELLING OF A CURRENT CONTROLLED OSCILLATOR

Transcription

1 Lebanese Science Journal, Vol. 6, No., MODELLING OF A CURRENT CONTROLLED OSCILLATOR R. Maghrebi and M. Masmoudi GMS: Group of Micro-technology and System-on-chip, Department of Electrical Engineering, National School of Engineers of Sfax, B.P. W, 3038, Sfax, Tunisia raja.maghrebi@enis.rnu.tn (Received 19 september Accepted 1 April 005) ABSTRACT This paper proposes a behavioral model for a current controlled oscillator (CCO) which will be an element of an analog behavioral library devoted to A/D converters. The analog block model will be associated with a digital block model in order to validate the conversion algorithm of a multi-slope analog to digital converter according to a proposed methodology. Results from simulations carried out using VHDL prove the validation of the CCO and are in good agreement with those obtained by electrical simulations and experimental Silicon prototypes. Keywords: current comparator circuit, current controlled oscillator, design methodology INTRODUCTION The concept of behavioral modeling has been efficiently used in digital circuits leading to a considerable reduction in the design cycle (Liu et al., 199). This concept is being applied to analogue and mixed signal blocks with the development of hardware description languages devoted to such circuits. One can cite for example the well known HDL-A and recently VHDL-AMS. Various mixed signal circuits have been described using hardware description languages. A new methodology using VHDL-AMS on a hard-disk drive design has been validated (Oudinot et al., 000). Description of analogue-to-digital converters has been presented in many works. One can cite for example the sigma-delta converter (Baraniecki et al., 1998) and the pipelined analogue-to-digital converter (Peralias et al., 000). In this context, this paper introduces a multi-slope current-mode analogue-to-digital converter model (Maghrebi et al., 001). Current-mode CMOS circuits are extremely useful and were demonstrated to provide speed and area advantages over voltage-mode circuits in circuitry design (Current, 1994). In some analogue and digital circuits, currents may be manipulated to yield more effective and/or efficient circuit realization (Freitas & Current, 1983). Several applications of current-mode CMOS circuits were presented in many studies over the past decade.

2 Lebanese Science Journal, Vol. 6, No., This study focuses on the design and modelling of a ring current-controlled oscillator (CCO). The CCO circuit will be used to conceive a multi-slope A/D converter (Maghrebi & Masmoudi, 1998). The main cell of this CCO is derived from the current threshold detector cell presented in (Freitas et al., 1983). The current threshold detector is a key component common to several CMOS Multiple-Valued Logic (MVL) such as currentmode MVL encoders and decoders, full adders, latches, current-mode latched quaternary full adders (Current, 1994), current-mode analogue to quaternary converter circuits (Current, 199). VHDL has been employed as a hardware description language to validate behavioural models and the mixed mode simulator ELDO to simulate and validate the CCO electrical circuit. This arises from the need of validating the conversion algorithm of a multi slope A/D converter as well as realizing the entire circuit within a short time. Since A/D and D/A converters are considered as good examples of mixed signal circuits, the methodology for designing A/D converters proposed in this work is also applicable for any mixed signal circuits design. Section describes the CMOS current controlled oscillator and its mode of operation. Section 3 presents the proposed methodology for designing A/D converters and the modeling of VHDL current controlled oscillator. A comparison between electrical simulations, behavioral modeling and experimental results is also provided in this section. Experimental results are illustrated in section 4. Section 5 presents the conversion algorithm of the multi-slope A/D converter and shows its validation. CMOS CURRENT CONTROLLED OSCILLATOR The simplest form of the current threshold detector cell (Freitas et al., 1983) is shown in Figure 1. M1 Figure 1. Current threshold detector.

3 Lebanese Science Journal, Vol. 6, No., The circuit is made up of diode-connected input NMOS transistor M1, and NMOS transistor M connected to replicate this input current. A reference current is applied to the drain of a diode-connected PMOS transistor M3. A PMOS transistor M4 replicates this reference current. M and M4 are connected to generate the comparator circuit's output voltage. When the input current is less than the threshold current, the output voltage provides a logical high, and when the input current is greater than the threshold current, the output voltage provides a logical low as shown in Figure. Figure. Input-output transfer characteristic of the current threshold detector. Figure shows the inversion function proved by the transfer characteristic of the current threshold detector. Therefore, an odd number of this cell may be used in a ring current controlled oscillator. To make a correspondence between the voltage output and the current input, we can modify the cell structure to obtain a voltage input by adding an NMOS transistor and a PMOS transistor as shown in Figure 3. Transistors M5 and M6 permit a voltage input of the comparator. The modified current comparator circuit and the input-output transfer characteristic are given in Figure 3 and Figure 4 respectively. Figure 3. Modified current-mode comparator.

4 Lebanese Science Journal, Vol. 6, No., Figure 4. Input-output transfer characteristic of the currentmode comparator. CURRENT CONTROLLED OSCILLATOR BEHAVIORAL MODELING Design methodology This paper focuses on the analogue part of a multi-slope self-calibrated A/D converter which is the current controlled oscillator. In order to study the whole mixed-signal system and to verify the functionality of the A/D converter, the analog and digital parts have to be described at behavioural level for simulation efficiency. The proposed methodology is illustrated in Figure 5. The proposed methodology has been applied for simulating the entire system with behavioural modelling tool, as well as for synthesizing the digital part of the multi-slope ADC reported in (Maghrebi et al., 001). This demonstrator is a 10-bit multi-slope A/D Converter. The main block of the analogue part of the A/D converter is the current controlled oscillator which model is described in the next section. The analog and digital parts of the A/D converter are modelled with the same hardware description language in order to avoid problems related to interactions between analogue and digital processes. The analog part model is needed to verify the conversion algorithm. The verification of the A/D converter model obtained by associating the analog and digital part models allows restoring and rectifying, in a first level, the digital part architecture and the analog part model or to change the basic structure of the two parts. This study focuses on the analogue part of the circuit. The validation of the analogue part model is obtained by comparing its modelling results to those obtained by simulation of the circuit at transistor level. The analog part is implemented in a standard CMOS technology.

5 Lebanese Science Journal, Vol. 6, No., CAN Analog Part Digital Part Analog Model Library Digital Library "IP" Circuit (Transistor level) Analog part Model Digital Part Model ELDO Verification & test Layout analog part A/D Converter Model Digital Part Synthesis Verification & test Vsystem LEDIT Leonardo Layout du convertisseur A/N Figure 5. Proposed design methodology. BEHAVIOURAL MODELLING To calculate the period T of the CCO, one must characterize the elementary modified current comparator cell shown in Figure 6. This is done by calculating the propagation delays for the rising edge t LH and the falling edge t HL.

6 Lebanese Science Journal, Vol. 6, No., Figure 6. Current-mode comparator. Propagation delays related to the charge and the discharge of the capacitor are obtained from the expression: I = C dvout, Where: I is the output capacitor current. dt Calculation of t LH During the capacitor charge phase, M5, M1 and M are off; the output capacitor current is equal to the drain current of M4. To calculate the propagation delay for the rising edge t LH, one can write: VDD tlh I=I ref and dt = C ref dvout I 0 0 Finally: t LH = C VDD Iref Calculation of t HL During the capacitor discharge phase, M5 is on thus making M1 and M functioning in saturation region. Since M4 is on, the output capacitor current is equal to the difference between M4 and M drain currents. According to M4 state (linear region or saturation region), the equation becomes:

7 Lebanese Science Journal, Vol. 6, No., t HL 0 dt = C V0 + V V DD TP I dvout I DM DM 4 C V DD I DM V0 + VTP dvout I DM 4 t HL = t 1 + t Where: and Between ( V + 0 VTP t 1= C t = C v0= V V0 + VTP I DM VDD VDD dvout I dvout DM 4 IDM IDM 4 V0 + VTP DD V TP.I β ref 3 ) and (V DD ), M works in the saturation region, M4 in the linear region. t 1= C VDD V0 + VTP β β 1.I ref β4 dvout ( )( ) ( Vout VDD V + ) 0 VTP VDD Vout VDD (β is the average gain constant defined as µ Cox w ) L The solution of the expression becomes: t1 = C arctg 4AD B² B 4AD B² β4 Where: A=, B= β4( VDD V0 VTP ) Between (1/VDD) and ( V + t = β V 0 VTP V β and D= V DD V Tn 4I β ref 5 ), M4 and M work in the saturation region, we can write: C 4Iref I β5 [ VDD V0 + VTp ] DD Tn ref

8 Lebanese Science Journal, Vol. 6, No., Finally: t HL = α arctgσ + t Where: α= ββ4 VDD VTn C 4Iref β5 [ β ( )] 4 VDD V0 VTP σ = ( VDD V0 VTP ) β4 4Iref ββ4 VDD VTn 5 β [ β ( )] 4 VDD V0 VTP ( DD 0+ V V Tp ) CV t= β VDD VTn 4I β ref 5 I ref By connecting an odd number of elementary cells, we obtain a ring oscillator whose period T depends on propagation delays t LH and t HL as follows: T= n.(t LH + t HL ) Where n is an odd number which represents the number of elementary cells used (three in this case). Figure 7 shows a noticeable resemblance between modelling and simulation results when comparing the curve slope and linearity. However, a variation in frequency of 10% is ascertained because the channel length modulation effects of the current mirrors in model hand calculations was not considered. When this term is neglected, the delay increases and the output signal frequency decreases. This explains the fact that the modelling curve is lower than the simulation curve as presented in Figure 7. To improve the CCO model, a multiplying factor is added to the period expression T: T = n*0.877* C I V DD ref + α arctg σ + t

9 Lebanese Science Journal, Vol. 6, No., F(MHz) F_sim F_model I(µA) Figure 7. Electrical and modelling simulation results of the CCO. In terms of linearity, the CCO model presents a good linearity. In Figure 8, linearity errors of the modelled and the simulated CCO are plotted. We notice linearity margins of 1.4% for the modelled CCO and 0.9% for the simulated CCO. These results prove the efficiency of our current controlled oscillator model as an element of a library I(µA) Nlsim Nlmodel Figure 8. Linearity of modelled and simulated CCO. EXPERIMENTAL RESULTS The oscillator prototype has been designed in a standard CMOS technology (MITEL). The circuit occupies an area of only µm² (die area). A photomicrograph of the integrated circuit is shown in Figure 9.

10 Lebanese Science Journal, Vol. 6, No., Figure 9. Current controlled oscillator photomicrograph. A good resemblance is obtained between electrical simulation results and those given by test. The relative error between test and electrical simulations is depicted in Figure 10 where an error margin of 1.1% is noticed. 1.6 Er(%) Er(sim_test) I(µA) Figure 10. Relative error between simulation results and test results of the CCO. APPLICATION: THE MULTI-SLOPE A/D CONVERTER The multi-slope A/D converter includes three similar cells as shown in Figure 11: A reference cell, an offset cell and the main cell (Maghrebi, 004).

11 Lebanese Science Journal, Vol. 6, No., The main cell of the multi-slope A/D converter is presented in the block diagram of Figure 1. The conversion algorithm is given in Figure 13. It consists of comparing the input current to a reference current during an up-count operation. Therefore subtracting an offset current (N off ) provided by an offset cell during a down-count phase. The end of conversion is achieved when no offset is detected and a full-scale value is obtained at the reference counter (N ref ). Simulation results obtained from the modelled A/D converter are depicted in figure 14 where a conversion cycle is presented. The conversion result (in this example ) is obtained when the offset and the reference counters indicate and respectively Reference current I ref Offset current I 0ff CURRENT CONTROLLED OSCILLATOR Fref UP-COUNTER Cpref DOWN- COUNTER Dcpref CURRENT CONTROLLED OSCILLATOR Foff UP-COUNTER Cpoff DOWN- COUNTER Dcpoff Digital Output N ref CONTROL LOGIC Digital Output N off DOWN- COUNTER Dcpe CLOCK Fmax Analog Input Iin CURRENT CONTROLLED OSCILLATOR Fe UP-COUNTER Cpe Digital Output Nout Figure 11. Block diagram of the multi-slope technique.

12 Lebanese Science Journal, Vol. 6, No., CONTROL LOGIC Analog input I S/H CCO F Up-down Counter N Digital output Figure 1. Main cell block diagram. N ref Digital Output N e1 N e N r N 0ff1 N 0ff T t 1 t 1 t t End of conversion Figure 13. Up-down count.

13 Lebanese Science Journal, Vol. 6, No., Figure 14. Modelling results of the A/D converter. CONCLUSION A VHDL current controlled oscillator model has been presented. The CCO constitute the analogue part of a multi-slope self-calibrated A/D converter. The analogue part model is needed to verify the digital part and therefore the entire circuit. We propose a design methodology which remains valid for designing any mixed signal circuit. The proposed methodology has been applied for simulating the entire system with behavioral modelling tool, as well as for synthesizing the digital part of the multi-slope ADC. The efficiency of our current controlled oscillator model has been shown by comparing obtained results with experimental and electrical simulation results. The design of the multi-slope self-calibrated analogue-to-digital converter is an object of the forthcoming research. One has to prove the validation of the A/D converter model by comparing modelling to test results. ACKNOWLEDGMENT Authors would like to thank J. Mouine, Professor at the University of Scherbrooke, Canada, for chip fabrication facility. REFERENCES Baraniecki, R., Dabrowski, P., Hejn, K Oversampling Σ analog-to-digital converters modeling based on VHDL. Analog Integrated Circuits and Signal Processing, 16:

14 Lebanese Science Journal, Vol. 6, No., Current, K. W Algorithmic analogue-to-quaternary converter circuit using currentmode CMOS. Electronic Letters, 8 (1). Current, K. W Current-mode CMOS multiple-valued logic circuits. IEEE Journal of Solid State Circuits, 9 (). Freitas, D. A., Current, K. W CMOS current comparator circuit. Electronic Letters, 19 (17). Liu, S and Vincentelli, S Behavioral representations for VCO and detectors in phaselock systems. IEEE Custom Integrated Circuits Conference. Maghrebi, R. and Masmoudi, M A current mode self-calibrated analog to digital converter. 10th International Conference on Microelectronics, ICM'98, Monastir, Tunisia. Maghrebi, R., Gueddah, N., Kitouni, N. and Masmoudi, M A new structure of self calibrated A/D converter. Smart Systems and Devices, SSD 001, Hammamet, Tunisia, March Maghrebi, R Contribution à la Modélisation, Conception et Test de Structures de Conversion Analogique Numérique. PhD thesis, National School of Engineers of Sfax, Tunisie. Oudinot, J., Hui-Bon-Hoa, C., Lemery, F. and Rossi, A Validation of a new methodology using VHDL-AMS on a hard-disk drive design. Deep Submicron Technical Publication. Peralias, E., Acosta, A. J., Rueda, A. and Huertas, J. L VHDL-based behavioural description of pipeline ADCs. ISCAS000 - IEEE International Symposium on Circuits and Systems, Geneva, Switzerland.