Single Electron Transistors (SET) substituting MOSFETs to Reduce Power Consumption of an Inverter Circuit

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1 nd Int'l Conf. on Electrical Engineering and Information & Communication Technology (ICEEICT) 1 ahangirnagar University, Dhaka-134, Bangladesh, 1-3 May 1 Single Electron Transistors (SET) substituting MOSFETs to Reduce Power Consumption of an Inverter Circuit Ahmed Shariful Alam, Abu Rena Md. Mustafa Kamal, Md. Abdur Rahman Dept. of EEE IUT, Gazipur, Bangladesh estiak16@yahoo.com Md. Nasmus Sakib Khan Shabbir, Atiqul Islam Dept. of EEE BUBT Dhaka, Bangladesh eng. sakib@gmail.com Abstract- Instead of MOSFET Single Electron Transistor (SET) can be used as a voltage controlled switch. The current flowing through a SET is the result of electron tunneling through tunnel j unctions of its source and drain. So the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this research work simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. Supply voltage requirement for a SET based inverter was 3mV whereas the supply voltage requirement for a CMOS inverter was 3.V. SET based inverter consumes almost million times less power than CMOS inverter. Keywords- ITRS, enhancement type MOSFET, Single electron transistor (SET), island, DC analysis, transient analysis, power consumption, background charge, co-tunneling. I. INTRODUCTION Scaling of MOSFET is important to reduce the power dissipation across that device. The advancement CMOS Technology has been doing by the engineers for almost 3 years under Moore's law. Some researchers showed that possibly CMOS cannot be scaled down further after a few next years. International Technology Road map for Semiconductors (ITRS) has determined the size of integrated circuits for next several years considering the rule of Moore's Law [1]. MOSFET is taken to be the leading electronic device in the plan of ITRS. According to ITRS the present computing hardwares are based on ' nanometer' technology node. mn technology node means the feature size (generally the gate length) of a typical MOSFET is nm. ITRS has a roadmap where 14 mn, 1 mn and 7 mn technology nodes will be the successor to nm technology node in 14, 16 and 18 respectively. MOSFET can support up to limn technology only. Hence the minimum feature size of the MOSFET does not support the 1 mn and 7 mn technology nodes. So it is clearly understood that CMOS technology is gradually getting invalid [] and reducing the power dissipation per gate of a MOSFET will no more be possible. To assure further development in this field, new switching devices must be introduced. Single Electron Transistor (SET) can work as a voltage biased switch which turns ON when tunneling current flows through it and turns OFF when tunneling current can not flow through it. According to the laws of classical physics, current can not pass through a capacitor if the capacitor is directly connected across a constant voltage source. But the quantum physics says that, there is a non vanishing probability of for an electron to pass through a thin insulating barrier or a thin capacitor. This process is known as Quantum Tunneling [3], [4]. Quantum tunneling is a random event and the magnitude of current flow due to the tunneling of electron is very low. This tunneling current is very low (in nanoampere range). So the supply voltage requirement for SET based digital circuits is also very low (typically in millivolt range). Additionally, SET has an advantage of being very small in size (quantum dots are of a few nanometers in size). So SET, an ultra-small and ultralow power consuming switching device can be a promising replacement ofmosfet in digital circuits. II. SUPPORTING THEORIES A. Structure and Theory of MOSFET In CMOS technology generally the engineers use enhancement type MOSFETs. In case of enhancement type NMOS the threshold voltage V,n (at zero body bias) is taken to be positive and in case of enhancement type PMOS the threshold voltage Vip (at zero body bias) is taken to be negative []. Fig. I. Structure and action of an enhancement type NMOS /1/$31. 1 IEEE

2 Fig. 1 and Fig. show an enhancement type NMOS and enhancement type PMOS respectively. For an NMOS the current I flows through it from drain to source and follows (1), () and (3). When NMOS is in cut off region (Vc;s :s; V,n)' In = (1) When NMOS is in resistive region (fie;s flen and S < fie;s -v,n ), V ) _ V V n s ] () D L (is In n ns n = Efin Wn [( V _ When NMOS IS m V DS Vc;s - V tn ), Here, fin = = D DL saturation region (V GS Vtn and Efin W" (V _ mobility of an electron. n V ) GS In (3) These equations [6] were used to simulate a MOSFET based inverter circuit. B. Structure and Theory of Single Electron Transistor (SET) SET represents a similar structure of a FET where channel is an Island or Quantum Dot. Each SET has three electrodes and one island. The electrodes are named as source, drain and gate. Between drain & island and source & island there are insulating tunnel junctions. Between gate and island there is a gate capacitor. Changing the gate bias voltage the condition of tunneling electron through the tunnel junctions can be controlled. Fig. 3 and Fig. 4 show the structure and circuit representation of a typical Single Electron Transistor respectively. Gate Capacitor Gate For a PMOS the current I flows through it from source to drain and follows (4), () and (6). Vso Fig. 3. Structure of a single electron transistor Fig.. c==p Type Material c== N Type Material D Metal Contact c== Semicounductor Oxide Layer Structure and action of an enhancement type PMOS W D e----1, c, c, I we----o I. When PMOS is in cut off region (Vsa :s; 1 V ip 1 ), (4) Fig. 4. Circuit represtation of a single electron transistor When PMOS IS m VSD < G -IVIp I), Efip Wp [( 1 I) I --- V resistive region (V (i 111,,, 1 and VSD ] D - D Lp SG -V Ip V SD -- When PMOS IS m saturation region (G 1v,p 1 and \T V (i -I fie" 1 ), (6) Here, = fi" mobility of a hole. () Fig. and fig. 6 explain the action of a SET. The energy of an electron in drain is expressed as Ell and the energy of an electron in source is expressed as Es. If a positive voltage is activated from source to drain then, Ell > Es. The energy of the energy level of the quantum dot or island which is not occupied by an electron is taken as E]. A single electron transistor is fabricated in such a way that Er is greater than both ED and Es (Es<Ell<E]) when there is no bias voltage applied to the gate electrode. As a result no electron can tunnel through the tunneling junctions and no current flow is observed from source to drain. When a small bias voltage is applied to the gate the Er decreases in such a way that Er comes in the range of ED and Es (Es<E] <Ell). Then electrons can tunnel through the tunneling junctions and a current flow can be observed from source to drain.

3 E I Es Fig.. Condition of available energy level of island with zero gate bias Fig. 8. Single electron transistor - schematic diagram E I When ne (where n = an integer which indicates the number of elementary charges i.e., an electron that was added to the island and e = positive elementary charge) charge is present on the island then simple electrostatics show that voltage of the island V (which is a function of n), V (n) = (ne + V;C] + VC + VU]CU] + VCiCCi + Qo) C z (7) Fig. 6. Condition of available energy level of island with positive gate bias For the purpose of proper switching another gate (gate ) has been introduced (Fig. 7). The gates are coupled with the island (sometimes which is termed as quantum dot) with two capacitors Cm and Cm respectively. Source and drain are connected with the island by two tunnel junctions. These two tunnel junctions have ultra low capacitive impedance C1 and C respectively. By the two gates the condition of flowing tunneling current from source to drain can be controlled. Here one thing should be remembered that the current flow causes due to tunneling of electrons through the two tunnel junctions. Fig. 8 shows the equivalent circuit for a SET. An output stray capacitor Co and a background charge Qo is introduced to this circuit model. SET is extremely charge sensitive which causes the background charge. The amount of electrostatic energy needed to add a charge equivalent to e can be expressed by the (8). e ev(n)+- C (8) The change of energy due to the tunneling of a charge e from a lead to the island is LlEj Assume the voltage of the lead is. So, e 11 = -ev +ev(n)+-- (9) C z Tunnel resistance, absolute temperature and the Boltzmann constant are expressed by R;, T and k respectively. Now the rate of tunneling Ii can be calculated using the change of energy due to the tunneling of a charge e. r = I1E, e R (AEi -11, kt ) (1) Higher order tunnel events where two or more charges tunnel simultaneously are called co-tunneling. Co-tunneling has been ignored here. Therefore, there are four possible ways of tunneling of charge e. They are, ru = tunneling through tunnel junction 1 towards left, ru = tunneling through tunnel junction towards left, rri = tunneling through tunnel junction I towards right, rr = tunneling through tunnel junction towards right. Fig. 7. Circuit representation of a single electron transistor (SET)

4 After determining the tunnel rates for all the pertinent charge states the probabilities of the charge states' getting occupied can be calculated from (11). pen) = p(n_ l )(rl(n-l)+rrl(n-l) (11) rr(n)+rl(n) The average current from tunnel junction 1 to can be determined from (1). (1) Then the average power dissipation for the time span, T = ten) - teo) can be easily calculated from (16), Ill. p= E T THE SIMPLEST DIGITAL CIRCUIT - AN INVERTER (17) Fig. 1 and Fig. 11 show a CMOS inverter and an inverter using SET respectively. Then island's average voltage can be determined by (13). v = 'LV(n)P(n) (13) The voltage and current can be calculated efficiently the charge state n should be calculated which has the highest possibility to be occupied. This charge state can be calculated by the (14). ( +T';"C; +VzC; +;PGj +ic;;) + C, T';" + Vz e e + (14) GND Vout The basic operation of single electron transistor can be found in [7] and all these equations which were implemented using the orthodox theory of electron tunneling [8] in SET SPICE model are available in [9]. C. Average Power Consumption Calculation This method uses the area calculation for equal time span through the whole graph. Fig. 9 shows a time vs. power dissipation curve. Area E(O) denotes the energy dissipated for the time span t( 1) - teo) which is the area covered by the power dissipation curve, time axis and the perpendiculars from the two boundary points of the curve. Thus the energy dissipated through the whole graph can be calculated from (1), N-j E = 'LE(n) (1) n=o Sometimes this area may be trapezoidal such as E(O), sometimes rectangular like E(n) or sometimes a combination of two triangles such as E(n+ 1). P( t)1 " ' r--. Vin Fig. 1. CMOS inverter Supply 3.SET l e ll l NSET Gi'ffi l e ll l I GND GND Fig. 11. SET based inverter The island of the upper SET is red colored. This means the background charge is negative. For exactly the opposite reason the island of the lower SET is blue colored. The sign of the background charge of red and blue islands are opposite but their absolute values are assumed equal. A short description on background charges and SET inverter characteristics can be found in [1]. Vout, ---.f.----f, ', '--'--+.-<...L,' _+._----,.>--- t '!- o il il G t(o) t(1) t(n) t(n+l) t(n) Fig. 9. Average power calculation algoritlun IV. COMPARISONS BETWEEN CMOS INVERTER AND SET A. Comparison of DC Analysis BASED INVERTER Both circuits were simulated in PSPICE. Fig. 1 and Fig. 13 show the simulation results of the DC analysis of inverters using MOSFET and SET respectively. From the both graphs

5 we can see that, as the input increases, the output voltage decreases. Normally the output voltage is limited between the supply voltage and zero voltage for both circuits. In case of CMOS inverter, The supply voltage = 3. V Inversion voltage = l.714 Y In case of SET built inverter, The supply voltage = 3. my Inversion voltage = mv We can see that, the in output voltage is LOW when the input voltage is HIGH and vice versa. 3 I _.----._----_.----_, g 1 \ Time Fig. 14. Transient analysis of a CMOS inverter x 1O. 1. Vin \ '1 ' Fig. 1. DC Characteristics of a CMOS inverter 1 \ 4.,,1 ' M L6 4, "-... g 'O: !------:------: !- T e ' :------: !------:, Fig. 1. Power consumption across the PMOS and the NMOS of a CMOS inverter Vin Fig. 13. DC Characteristics of a SET based inverter B. Comparison o/transient Analysis and Power Consumption The input voltage & output voltage curves and the power consumption curves across PMOS & NMOS for a CMOS inverter circuit are shown in Fig. 14 and Fig. 1 respectively. Again the input voltage & output voltage curves and the power consumption curves across PSET & NSET for a SET based inverter circuit are shown in Fig. 16 and Fig. 17 respectively. Taking power consumption values for different times the average power consumption has been calculated by MA TLAB for both circuits using the above mentioned power consumption algorithm. Following observation were made from the simulated results of MAT LAB: For a CMOS inveter: The average power dissipation across PMOS x 1- Watt. The average power dissipation across NMOS = x 1- Watt. The total average power dissipation across the CMOS inverter = x 1- Watt.

6 .36 V. RESULTS AND CONCLUSION m C m 'M > 1 1 O.M.36 m m 1 1 O.M \ \ I 11O The PSPICE DC analysis and transient analysis show similar results for both CMOS inverter and SET based inverter. The simulation results clearly show that total power consumption of a SET based inverter is almost million times less than that of a CMOS inverter. This model has been designed considering the orthodox theory [8] where co-tunneling is neglected. For more precious result we may consider it. We have a lots of potential regarding SET based technologies. Complex Logic circuit implementation using SET may be very useful. Literature shows SET-MOS Hybrid circuits have better performance. These hybrid circuits are being researched and SET can be a leading device in future technologies. Still there are many limitations in SET based digital circuits. If these limitations are minimized then SET can be a leading device in future technologies. Time 11O B 6 of-' 1 B 6. Fig. 16. Transient analysis of a SET based inverter Time Fig. 17. Power consumption across the PSET and the NSET of a SET based inverter For a SET based inveter: The average power dissipation across PSET x 1-1 Watt. The average power dissipation across NSET = 6.78 x 1-1 Watt. The total average power dissipation across the SET based inverter = x 1-1 Watt. 11" 8 [I] REFERENCES R. R. Schaller, "Technological innovation in the semiconductor industry: a case study of the international technology roadmap for semiconductors (ltrs)", PhD. Disserteation, George Mason University, Virginia, United States of America, 4. [] R. R. Schaller, "Technological innovation in the semiconductor industry: a case study of the international technology roadmap for semiconductors (ITRS)", PhD. Disserteation, George Mason University, Virginia, United States of America, 4. [3] N. Froman, and P.O. Froman, WKB Approximation: Contributions to the Theory, 1st ed., North-Holland Publishing Company, Amsterdam, 196. [4] 1. Binney, and D. Skinner, The Physics of Quantum Mechanics: An Introduction, 3rd ed., Cappella Archive, 1. [] Douglas A. Pucknell, and Kamran Eshraghian, Basic VLSI Design, 3rd ed., Prentice-Hall, 199, pp.6-1 O. [6] Linda E. M. Brackenbury, Design of VLSI systems: A Practical Introduction, Macmillan, 1987, pp [7] K. K. Likharev, "Single-Electron Devices and Their Applications," Proceedings of the IEEE, vol. 87, pp , August. [8] A. Scholze, "Simulation of single-electron devices," Ph.D. dissertation, Swiss Federal Institute of Technology, Zurich, Switzerland,, pp [9] G. Lientschnig, "Single-Electron and Molecular Devices," PhD. thesis, Delft University of Technology, Delft, Netherlands, November 3, pp.13-. [1]. R. Tucker, "Complementary digital logic based on the Coulomb blockade," ournal of Applied Physics, 7, 4399, 199.