Low Voltage and Power Efficient Double Tail Comparator with Reduced Delay Time

Transcription

1 Low olae and Power Efficien Double Tail omparaor wih Reduced Delay Time Madhuri Madasu M.Tech Suden in LS Desin, Deparmen of EE, Dhanekula nsiue of Enineerin and Technoloy, Ganuru, Krishna Disric, A.P. Dr.G.L.Madhumahi Professor & HOD, Deparmen of EE, Dhanekula nsiue of Enineerin and Technoloy, Ganuru, Krishna Disric, A.P. Absrac: One of he main buildin blocks in many appli-caions is he analoue-o-diial converer (AD), which serves as an inerface beween he analoue world and he diial processin uni. n all hese desins, he comparaor of he AD is one he buildin block. For power efficiency and o decrease he delay, AD s make use of dynamic reeneraive comparaors. n his paper, he delay of he dynamic comparaors is analysed and expressions are deri-ved. From he analyical expressions, he main fac-ors which are conribued o he comparaor delay and radeoffs in dynamic comparaor desin are explored. Based on he presened analysis, a new dynamic comparaor is proposed, where he circui of a convenional double ail comparaor is modified for low-power and fas operaion even in small supply volaes. Wihou complicain he desin and by addin few ransisors, he posiive feedback durin he reeneraion is srenhened, which resuls in remarkably reduced delay ime. Pos-layou simulaion resuls in a 0.18-μm MOS echn-oloy confirm he analysis resuls. is shown ha in he proposed dynamic comparaor boh he power consumpion and delay ime are sinificanly reduc-ed in he maximum clock frequency ranes of GHz wih 0.8 power supply. ndex Terms: Double-ail comparaor, dynamic clocked comparaor, hihspeed analo-o-diial converers (ADs), lowpower analo desin. 1.NTRODUTON: One of he fundamenal buildin block of mos analoo-diial converers (ADs) is he OMPARATOR. Many hih speed AD s, such as flash AD s require hih-speed, low power comparaors wih small chip area. Especially, when we consider he hreshold volaes of he devices have no been scaled a he same pace as he supply volaes of he modern MOS processes [1], hih speed comparaors in ulra deep sub-micromeer (UDSM) MOS suffer from low supply volaes. So, when he supply volae is smaller, he ask of desinin of hih speed comparaors is a challene. n oher words, larer ransisors are required o compensae he reducion of supply volae a a iven echnoloy o achieve hih speed. also means ha more die area and power is needed. Low-volae operaion resuls in limied common-mode inpu rane, which is imporan in many hih speed AD archiecures, such as he flash ADs. To mee he low vol-ae desin challenes, many echniques, such as supply boosin mehods [2],[3], echniques employin body-driven ransisors[4],[5], curren-mode desin[6], and hose usin dual-oxide processes, which can handle hiher supply volaes have been developed. Based on aumenin he supply, reference, or clock volae, Boosin and boosrappin are wo echniques o address inpurane and swichin problems. These are effecive echniques, bu hey inroduce reliabiliy issu-es especially in he echnoloies of UDSM MOS. Body driven echnique adoped by Blalock[4] removes he hreshold volae requiremen so ha body driven MOSFET operaes as a depleion ype device. A 1-bi quanizer for sub-1 modulaors is proposed based on his approach[5]. Pae 355

2 Bu, he bodydriven ransisor suffers from he smaller ransconducance (equal o mb of he ransisor) compared o is ae-driven counerpar. While special fabricaion process, such as deep n-well is required o have boh nmos and pmos ransisors operae in he body driven confiuraion. Developin new circui srucures which avoid sackin oo many ransisors beween he supply rails is preferable for low volae operaion, apar from echnoloical modify-caions, especially if hey do no increase he circui complexiy. Addiional circuiry[7]-[9] is added o he convenional dynamic comparaor o enhance he comp-araor speed in low supply volaes. The proposed comparaor works down o a supply volae of 0.5 wih a maximum clock frequency of 600 MHz and consumes 18 μw. Despie he effeciveness of his approach, he effec of componen mismach in he addiional circuiry on he performance of he comparaor should be considered. The srucure of double ail dynamic comparaor[10] firs proposed is based on desinin a separae inpu and cross coupled sae. This separaion enables fas operaion over a wide common mode and supply volae rane. n his paper, a comprehensive analysis abou he delay of dynamic comparaors has been presened for various archie-cures. Furhermore, a new dynamic comparaor is pres-ened, which does no require boosed volae or sackin of oo many ransisors. Merely, by addin a few minimum size ransisors o he convenional double ail dynamic comparaor, lach delay ime is profoundly reduced. This modificaion also resuls in considerable power savins when compared o he convenional dynamic comparaor and double ail comparaor. 2. LOKED REGENERATE OMPARATORS locked reeneraive comparaors make fas decisions due o he sron posiive feedback in he reeneraive lach, so hey found wide applicaions in many hih speed AD s. These comparaors are used o invesiae in differen aspecs noise [11], offse [12], [13], [14] random decision errors[15], and kickback noise [16]. Bu in his paper only delay analysis of convenional dynamic and convenional double ail comparaor is analysed and based on ha proposed comparaor is presened. 2.1 onvenional dynamic omparaors: The schemaic diaram of he convenional dynamic comparaor is shown in fiure 2.1 Fiure : Schemaic diaram of convenional dynamic omparaor They are widely used in A/D converers. They have hih inpu impedance, rail-o-rail oupu swin and no saic power consumpion. The operaion of convenion-nal dynamic comparaor is as follows: has 3 phases of operaion, ha are rese phase, comparison phase, lach reeneraion phase. Durin he rese phase, when he LK is low(=0), he ail ransisor (T ail ) is OFF and rese ransisors (T 7 T 8 ) pull boh oupu nodes Oun and Oup o DD o have a valid loical level o define a sar condiion durin he rese phase. n he comparison phase, when LK= DD, T ail is on, ransisors T 7 and T 8 are OFF. Dependin on he applied inpu volaes a NN and PP, he Oupu nodes (Oun and Oup) which had been prechared o DD, sar o dischare. f volae a NP ( NP ) is reaer han he volae a NN ( NN ) i.e ( NP > NN ), Oup dischares faser han Oun. when Oup (dischared by drain curren of ransisor T 2 ), falls down o DD - p before Oun (dischared by drain curren of ransisor T 1 ) and he correspondin pmos Pae 356

3 ransisor (T 5 ) will urn on iniiain he lach reeneraion caused by back-o-back inverers (T 3,T 5 and T 4,T 6 ). Thus Oup dischares o round and Oun pulls o DD. f ( NP < NN ), he circui works vice versa. Fiure 2.1.2: Transcien simulaions of onvenional dynamic omparaor wih v in = 5mv, cm = 0.7, DD = 0.8 This comparaor has 2 ime delays, o and lach. The delay 0 represens he capaciive charin of he load capaciance L (a he lach sae oupu nodes, Oun and Oup) unil he firs n-channel ransisor (T 9 / T 10 ) urns on. L hp L hp o 2.. (1) 2 n (1), since 2 = ail /2 + in = ail /2 + m1,2 in, for small differenial inpu ( in ), 2 can be approximaed o be consan and equal o he half of he ail curren. The delay lach is he lachin delay of wo cross coupled inverers. Assumin ha he volae swin of ou = DD /2 has o be obained from iniial volae difference 0 a he fallin oupu (Oup or Oun). Half of he supply volae is considered o be he hreshold volae of he comparaor followin inverer or SR lach. Hence lach ime is iven by L ou lach.ln eff 0.. (2) / 2 L DD.ln eff 0 The oal delay of he comparaor is approximaed as ail delay = o + lach L hp L DD / 2 2.ln delay (3) ail eff 0 From equaion (3) he oal delay is direcly proporion-al o he comparaor load capaciance L and inversely proporional o he inpu difference volae ( in ) and depends indirecly on inpu common volae( cm ). By decreasin cm causes smaller bias curren and delay 0 of he firs sensin phase increases. Smaller ail resuls in an increased iniial volae difference ( 0 ) reducin lach ha will finally lead o an increase in he oal dela-y. n [17], i has been shown ha an inpu common mo-de volae of 70% of he supply volae is opimal reardin speed and yield. The advanaes of his srucure is hih inpu impedan-ce, rail-o-rail oupu swin, no saic power consump-ion and ood robusness aains noise and mismach due o he parasiic capaciances of inpu ransisors do no direcly affec swichin speed of he oupu nodes and i is possible o desin lare inpu ransisors o mi-nimize he offse. On he oher hand, he disadvanae is due o he several sacked ransisors, a sufficienly hih supply volae is needed for a proper delay ime. The oher imporan drawback is ha here is only one curr-en pah via ail ransisor T ail which defines he curren for boh he differenial amplifier and he lach onvenional Double Tail Dynamic omparaors: A convenional double ail comparaor is as shown in fiure 2.2. Pae 357

4 Fiure : Schemaic diaram of onvenional double ail dynamic omparaor. When compared o convenional dynamic comparaor, his srucure has less sackin so i can operaes a lower supply volaes. The double ail enables boh a lare curren in he lachin sae and wider T ail2, for fas lachin independen of he inpu common-mode volae (cm), and a small curren in he inpu sae (small T ail1 ), for low offse. The operaion of his comparaor is as follows: Durin he rese phase LK = 0 and T ail1, T ail2 are urn-ed off and ransisors T 3 - T 4 prechare f n and f p nodes o DD, which causes ransisors T R1 and T R2 o dischar-e he oupu nodes o round. Durin decision makin phase LK= DD and T ail1, and T ail2 urn on,t 3,T 4 ra-nsisors urns off and a nodes f n and f p he previously chared volae sar o dischare. The ransisors T R1 and T R2 passes inpu dependen differenial volae f n(p) o he cross coupled inverers due o his kick-back noise will oin o reduce and ood shieldin beween inpu and oupu will be provided. Fiure 2.2.2: Transcien simulaions of onvenional double ail dynamic omparaor wih v in = 5mv, cm = 0.7, DD = 0.8. For his comparaor, he oal delay is he sum of 0 and lach. The delay 0 represens he capaciive charin of he load capaciance Lou unil he firs n channel rans-isor T 9 /T 10 urns on, afer which he lach reeneraion sars. So 0 is o Lou B1 hn 2 Lou ail 2 Where b1 is he drain curren of he ransisor T 9 (if we assume NP > NN ) hen b1 can be made half of ail2. When he ransisor T 9 of lach is in ON sae,he oupu oun will be dischared o he round poenial which makes T 8 he p-hannel ransisor o become ON sae and charin he oupu oup o he volae DD. The delay ime lach dependens on o which is he di-fference beween he node volaes a f n and f p of seco-nd sae. Where TR1,2 lach fn / fp 0 2 Thn 2 Thn ail 2 hn ail 2 niial oupu differenial volae o is influenced by wo main parameers ransconducance TR1,2 and volae difference fn/fp a oupu nodes f n and f p. delay = o + lach delay 2 Lou ail 2 hn Lou eff DD.ln / 2 0 Pae 358

5 The imporan poins can be concluded from he equaions derived for he delay of he double ail comparaor: 1. As fn/fp increases he delay of he comparaor is reduces. 2. n his omparaor he ransconducance of inermediae ransisors will improve only when inermediae sae ransisor are cu off mode which makes boh f n and f p nodes o dischare compleely. Aain in he rese phase, hese nodes have o be chared from round o supply volae which leads o consumpion of more power. 3. lach will be imbalanced due o he amplificaion of fn/fp by inermediae sae ransisors. 2.3 Proposed omparaors: n low volae applicaions, he proposed comparaor is desined based on he double ail comparaor due o he beer performance. The main idea behi-nd he proposed comparaor is o increase he diff-erenial volae fn/fp inorder o increase he lach reeneraion speed. For his purpose, wo conrol ransisor T c1 and T c2 are added o he double ail comparaor in parallel o T 3 /T 4 ransiso-rs, bu in cross coupled manner. The schemaic of prop-osed comparaor is as shown in he fiure 2.3. Operaion of proposed comparaor: The operaion of proposed comparaor is as follows: When LK=0, T ail1, T ail2 are urned off. This phase called rese phase. Durin his phase, T 3 and T 4 pulls boh f n and f p nodes o DD, hence ransisor T c1 and T c2 are cu off and inermediae ransisors rese boh lach oupus o round. When LK= DD and T ail1, and T ail2 urn on, called decision makin phase. Durin his phase, ransisors T 3 and T 4 are urnoff. A he beinnin of his phase, Since f n and f p nodes are abou DD, he conrol ransisors are sill off. Thus, f n and f p nodes sar o drop wih differen raes accordin o he applied inpu volaes. f ( NP > NN ), hen f n drops faser han f p because more curren is passed hrouh T 2 han T 1. As far as f n coninues fallin, he correspondin pmos conrol ransisor T c1 sars o urn on, pullin f p node o DD. So ha T c2 remains off and allowin f n o be dischared compleely. For convenional dynamic double ail comparaor fn/fp is jus a funcion of inpu ransisor conducance and inpu volae difference. Bu, in he proposed comparaor, as quick as compa-raor deecs node f n dischares faser, a pmos conrol ransisor T c1 urns on pulin he f p node o DD so ha he difference beween f n and fp( fn/fp ) increases in exponenial manner leadin o he reducion of lach reeneraion ime. Fiure 2.3.2: Transcien simulaions of onvenional omparaor wih v in = 5mv, cm = 0.7, DD = 0.8 Fi 2.3.1: Schemaic diaram of Proposed omparaor Delay analysis: The proposed dynamic comparaor enhances he speed of convenional dynamic double ail comparaor by affecin wo imporan facors: Pae 359

6 i) increases he iniial oupu volae difference ( o ). f o increases, reeneraion ime is less. ii) enhances he effecive ransconducance. By includin boh effecs, he oal delay of he propos-ed comparaor is achieved from delay = o + lach delay Thn 2 delay ln 4 ail 2 Thn 2 Thn Thp Lou ail 2 Lou TR1,2 ail 2 eff eff DD m1,2. Lou Lou / 2 ail 1 in TR1,2 TR1,2 * G.exp DD.ln. eff 1 o L, fn( p) / 2 O By comparin he expressions derived for he delay of he hree srucures, proposed comparaor akes advanae of an inner posiive feedback in double ail operaion, which srenhen he whole lach reeneraion. Th-is speed improvemen is even more obvious in lower supply volaes. This is due o he fac ha for larer values of h / DD, he ransconducance of he ransis-ors decreases, hus he exisence of an inner posiive fe-edback in he archiecure of he firs sae will lead o he improved performance of he comparaor. Simulai-on resuls confirm his maer. iii) Reducin he enery per conversion: is no only he delay parameer which is improved, bu he enery per conversion is reduced as well in he proposed comparaor. 3. omparison of Resuls: Srucure onvenion onvenion Proposed al Dynamic al Double omparao omparaor ail r omparaor Technolo 180 nm 180nm 180nm y Power Supply Delay 900ps 373ps 286ps Area 16 μ 16 μ 28 μ 12 μ 28 μ 14 μ Fiure 3: Layou of proposed comparaor 4. Flash Type AD: n he real world, he sinals are analo in naure. f we wan o e diial sinal, analo sinal mus be conver o diial form by usin Analo o- diial converer and if we need he analo sinal back, diial-o-analo converer is used. There are many AD archiecures which are implemened oriened on power, size and speed. The firs archiecure is pipeline AD operain in medium resoluion and hih speed bu below flash ype AD. The second one is SAR ype AD which is operain in moderae speed and medium o hih resoluion applicaions. The hird one is sima dela AD which is for hih resoluion and low speed applicaions. The fourh is Flash ype AD which is for hih speed and low resoluion applicaions. Flash AD is he fases AD in comparison wih oher AD archiecures. Flash AD is he bes ype in applicaions of hih speed low resoluion applicaions. is hihly used in hih da, hih speed insrumenaion, dae rae links, radar, and opical communicaions and diial oscilloscopes. The maximum operain frequency in he rane of iaherz because flash AD is operain in parallel conversion mehod. Here we use he proposed comparaor o reduce he delay and power of AD. 4.1 Flash Archiecure: The fases AD is he flash ype AD because is conversion speed is only one clock cycle. Flash ype AD is based on he principle of comparin analo volae wih a se of reference volaes. To conver he analo inpu volae ino a diial sinal of n-bi oupu,(2n-1) comparaors are required. Pae 360

7 The block diaram of 2-bi flash ype AD is as shown in fiure: Fiure : Block diaram of Flash ype AD consiss of 3 comparaors and encoder block is shown in he fiure Fiure : Encoder block The encoder block consiss of one xnor ae and wo and aes. Fiure : Layou of Flash ype AD onclusion: n his paper, a comprehensive delay analysis of wo srucures convenional dynamic and convenional double ail comparaor were analyzed. n order o improve he performance of he comparaor he new dynamic comparaor wih low volae and low power capabiliy is proposed. Pos layou simulaion in 180nm echnoloy confirmed ha he delay is reduced for he proposed comparaor compared o he convenional dynamic and convenional double ail dynamic comparaor. is applied o 2 bi flash ype AD and is delay and power is realy reduced. 6. REFERENES: [1] B. Goll and H. Zimmermann, A comparaor wih reduced delay ime in65-nm MOS for supply volaes down o 0.65, EEE Trans. ircuissys., Exp. Briefs, vol. 56, no. 11, pp , Nov Fiure : Simulaion resul of 2 bi flash ype AD wih PWR [2] S. U. Ay, A sub-1 vol 10-bi supply boosed SAR AD desin insandard MOS, n. J. Analo ner. ircuis Sinal Process., vol. 66,no. 2, pp , Feb [3] A. Mesarani, M. N. Ala F. Z. Nelson, and S. U. Ay, Supply boosin echnique for desinin very low-volae mixed-sinal circuis in sandard MOS, in Proc. EEE n. Midwes Symp. ircuis Sys.Di. Tech. Papers, Au. 2010, pp [4] B. J. Blalock, Body-drivin as a Low-olae Analo Desin Technique for MOS echnoloy, in Pae 361

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