Laboratory #3, 2009

Transcription

1 Laboratory #3, 2009 The purpose of this laboratory is to familiarize the class with common-source amplifier frequency response, output stage slew rate limitations, and differential pair biasing and operation. This laboratory is due at the start of your next lab. After that, there is a deduction of 20% per day, including weekends/holidays/breaks, until the value of the lab is zero. How to Write Your Lab. You may submit labs individually, or as a group. The maximum group size is three people. If you submit your labs as a group, then all group members receive identical marks. The onus is on you to ensure that your work is fairly shared, and correctly documented. The minimum contents of your laboratory write-up should answer all questions posed in the lab question sheet. If a plot is required in answering a question, then draw the plot as accurately as you can. You should label all plots fully (axes units, label different curves, etc.). Of course, feel free to use ADS (or any other software) to create the plots. Points to Ponder: You will find boxes throughout the lab with Point to Ponders inside them. You should expect some of these questions to appear on your midterm or final. Part 1: Preparing for the Laboratory. We will use a model file that I found on the MOSIS web site ( mosis.org). The model file contains nmos and pmos models for devices implemented in a 0.18µm n-well CMOS process. The models are BSIMv3.1 type models, which are considerably more complex than the simple MOSFET model that we discussed in class. You can find more information about the technology and the the model file at params/tsmc-018/t29b_mm_non_epi-params.txt. I ve already imported these models into Agilent ADS for you. You should download the model files to a local directory, and unarchive the file. The TA will explain this procedure, but in a nutshell, here s what you do: (1) Download the model files for the lab from the course blog to a local directory. (2) Start ADS. (3) Under File, choose Unarchive Project. In the window that opens, click on Browse, and navigate to the file that you just downloaded. In the To Directory box, fill in where you want to store your project files (probably your network drive). (4) Make sure that the check box Open Project After Unarchive is checked. (5) Click OK. At this point ADS will unarchive the file, and open the new project for you. You will see a directory tree, containing data, mom dsn, networks, synthesis and verification. Expand the branch for networks, and you will see a file called models.dsn. Right-click on models.dsn, choose Open in Schematic Window, 1

2 2 and ADS will open a schematic window. The schematic window will contain two models (these are the models that I imported from the MOSIS web site). You need to use these models in each of the schematics that you create during the rest of this lab. An easy way to do this is to go to File (on the schematic window) and then Save As, and save the basic schematic containing just the two models under a different filename, for each section of the lab. 1. Common Source Amplifier Frequency Response. In this section of the laboratory you will do some experimenting with common source amplifiers. If you ve looked through the notes, you should agree that a common source amplifer loaded by a current mirror can achieve some decent gain DC Biasing. What we want to do here first is try and gain some understanding of the various DC bias points required for proper operation of the amplifier. Here s what you should do: (1) First, construct the circuit shown in Figure 1. The output of this circuit is at the drain of M 1. (2) Then, generate a family of V OUT versus V BIAS curves for V BIAS between 0V and 1.8V AND I REF between 10µA and 50µA. Use the Parameter Sweep component shown in Figure 1 to perform the nested sweep. Use your best judgement on how many points to plot, what axes scale you should use, and so on. I used I REF {10µA, 20µA, 30µA, 40µA, 50µA} when I did this lab, but you can choose whatever values you want. So, after doing the above, what is the useful range of V BIAS for maximum gain from this circuit? In other words, what range of V BIAS allows all of the devices to remain in the saturation region of operation? Does the range of useful V BIAS depend on the reference current, I REF? As V BIAS is increased, which device drops out of saturation first, and why? Can you explain why a certain device drops out of saturation first using equations? And as a final question, see if you can figure out what the DC gain of the amplifier is over the range of bias currents and voltages. As I REF is increased, how does the gain vary? You might think that as I REF increases, the gain must go up because the small signal transconductance of M 3 also goes up. Is this the case? 1.2. Frequency Response. Note in Figure 1 that a sinusoidal signal rides on top of the DC bias at the gate of M 3. For DC simulations, this signal doesn t do anything, because the particular component used in the schematic is V AC, which is disabled during DC simulations. For this next portion of the lab, we re going to use an AC SWEEP in order to include the component in the simulation. The 1V AC source will be applied to the amplifier, with a varying output frequency from 1Hz to 1MHz. Modify your circuit so it looks like Figure 2 (the simulation type has been changed, and the variables are set to different values). Make a plot of the gain of the circuit in db, versus frequency (on a log scale) for the input frequency range 1Hz to 1MHz in 1kHz steps? Based on your plot, (1) What is the 3dB bandwidth of this amplifier?

3 3 DC Var Eqn DC DC1 SweepVar="VBIAS" Start=0 Stop=1.8 Step=.005 VAR VAR1 M1width=10u M2width=10u M3width=50u M1length=2u M2length=2u M3length=2u VBIAS=1 IBIAS=10u PARAMETER SWEEP ParamSweep Sweep1 SweepVar="IBIAS" SimInstanceName[1]="DC1" SimInstanceName[2]= SimInstanceName[3]= SimInstanceName[4]= SimInstanceName[5]= SimInstanceName[6]= Start=10u Stop=50u Step=10u V_DC SRC1 Vdc=1.8 V MOSFET_PMOS M2 Model=cmosp Length=M2length Width=M2width Ad=M2width*4u As=M2width*4u Pd=2*M2width+2*2u Ps=2*M2width+2*2u I_DC SRC2 Idc=IBIAS V_AC SRC4 Vac=polar(1,0) V Freq=freq V_DC SRC3 Vdc=VBIAS MOSFET_PMOS M1 Model=cmosp Length=M1length Width=M1width Ad=M1width*4u As=M1width*4u Pd=2*M1width+2*2u Ps=2*M1width+2*2u VOUT MOSFET_NMOS M3 Model=cmosn Length=M3length Width=M3width Ad=M3width*4u As=M3width*4u Pd=2*M3width+2*2u Ps=2*M3width+2*2u Figure 1. Common-source amplifier with current-mirror load. (2) What is the UGBW of the amplifier (the frequency at which the gain is 0dB) 1. (3) Is this a low pass, high pass, or band pass amplifier? Draw the small signal model for the amplifier, including the capacitors c gs, c gd, and c db for each MOSFET. Which capacitor most likely limits the bandwidth of the amplifier? Point to Ponder: Derive the 3dB-down bandwidth based on your small signal model. Get the values of c gs, c gd, c db, I DS, g ds, and g m for each MOS- FET directly from ADS (look under the Simulate Detailed Device Operating Point menu). Plug these values into your equation. Does the simulated 3dB-down frequency match your calculated value? If it doesn t, can you explain why? 1 Important note: The model file that we are using will give you incorrect results for the UGBW. I gave further instruction (in an ) on why this is so, and what to do about it.

4 4 Figure 2. Common-source amplifier with current-mirror load setup for AC analysis. 2. Output Stage Slew Rate Limitations. Next we are going to look at a practical problem encountered when designing amplifiers: what is the output load and what is its effect on our circuit operation? If I asked you to design an amplifier, and told you that the load was 2pF, what does this do to your design? 2.1. Slew Rate. We will cover this in class in some more detail, but for now, you need to have a basic understanding of slew rate. In the most basic terms, slew rate is defined as, (1) SR = dv dt If we are charging or discharging a capacitor, then we know that 2 (2) I = C dv dt. Using (1) and (2), we can write the slew rate as (3) SR = I C 2 If we assume that the capacitance is constant.

5 5 in which I is the bias current that supplies some load capacitance C. When a circuit is slewing, all available bias current is used to charge or discharge a load capacitance Simulating Slew Rate. In order to simulate slewing, we need to drive the amplifier with a pulse, and see how fast the output voltage changes. (1) First, construct the common-source amplifier MOSFET circuit shown in Figure 3. (2) Measure the slew rate of the amplifier by finding dv dt for the output voltage during a transient simulation. (3) Change the load capacitance C to 10pF. What is the slew rate now? (4) Change I REF to 35µA, and set C to 4pF. What is the slew rate? Make a table comparing the simulated slew rate to the slew rate calculated using (3). What capacitance do you use for C in (3)? Do you need to include the MOSFET capacitances? The three current probes are included in Figure 3 so that you can check where the current is coming from and going to during the transient simulation. Figure 3. Common-source amplifier with current-mirror load setup for slew test.

6 6 3. A Conundrum Point to Ponder: Holy Cow! You made it to the end of your lab, and suddenly I m going to ask you something disturbing. In all of your AC analyses, why did you use an amplitude of 1V? That isn t a small signal! Maybe you should repeat the whole lab, unless you can explain whether or not it s ok to use a 1V signal for your AC analyses. 4. Epilogue: Test Yuorself with an Amplifier Design Apply your knowledge, and design a circuit to specifications. There is no single right answer. (1) Design a common source amplifier, using either an nfet or a pfet as the transconductance device. (2) The amplifier load should be a current mirror (just a two MOSFET current mirror no cascode mirrors). (3) The minimum acceptable gain is 15dB (using G = 20 log(v out /v in )). (4) The largest input signal expected is 10µV. (5) Assume the input signal is AC coupled, so you need to bias the input node appropriately. (6) The minimum acceptable slew rate is 30 MV/S, for a maximum load of 3pF. (7) The 3dB-down bandwidth should be at least 10kHz. (8) Use the same formulas for the source and drain areas and perimeters as given in Figure 1 of this lab. Have fun with it! See if you can get the highest gain for the lowest power consumption. And in the words of David Letterman, This is only an exhibition, this is not a competition. Please, as always, ladies and gentlemen... no wagering.

7 7 Laboratory Questions: Answer the following questions and pass in your answers to your TA. Questions Relating to Section 1.1: (1) [10 Marks] What was the useful range of V BIAS for high gain from the circuit in Figure 1? In other words, what range of V BIAS allows all of the devices to remain in the saturation region of operation? (2) [10 Marks] As V BIAS was increased, which device drops out of saturation first, and why (justify using equations)? (3) [10 Marks] As I REF is increased, how does the gain vary? You might think that as I REF increases, the gain must go up because the small signal transconductance of M 3 also goes up. Is this the case? Questions Relating to Section 1.2: (1) [5 Marks] Sketch a plot of the gain of the circuit shown in Figure 2 in db, versus frequency (on a log scale) for the input frequency range 1Hz to 1MHz. (2) Based on your plot, (a) [10 Marks] What is the 3dB bandwidth of this amplifier? (b) [10 Marks] What is the UGBW of the amplifier (the frequency at which the gain is 0dB)? (c) [5 Marks] Is this a low pass, high pass, or band pass amplifier? (3) [10 Marks] Draw the small signal model for the amplifier, including the capacitors c gs, c gd, and c db for each MOSFET. (4) [10 Marks] Which capacitor most likely limits the bandwidth of the amplifier? Questions Relating to Section 2.2: (1) [10 Marks] What was the slew rate (in V/µS) when the load capacitance was 10pF? (2) [10 Marks] What was the slew rate (in V/µS) when the load capacitance was 4pF?