Next-Generation Power-Aware Design

Transcription

1 ISLPED 08 Aug. 13, 16:30-17:30, Bangalore, India Next-Generation Power-Aware Design Prof. Takayasu Sakurai Institute of Industrial Science, University of Tokyo

2 We can help in two ways for Cool Earth Green of IT Green by IT

3 Next-Generation Power-Aware Design 3D integration Deep sub-volt design Organic integrated circuits (Green by IT)

4 Power distribution is diverse I/O I/O Memory MPU1 Clock Clock Memory MPU2 Logic Logic I/O Clock ASSP1 Memory Logic Clock ASSP2 Logic I/O Memory

5 System-on-a-Chip reduces I/O power but Separate chips Logic & memory DRAM - logic interface DRAM 891mW DRAM on a chip Power 240mW 70% power reduction by DRAM embedding but expensive. VT VT 16Mbit DRAM CamDisplay I/F I/F MPEG4 codec Host I/F DRAM I/F Prefilter PLL Speech codec Multiplexer MPEG-4 Video Codec VT VT

6 3D achieves low power and high performance with reasonable cost 2D assembly Substrate < 20µm thick 3-D SiP 8 times more devices in 1mm distance More devices in closer vicinity Reducing R and C Lower power Higher performance

7 Stacked processor & cache by processor companies Heat sink from back of processor Processor, 1TFLOPS at 98W 22 mm x mm 80 cores, face down Each unit is core + router Stacked memory 256KB SRAM per core 4x C4 bump density 8490 through-si vias Package

8 New contender wireless link Capacitive and inductive-coupling links Wireless data links between stacked chips No need for additional wafer process low cost No need for ESD protection circuit high speed + low power Metal Electrode Capacitive-Coupling Link U. Tokyo and Keio U., (ISSCC 03) Metal Coil Inductive-Coupling Link Keio U. and U. Tokyo, (ISSCC 04)

9 N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro,, and T.Kuroda, "An 11Gb/s Inductive-Coupling Link with Burst Transmission," ISSCC'08, pp , Feb How were we and how are we? V T Electrode V T 10 [1] UCLA This Work E V R C C V R C SUB Data Rate [Gb/s] [2] [3] [4] [5] [7] [8] [6] Sun [10] Capacitive Inductive [12] [12] [12] I T Coil H V R =V T I T M C C C C +C SUB [9] [11] Communication Distance [μm] + V R - V R =M di T dt + - V R

10 Inductive Wireless Superconnect Connecting multiple chips Chip#3(Memory) Metal Inductor Tx Chip#3 V R Rx Tx Clock & Power Chip#2 Chip#2(Memory) V R Rx Chip#4 Analog Tx Chip#1 I T I T Rx Chip#1(Logic) D. Mizoguchi, Y. Yusof, N. Miura, T. Sakurai, T. Kuroda, "A 1.2Gb/s/pin Wireless Superconnectbased on Inductive Interchip Signaling (IIS), ISSCC 04, pp , Feb N. Miura, D. Mizoguchi, Y. B. Yusof, T. Sakurai, and T. Kuroda, Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect, Symp. on VLSI Circuits, pp June 2004.

11 120µm coils couple through stacked chips Transmitter (Top Chip) Fabricated in 180nm CMOS Tx 120µm Rx Receiver (Bottom Chip) Top Chip (40,25,10µm-Thick) Distance=45,30,15μm Bottom Chip Voltage supply by bonding does not increase power nor decrease speed.

12 Just talk without waiting for clock - fast Circuit Topology Synchronous front-end Keio U. / U. Tokyo (ISSCC 07) Txdata Txclk Pulse Generator Long Latency H Rxclk Slow Timing Controller Rxdata + - I T V R Asynchronous front-end Proposed Transceiver Txdata H-Bridge H - + I T V R Comparator Rxdata Data Rate 1Gb/s 11Gb/s Latency Energy/bit 600ps 0.4pJ/b 36ps 1.4pJ/b Simulated in 180nm CMOS

13 High-Speed Inductive-Coupling Link Transmitter Txdata Txdata Txdata [V] I T I T [ma] V R + - V B V R [mv] Rxdata Receiver Rxdata Rxdata [V] Time [ns]

14 Gps over 15µm Measured BER Tx 120µm Communication Distance, X Rx Inductive-Coupling Link X=45µm X=30µm X=15µm Data Rate [Gb/s]

15 Lower power solution in scaled CMOS Parallel 180nm CMOS (Measured) 90nm CMOS (Simulated) Burst Data Rate Energy Area Link Area Reduction by Burst Transmission 11Gb/s 30Gb/s Burst 6.4Gb/s 20.8Gb/s Link 1.4pJ/b 0.11pJ/b 45nm Burst 52.6pJ/b 11.2pJ/b Parallel* Burst 0.3mm 2 (16Links for 6.4Gb/s) 0.1mm 2 (2Links for 6.4Gb/s) 0.96mm 2 (52Links for20.8gb/s) 0.08mm 2 (2Links for 20.8Gb/s) 1/3 1/12 *Multiple Use of Data Links with 400MHz System Clock For TSV connection: E= PD =ƒcv 2 /ƒ =CV 2 ~C (V~1) = 0.03pJ/b (w/ ESD)

16 L-coupled link: low power contender 1000 Toshiba Energy per bit transfer [mw/gb/s=pj/b] NTT Hitachi Intel NEC NEC TI NEC Our Work TeraChip Our Work Our Work Rambus FlexIO Our Work Current products Year Drastically lowering power consumption of I/O s N.Miura, H.Ishikuro,, T.Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," Paper#20.2, ISSCC, Feb.2007.

17 EMI? Near Field and Far Field Signal Frequency: f [Hz] 50G 50M 50k Chip-link in SiP Far Field (Radiative) RFID (13.56MHz) RFID (135kHz) Near Field (Reactive) mm-wave WLAN RFID Cellular (2.4MHz) FM f = c/(2πx), x=λ/2π 1μm 1mm 1m 1km Communication Distance: x H.Ishikuro, N. Miura, T. Kuroda, Wideband Inductive-coupling Interface for High-performance Portable System, CICC '07, pp.13-20, Sept

18 It s not paradise: remaining issues for 3D SiP KGD (Known Good Die) At-speed testing of wafer, Wafer burn-in, Huge pin counts Heat removal and inspection of contacts Heat estimate, Testing by X-ray and ultrasonic Interposer Secure power distribution circuits, RLC testing Design environments EMC, Noise, Heat, 3D modeling, Simulation Standardization Protocol, Electrical, Physical, Testing, Logistics, Legal issues, 3D data handling

19 3D SiP house Foundry A TSV / wireless KGD test Foundry B TSV / wireless KGD Interposer, Assembly & test 3D SiP to system customer Foundry C Foundry may provide TSV service. TSV / wireless KGD test TSV by 3D SiP house is based on Via-last 3D SiP house

20 Interposer to ensure design freedom Silicon/glass or organic depends on design rule (~10µm) and cost trade-off Foundry A Foundry A TSV ed memory can be considered as one LSI product. Assembly-specific Re-distribution layer to adjust TSV location and material discrepancy among dies. Foundry A or B May experience separate shrink and multi-vendor supply.

21 Future power-aware 3D integration Stacked memories Stacked analog/rf, HV, sensors, MEMS Power control proc. HV Power grid Proc. unit Power unit Specialized blocks Sensors and information collecting circuits T. Sakurai, Low Power Digital Circuit Design (Keynote), ESSCIRC 04, pp.11-18, Sept , "Moore's Law Plus (Keynote)" VMIC, Oct

22 Next-Generation Power-Aware Design 3D integration Deep sub-volt design Organic integrated circuits (Green by IT)

23 Ultra-low voltage domain Normalized delay & power Delay Power PD product V DD [V] Normalized PD product Simulation (fitted to measurement)

24 Ring Oscillators to enable V DDmin Measurement V DD2 V DD2 V DD 1V Low swing 1V swing V SS2 V SS2 (manually tuned) V SS Ring Oscillator Output Buffer V DD -V SS of output buffer is separated from V DD2 -V SS2 of ring oscillator, so that small swing output signal can be measured. NMOS/PMOS body bias voltage of ring oscillators can be tuned independently. 0V

25 Fabricated Ring Oscillators (RO s) 90nm CMOS process, based on standard cell library Three RO s (11-stage, 101- stage and 1001-stage) More stages up to million gates in subsequent tapeout 11-stage 1mm 400µm 101-stage 1001-stage Layout Micrograph T. Niiyama, P. Zhe, K.Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM, ISQED, March, 2008.

26 V DDmin simulation V OUT 200 Voltage (mv) V OUT V DD V DDmin Time (µs) Simulation

27 V DD Dependence of Oscillation Frequency Oscillation frequency (Hz) 10G 1G 100M 10M 11-stage 1M 1001-stage 100k 13 dies 10k V DD (V) V DDmin V DDmin is defined as the supply voltage when the RO s stop oscillation and no voltage transition from the output buffer are observed. V DDmin of 11-stage ring oscillator is lower than that of 1001-stage ring oscillator.

28 Measured Die-to-Die (D2D) variations Frequency variations (= σ / average) (%) V DDmin 11-stage 13 dies 1001-stage ring oscillators V DD [V] pd Δ tpd = Δ dvth ( V V ) Frequency variations increase with reduced V DD. t pd dt DD CV DD V TH TH Δt α t V V pd Δ pd DD TH V TH Δf Δtpd α ΔV f t V V α pd DD TH TH

29 Measured WID V TH variation of 4000 MOSFET array Spectrum of V TH (A.U.) Fourier transform of V TH Spatial frequency (1/µm) The spatial spectrum doesn t show distinctive peaks at particular spatial frequencies, which indicates that the intra-die V TH variations are not systematic but purely random across 4mm. D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 x 1 Transistor Arrays in 90nm CMOS," CICC, pp , Sept mm (4000 transistors) 1000 Transistor Array 4mm Same 90nm CMOS process

30 V DD =85mV What s happening at V DDmin V 1 V 2 V 3 V 10 V V INV of inverter V 1 ~ V 11 (mv) V 2 V 6 V 9 V 4 V 11 V 7 V 8 V 10 V 1 V 3 V V INV V 1 ~V 11 Fail V OUT_LOW_7 > V INV_8 Inverter number

31 Adaptive body bias to reduce V DDmin Simulated V DDmin =89 mv (Initial) Body bias control V DDmin =87 mv The body bias of pmos is adaptively controlled to minimize V DDmin and the body bias of nmos is fixed. When a common body bias is applied to the 11 inverters, V DDmin improvement is only 2mV.

32 Fine-grained body bias to reduce V DDmin Simulated Vb1 Vb2 Vb3 Vb4 Vb5 Vb V DDmin =85 mv Vb1 Vb3 Vb5 Vb7 Vb9 Vb11 Vb2 Vb4 Vb6 Vb8 Vb V DDmin =43 mv When independent body bias is applied for every 2 inverters, V DDmin improvement is only 4mV. When inverter-by-inverter body bias is applied, V DDmin is drastically reduced to 43mV. But it is impractical.

33 Probability distribution function f x 2σ ( x) = Worst-case distribution Largest value distribution of n variables, each following Gaussian distribution 1 1 ( y x) 2 d x 1 2 e 2σ dy dx 2πσ 2 ( x x ) 1 2 2σ e 2πσ n= x σ x x + σ k SD ~ σ= σ (if n = 10 ) ( log10 n + 1) ( k+ 1) n x + 2σ Variable: x 1K x + 3σ 1G M x + 4σ x + 5σ x + 6σ x + 7σ k peak ~ x + 2 k σ (if n = 10 ) ~x+ 2 log nσ 10 CMOS VLSI design, 1989, Baifukan, ISBN C3055

34 V DDmin of million-stage ring oscillator Center V TH =0.22V Average V DDmin (mv) Measurement Matlab (Monte Carlo simulation) Model calculation x4 inverter RO Inverter RO Sim150 Sim125 Sim100 Sim k 10k 100k 1M n: Number of stages Model calculation Worst case ~ x + 2 log n σ T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators, ISLPED 08, pp , Aug

35 Next-Generation Power-Aware Design 3D integration Deep sub-volt design Organic integrated circuits (Green by IT)

36 New electronics targets physical space Environment monitoring On-demand logistics Disaster prevention Rescue support Pedestrian assistance Anti-theft Life supporting robots Environment Town & street Anormaly monitoring & alarming Physical space Interfaces Virtual space Human body Transportation system Emergency control Accident avoidance Health monitoring Remote medical assistance Home Individual adaptive marketing Smart shelf Smart cashier Production data tracking Personal data Original drawing: Professor Hiroyuki Morikawa, University of Tokyo Nano sensor-net on body Wearable

37 Frequently-mentioned features of organic IC s Advantages Low-cost manufacturing Mechanical flexibility Disadvantages Low speed (<10-3 of Si VLSI) Low density (<10-4 of Si VLSI)

38 Cost consideration Cost per function (processors, memories, analog, ) Organic Si Cost per area Good for Green by IT (sensors, display, actuators, ) Organic Si

39 Unique manufacturing process: Printing large-area organic transistor array

40 Courtesy of Professor Takao Someya, University of Tokyo Screen printing Epoxy partitions

41 Inkjet printing Gate electrodes & Word line 28 x 28 cm 2 Gate electrodes : 45 x 45 Word line : 45 lines 3 mm

42 Organic transistors Organic semiconductors: main elements --- C & H Pentacene Organic semiconductor + - Insulator Current + - Source Gate Drain Voltage OFF ON

43 I DS [µa] L=100µm, W=2mm V GS = -40V -30V -20V Modeling by SPICE level1 Measurement Simulation Level 1 SPICE MOS model S 200k G 200k D -10V V DS [V] SPICE & VLSI layout tool work.

44 Large-area electronics Human-scale interfaces E-skin Braille display Comm sheet Sheet scanner Power sheet IEDM 03 ISSCC 04 IEDM 04 ISSCC 05 Pressure sensors + OFETs Photodetectors + OFETs IEDM 05 ISSCC 06 Actuators + OFETs IEDM 06 ISSCC 07 IEDM 07 ISSCC 08 Organics + Si co-design Coils + MEMS + OFETs

45 Large-area & high efficiency Large coil Receiver coil 1 inch 2 Efficiency ~ 0.1% 30x30 cm 2 X 1 coil Electro- magnetic induction works Many coils Receiver coil & one selected 1 inch 2 Efficiency > 60% 1 inch 2 X 64 coils Selective activation is the key.

46 Combination of MEMS and OFET Power transmission coils Plastic MEMS switches Low loss Slow ~ 0.1s # of switching limited Position-sensing coils Organic FETs Resistive Faster < ms # of switching unlimited 21 x 21 cm 2 (8 x 8 cells) Wireless power transmission system Contactless positionsensing system

47 MEMS switches ~ 5mm x 10mm

48 Wireless power transmission sheet Large-area & Low cost Contactless position sensing High power Size : 21 x 21 cm2 Thickness : 1 mm Weight : 50 g Efficiency : 62.3% Max received power : 29.3 W Lightweight & Printable

49 X mas tree w/o a battery wirelessly powered 21 LEDs MHz Received power : 2 W

50 Demonstration of power transmission (Ubiquitous electronics) In the wall TV on a wall Mobile phone & PC & e-accessories (data can be wireless but USB s wire delivers power) In the table Ambient illumination Home-care robot Vacuum cleaner In the floor

51 No electrical shock I touched it by my hand. No problem

52 Next-Generation Power-Aware Design 3D integration Wireless link (0.17pJ/b 0.03pJ/b) Deep sub-volt design Watch out for random WID variation Organic integrated circuit Large-area electronics for Green by IT All can help to realize COOL EARTH through Green of IT and Green by IT.