Quad Comparator with Known Power-Up State ADCMP393

Transcription

1 FEATUES Single-supply voltage operation:.3 to 5.5 ail-to-rail common-mode input voltage range Low input offset voltage across CM: m typical Guarantees comparator output logic low from CC 0.9 to undervoltage lockout (ULO) Operating temperature range: 40 C to +5 C 4-lead standard small outline package (SOIC) 4-lead thin shrink small outline package (TSSOP) APPLICATIONS Battery management/monitoring Power supply detection Window comparators Threshold detectors/discriminators Microprocessor systems Quad Comparator with Known Power-Up State FUNCTIONAL BLOCK DIAGAM CC INA+ INA INB+ OUTB INB INC+ OUTC INC IND+ OUTD IND GND Figure GENEAL DESCIPTION The is a quad, rail-to-rail input, low power comparator ideal for use in general-purpose applications. The device operates from a single supply voltage of.3 to 5.5 and draws a minimal amount of current. The quad consumes only 6.8 µa of supply current. The low voltage and low current operation of the makes it ideal for battery-powered systems. The features a common-mode input voltage range of 00 m beyond rails, an offset voltage of m typical across the full common-mode range, and a ULO monitor. In addition, the design of the comparator allows a defined output state upon power-up. The comparator generates a logic low output while the supply voltage is less than the ULO threshold. The is available in a 4-lead narrow body SOIC and TSSOP packages. The is specified to operate over the 40 C to +5 C extended temperature range. ev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... evision History... Specifications... 3 Absolute Maximum atings... 4 Thermal esistance... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... 5 Typical Performance Characteristics... 6 Theory of Operation... 9 Basic Comparator... 9 ail-to-ail Input (I)... 9 Data Sheet Open-Drain Output...9 Power-Up Behavior...9 Crossover Bias Point...9 Comparator Hysteresis...9 Typical Applications... 0 Adding Hysteresis... 0 Window Comparator for Positive oltage Monitoring... 0 Window Comparator for Negative oltage Monitoring... Programmable Sequencing Control Circuit... Mirrored oltage Sequencer Example... 3 Threshold and Timeout Programmable oltage Supervisor... 4 Outline Dimensions... 5 Ordering Guide... 5 EISION HISTOY 0/4 ev. A to ev. B Added TSSOP Package (Throughout)... Changes to Data Sheet Title... Added Figure 3; enumbered Sequentially... 5 Changes to Open-Drain Output Section... 9 Changes to Programming Sequencing Control Circuit Section; Added Figure 5; Changes to Figure 6... Changes to Figure 7 and Figure 8... Changes to Figure Changes to Mirrored oltage Sequencer Example Section... 3 Changes to Figure 30, and Figure Added Figure 3, Outline Dimensions... 5 Changes to Ordering Guide /4 ev. 0 to ev. A Changes to Product Title... Changes to Mirrored oltage Sequencer Example Section... 4 Changes to Threshold and Timeout Programmable oltage Supervisor Section /4 evision 0: Initial ersion ev. B Page of 5

3 SPECIFICATIONS CC.3 to 5.5, TA 40 C to +5 C, CM 00 m to CC + 00 m, unless otherwise noted. Typical values are at TA 5 C. Table. Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWE SUPPLY Supply oltage CC ULOISE Guarantees comparator output low CC Quiescent Current ICC µa All outputs in high-z state, OD µa All outputs low, OD 0. UNDEOLTAGE LOCKOUT CC ising ULOISE Hysteresis ULOHYS m COMPAATO INPUT Common-Mode Input ange CM 00 CC + 00 m Input Offset oltage OS m INx+ INx m INx+ INx, TA 40 C to +85 C 5 m 5 m TA 40 C to +85 C Input Offset Current IOS 0 na CM 50 m to CC + 50 m Input Bias Current IBIAS ±30 na INx+ INx ±80 na CM 50 m to CC + 50 m ±0 na CM 50 m to CC + 50 m, TA 40 C to +85 C Input Hysteresis HYST 3 4 m CM 6 8 m COMPAATO OUTPUT Output Low oltage OL CC.3, ISINK.5 ma CC 0.9, ISINK 00 µa Output Leakage Current ILEAK 50 na OUT 0 to 5.5 COMPAATO CHAACTEISTICS Power Supply ejection atio PS db Common-Mode ejection atio CM db oltage Gain A 3 db ise Time t. µs OUT 0% to 90% of CC Fall Time tf 0.5 µs OUT 90% to 0% of CC Propagation Delay Input ising tpop_ 4.7 µs CM, CC.3, OD 0 m 4.9 µs CM, CC 5, OD 0 m.8 µs CM, CC.3, OD 00 m 3. µs CM, CC 5, OD 00 m Input Falling tpop_f 4.5 µs CM, CC.3, OD 0 m 9.5 µs CM, CC 5, OD 0 m µs CM, CC.3, OD 00 m 4. µs CM, CC 5, OD 00 m OD overdrive voltage. PULLUP 0 kω, and CL 50 pf. ev. B Page 3 of 5

4 ABSOLUTE MAXIMUM ATINGS Table. Parameter ating CC Pin 0.3 to +6 All INx+ and INx Pins 0.3 to +6 All OUTx Pins 0.3 to +6 OUTx Pins Sink Current (ISINK) 0 ma Storage Temperature ange 65 C to +50 C Operating Temperature ange 40 C to +5 C Lead Temperature (0 sec) 300 C Junction Temperature 50 C THEMAL ESISTANCE Data Sheet Table 3. Thermal esistance Package Type θja Unit 4-Lead Narrow-Body SOIC 80 C/W 4-Lead TSSOP 5 C/W ESD CAUTION Stresses at or above those listed under Absolute Maximum atings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ev. B Page 4 of 5

5 PIN CONFIGUATION AND FUNCTION DESCIPTIONS OUTB 4 OUTC 3 OUTD CC 3 GND INA 4 TOP IEW IND+ INA+ 5 (Not to Scale) 0 IND INB 6 9 INC+ INB+ 7 8 INC Figure. SOIC Pin Configuration OUTB 4 OUTC CC 3 3 OUTD GND INA 4 TOP IEW (Not to Scale) IND+ INA+ INB INB IND INC+ INC Figure 3. TSSOP Pin Configuration 08-0 Table 4. Pin Function Descriptions Pin No. Mnemonic Description OUTB Comparator B Output, Open Drain Comparator A Output, Open Drain 3 CC Device Supply Input 4 INA Comparator A Inverting Input 5 INA+ Comparator A Noninverting Input 6 INB Comparator B Inverting Input 7 INB+ Comparator B Noninverting Input 8 INC Comparator C Inverting Input 9 INC+ Comparator C Noninverting Input 0 IND Comparator D Inverting Input IND+ Comparator D Noninverting Input GND Device Ground 3 OUTD Comparator D Output, Open Drain 4 OUTC Comparator C Output, Open Drain ev. B Page 5 of 5

6 Data Sheet TYPICAL PEFOMANCE CHAACTEISTICS INPUT OFFSET OLTAGE (m) SAMPLE SAMPLE SAMPLE 3 INPUT OFFSET OLTAGE (m) T A +5 C T A +85 C T A +5 C T A 40 C COMMON-MODE OLTAGE () Figure 4. Input Offset oltage (OS) vs. Common-Mode oltage (CM), CC SUPPLY OLTAGE () Figure 7. Input Offset oltage (OS) vs. Supply oltage (CC), CM for arious Temperatures INPUT OFFSET OLTAGE (m) CC.3 CC 3.3 CC 5.5 OUTPUT OLTAGE () IN+ IN + 0m CM IN TEMPEATUE ( C) SUPPLY OLTAGE () Figure 5. Input Offset oltage (OS) vs. Temperature for arious Supply oltages (CC), CM Figure 8. Output oltage (OUT) vs. Supply oltage (CC), PULLUP 0 kω T A +5 C T A +85 C T A +5 C T A 40 C T A +5 C T A +85 C T A +5 C T A 40 C SUPPLY CUENT (µa) SUPPLY CUENT (µa) SUPPLY OLTAGE () Figure 6. Supply Current vs. Supply oltage at Output Low oltage for arious Temperatures SUPPLY OLTAGE () Figure 9. Supply Current vs. Supply oltage at Output High oltage for arious Temperatures ev. B Page 6 of 5

7 SUPPLY CUENT (µa) SUPPLY CUENT (µa) TEMPEATUE ( C) TEMPEATUE ( C) Figure 0. Supply Current vs. Temperature at Output High oltage for arious Supply oltages Figure 3. Supply Current vs. Temperature at Output Low oltage for arious Supply oltages INPUT HYSTEESIS (m) CC.3 CC 3.3 CC TEMPEATUE ( C) INPUT HYSTEESIS (m) T A +5 C T A +85 C.9 T A +5 C T A 40 C SUPPLY OLTAGE () Figure. Input Hysteresis vs. Temperature for arious Supply oltages (CC), CM Figure 4. Input Hysteresis vs. Supply oltage for arious Temperatures, CM 8 7 CC.3 CC 3.3 CC 5.5 PULLUP 0kΩ OD 0m C L 50pF CM 4 CC.3 CC 3.3 CC 5.5 PULLUP 0kΩ OD 0m C L 50pF CM POPAGATION DELAY (µs) POPAGATION DELAY (µs) TEMPEATUE ( C) Figure. Propagation Delay vs. Temperature, Low to High, OD 0 m TEMPEATUE ( C) Figure 5. Propagation Delay vs. Temperature, High to Low, OD 0 m ev. B Page 7 of 5

8 Data Sheet CC.3 CC 3.3 CC 5.5 PULLUP 0kΩ C L 50pF CM 0 9 CC.3 CC 3.3 CC 5.5 PULLUP 0kΩ C L 50pF CM POPAGATION DELAY (µs) POPAGATION DELAY (µs) INPUT OEDIE OLTAGE (m) Figure 6. Propagation Delay vs. Input Overdrive oltage, Low to High INPUT OEDIE OLTAGE (m) Figure 8. Propagation Delay vs. Input Overdrive oltage, High to Low CC 3.3 C L 50pF CC 3.3 C L 50pF OUTPUT OLTAGE ISE TIME (µs) OUTPUT OLTAGE FALL TIME (µs) PULL-UP ESISTANCE (kω) Figure 7. Output oltage ise Time (t) vs. Pull-Up esistance (PULLUP) PULL-UP ESISTANCE (kω) Figure 9. Output oltage Fall Time (tf) vs. Pull-Up esistance (PULLUP) ev. B Page 8 of 5

9 THEOY OF OPEATION BASIC COMPAATO In its most basic configuration, a comparator can be used to convert an analog input signal to a digital output signal (see Figure 0). The analog signal on INx+ is compared to the voltage on INx, and the voltage at OUTx is either high or low, depending on whether INx+ is at a higher or lower potential than INx, respectively. IN + 0 INx+ INx IN CC + OUT OUTx Figure 0. Basic Comparator and Input and Output Signals AIL-TO-AIL INPUT (I) Using a CMOS noni stage (that is, a single differential pair) limits the input voltage to approximately one gate-to-source voltage (GS) away from one of the supply lines. Because GS for normal operation is commonly more than, a single differential pair input stage comparator greatly restricts the allowable input voltage. This restriction can be quite limiting with low supply voltages. To resolve this issue, I stages allow the input signal range to extend up to the supply voltage range. In the case of the, the inputs continue to operate 00 m beyond the supply rails. OPEN-DAIN OUTPUT The has an open-drain output stage that requires an external resistor to pull up to the logic high voltage level when the output transistor is switched off. The pull-up resistor must be large enough to avoid excessive power dissipation, but small enough to switch logic levels reasonably quickly when the comparator output is connected to other digital circuitry. The rise time of the open-drain output depends on the pull-up resistor (PULLUP) and load capacitor (CL) used. The rise time can be calculated by t. PULLUP CL () t POWE-UP BEHAIO On power-up, when CC reaches 0.9, the is guaranteed to assert an output low logic. When the voltage on the CC pin exceeds ULO, the comparator inputs take control. COSSOE BIAS POINT ail-to-rail inputs of this type of architecture, in both op amps and comparators, have a dual front-end design. PMOS devices are inactive near the CC rail, and NMOS devices are inactive near GND. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally 0.8 and CC 0.8, the measured offset voltages change. COMPAATO HYSTEESIS In noisy environments, or when the differential input amplitudes are relatively small or slow moving, adding hysteresis (HYST) to the comparator is often desirable. The transfer function for a comparator with hysteresis is shown in Figure. As the input voltage approaches the threshold (0 in Figure ) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +HYST/. The new switch threshold becomes HYST/. The comparator remains in the high state until the HYST/ threshold is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on the 0 input cannot cause the comparator to switch states unless it exceeds the region bounded by ±HYST/. HYST OUTPUT OL 0 OH INPUT + HYST Figure. Comparator Hysteresis Transfer Function ev. B Page 9 of 5

10 TYPICAL APPLICATIONS ADDING HYSTEESIS To add hysteresis, see Figure ; two resistors are used to create different switching thresholds, depending on whether the input signal is increasing or decreasing in magnitude. When the input voltage increases, the threshold is above, and when the input voltage decreases, the threshold is below. CC 5 Data Sheet WINDOW COMPAATO FO POSITIE OLTAGE MONITOING When monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by M, IM is the nominal current through the resistor divider, O is the overvoltage trip point, and U is the undervoltage trip point. M.5 IN INx+ INx OUTx PULLUP LOAD X PH Y INA+ INA PL INB+ INB OUTB OUT Z 08-0 Figure 3. Positive Undervoltage/Overvoltage Monitoring Configuration Figure. Noninverting Comparator Configuration with Hysteresis The upper input threshold level is given by IN_HI ( + ) () Assuming LOAD >>, PULLUP. The lower input threshold level is given by IN ( + + ) PULLUP CC _ LO (3) + PULLUP The hysteresis is the difference between these voltages levels. Δ IN IN_LO IN_HI CC IN (4) + PULLUP Figure 3 illustrates the positive voltage monitoring input connection. Three external resistors, X, Y, and Z, divide the positive voltage for monitoring, M, into the high-side voltage, PH, and the low-side voltage, PL. The high-side voltage is connected to the INA+ pin and the low-side voltage is connected to the INB pin. To trigger an overvoltage condition, the low-side voltage (in this case, PL) must exceed the threshold on the INB+ pin. Calculate the low-side voltage, PL, by the following: Z PL O X + Y + Z (5) In addition, X + Y + Z M/IM (6) Therefore, Z, which sets the desired trip point for the overvoltage monitor, is calculated as ( )( M ) Z I (7) ( )( ) O M To trigger the undervoltage condition, the high-side voltage, PH, must be less than the threshold on the INA pin. The high-side voltage, PH, is calculated by Y + Z PH U (8) X + Y + Z Because Z is already known, Y can be expressed as ( )( M ) Y (9) I ( )( ) Z U M When Y and Z are known, X can be calculated by X (M/IM) Y Z (0) If M, IM, O, or U changes, each step must be recalculated. ev. B Page 0 of 5

11 WINDOW COMPAATO FO NEGATIE OLTAGE MONITOING Figure 4 shows the circuit configuration for negative supply voltage monitoring. To monitor a negative voltage, a reference voltage is required to connect to the end node of the voltage divider circuit, in this case,. Z NH Y NL INC+ INC IND+ IND OUTC OUTD Because Z is already known, Y can be expressed as follows: M Z Y (5) I M U When Y and Z are known, X is then calculated by M X Y Z (6) I M POGAMMABLE SEQUENCING CONTOL CICUIT The circuit shown in Figure 5 is used to control the power supply sequencing. The delay is set by the combination of the pull-up resistor (PULLUP), the load capacitor (CL), and the resistor divider network. / CC Figure 4. Negative Undervoltage/Overvoltage Monitoring Configuration Equation 7, Equation 9, and Equation 0 need some minor modifications for use with negative voltage monitoring. The reference voltage,, is added to the overall voltage drop; therefore, it must be subtracted from M, U, and O before using each of them in Equation 7, Equation 9, and Equation 0. To monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between and the negative supply voltage into the high-side voltage, NH, and the low-side voltage, NL. The high-side voltage, NH, is connected to INC+, and the low-side voltage, NL, is connected to IND. To trigger an overvoltage condition, the monitored voltage must exceed the nominal voltage in terms of magnitude, and the high-side voltage (in this case, NH) on the INC+ pin must be more negative than ground. Calculate the high-side voltage, NH, by the following: NH In addition, X Y GND O () O X Y Z M X Y Z () I M Therefore, Z, which sets the desired trip point for the overvoltage monitor, is calculated by M Z (3) I M O To trigger an undervoltage condition, the monitored voltage must be less than the nominal voltage in terms of magnitude, and the low-side voltage (in this case, NL) on the IND pin must be more positive than ground. Calculate the low-side voltage, NL, by the following: NL X M X GND U (4) U X Y Z 08-0 ev. B Page of 5 SEQ PULLUP C L INA+ INA INB+ INB INC+ INC IND+ IND OUTD Figure 5. Programmable Sequencing Control Circuit Figure 6 shows a simplified block diagram for the programmable sequencing control circuit. The application delays the enable signal, EN, of the external regulators (LDO x) in a linear order when the open-drain signal (SEQ) changes from low to high impedance. The has a defined output state during startup, which prevents any regulator from turning on if CC is still below the ULO threshold. 3.3 / CC t t SEQ t 3 t 4 GND IN OUT LDO EN GND IN OUT LDO EN GND IN OUT LDO 3 EN GND IN OUT LDO 4 EN GND Figure 6. Simplified Block Diagram of a Programmable Sequencing Control Circuit U OUTC OUTB 08-5

12 Data Sheet SEQ CL OUTB OUTC OUTD Figure 7. Programmable Sequencing Control Circuit Timing Diagram When the SEQ signal changes from low to high impedance, the load capacitor, CL, starts to charge. The time it takes to charge the load capacitor to the pull-up voltage (in this case, or CC) is the maximum delay programmable in the circuit. It is recommended to have the threshold within 0% to 90% of the pull-up voltage. Calculate the maximum allowable delay by tmax t. PULLUP CL (7) The delay of each output is changed by changing the threshold voltage, to 4, when the comparator changes its output state. To calculate the voltage thresholds for the comparator, use the following formulas: t PULLUPC L e (8) 3 t t t PULLUP C L e (9) t 3 PULLUP C L e (0) t 4 t 3 t 4 PULLUPC 4 L e () The threshold voltages can come from a voltage reference or a voltage divider circuit, as shown in Figure First, determine the allowable current, IDI, flowing through the resistor divider. After the value for IDI is determined, calculate,, 3, 4, and 5 using the following formulas: DI () I DI DI (3) DI (4) 3DI 3 (5) 4DI 4 3 (6) 5 DI 3 4 (7) To create a mirrored voltage sequence, add a resistor, MIO, between the pull-up resistor (PULLUP) and the load capacitor (CL) as shown in Figure 8. SEQ / CC PULLUP MIO C L INA+ INA INB+ INB INC+ INC IND+ IND Figure 8. Circuit Configuration for a Mirrored oltage Sequencer Figure 8 shows the circuit configuration for a mirrored voltage sequencer. When SEQ changes from low to high impedance, the response is similar to Figure 7. When SEQ changes from high impedance to low, the load capacitor (CL) starts to discharge at a rate set by MIO. The delay of each comparator is dependent on the threshold voltage previously set for t to t4. The result is a mirrored power-down sequence. U OUTB OUTC OUTD 08-7 ev. B Page of 5

13 SEQ CL t 4 t 5 OUTB t 3 t 6 OUTC t t 7 OUTD t t Figure 9. Mirrored oltage Sequencer Timing Diagram The timing diagram for the mirrored voltage sequencer is shown in Figure 9. Equation 8 through Equation must account for the additional resistance, MIO, in the calculations of the voltage thresholds. To calculate these new thresholds, see Equation 8 through Equation 3. t ( PULLUP + MIO ) CL e (8) t ( PULLUP + MIO ) CL e (9) t 3 ( PULLUP + MIO ) CL 3 e (30) t 4 ( PULLUP + MIO ) CL 4 e (3) MIO provides the mirrored delay by prolonging the discharge time of the capacitor. The mirrored voltage sequencer uses the same threshold in Equation 8 to Equation 3 in a decreasing order. To calculate the exact value of the mirrored delay time, see Equation 3 through Equation 35. t t t MIO MIO MIO 4 C Lln (3) 3 C Lln (33) C Lln (34) t 8 MIOCLln (35) MIOED OLTAGE SEQUENCE EXAMPLE To illustrate how the mirrored voltage sequencer works, see Figure 6 and then consider a system that uses a of and requires a delay of 50 ms when SEQ changes from low to high impedance, and between each regulator when turning on. These considerations require a rise time of at least 00 ms for the pull-up resistor (PULLUP) and the load capacitor (CL). The sum of the resistance of MIO and PULLUP must be large enough to charge the capacitor longer than the minimum required delay. For a symmetrical mirrored power-down sequence, the value of MIO must be much larger than PULLUP. A 0 kω PULLUP value limits the pull-down current to 00 µa while giving a reasonable value for MIO. A typical µf capacitor together with a 50 kω MIO value gives a value of tmax.(( ) ( 0 6 )) 35 ms (36) The threshold voltage required by each comparator is set by Equation 8 to Equation 3. For example, 60 e where m Therefore, m, m, and m. Next, consider 0 µa as the maximum current (IDI) flowing through the resistor divider network. This current gives the total resistance of the divider network (DI) and the individual resistor values using Equation to Equation 7, resulting in the following: DI 00 kω 6.84 kω 6.7 kω 9.64 kω 9.6 kω kω 4.3 kω kω 0.5 kω kω 8.7 kω ev. B Page 3 of 5

14 esistor values from the calculation are nonindustry standard, using industry standard resistor values resulted in a new DI value of 99.8 kω. Due to the discrepancy of the calculated resistor value to the industry standard value, the threshold of each comparator also changed. Calculate the new threshold values by using a simple voltage divider formula: /DI (37) where ( 6.7 kω) 99.8 kω m. Therefore, m, m, and m. Because the threshold of each comparator has changed, the time when each comparator changes its output has also changed. Calculate the new delay values for each comparator by using the following equation: t C ln (38) L ( ) PULLUP + MIO m where t µf(0 kω + 50 kω)ln 49.8 ms. Therefore, t ms, t ms, and t ms. To calculate t5 through t8, use Equation 3 to Equation 35: t 5 MIO C Lln m where t5 50 kω µf ln ms. Therefore, t ms, t7 5. ms, and t ms. THESHOLD AND TIMEOUT POGAMMABLE OLTAGE SUPEISO Figure 30 shows a circuit configuration for a programmable threshold and timeout circuit. The timeout, teset, defines the duration that the input voltage (IN) must be kept above the threshold voltage to toggle the ESET signal, preventing the device from operating when IN is not stable. If IN falls below the threshold voltage, the ESET signal toggles quickly. Data Sheet Figure 30. Programmable Threshold and Timeout Circuit Figure 3. Threshold and Timeout Programmable oltage Supervisor Timing Diagram During startup, the guarantees a low output state when CC is still below the ULO threshold, preventing the voltage supervisor from toggling. When IN reaches the threshold set by the resistor divider ( and ) and, changes from low to high and starts to charge the timeout capacitor (CT). If IN is kept above the threshold voltage and the voltage in CT reaches, OUTB toggles. If IN falls below the threshold voltage while CT is charging, the timeout capacitor quickly discharges, preventing OUTB from toggling while IN is not stable. In the condition that IN is tied to CC, the circuit operates when CC is more than the minimum operating voltage. The threshold voltage (TH) is configured by changing the resistor divider or. Calculate the threshold voltage by TH + (39) Timeout is adjusted by changing the values of the pull-up resistor or the timeout capacitor. To set the timeout value, determine the allowable current flowing through PULLUP and IPULLUP. When IPULLUP is known, calculate PULLUP and CT by the following formulas: PULLUP CC/IPULLUP (40) C T IN ESET IN TH PULLUP t ESET teset ln CC C T CC PULLUP OUTB t ESET ESET (4) ev. B Page 4 of 5

15 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.575) 3.80 (0.496) (0.44) 5.80 (0.83) 0.5 (0.0098) 0.0 (0.0039) COPLANAITY (0.0500) BSC 0.5 (0.00) 0.3 (0.0).75 (0.0689).35 (0.053) SEATING PLANE (0.0098) 0.7 (0.0067) 0.50 (0.097) 0.5 (0.0098).7 (0.0500) 0.40 (0.057) 45 COMPLIANT TO JEDEC STANDADS MS-0-AB CONTOLLING DIMENSIONS AE IN MILLIMETES; INCH DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF MILLIMETE EQUIALENTS FO EENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure 3. 4-Lead Standard Small Outline Package [SOIC_N] Narrow Body (-4) Dimensions shown in millimeters and (inches) A BSC 7 PIN Figure Lead Thin Shrink Small Outline Package [TSSOP] (U-4) Dimensions shown in millimeters ODEING GUIDE Model Temperature ange Package Description Package Option AZ 40 C to +5 C 4-Lead Standard Small Outline Package [SOIC_N] -4 AZ-L7 40 C to +5 C 4-Lead Standard Small Outline Package [SOIC_N] -4 AUZ 40 C to +5 C 4-Lead Thin Shrink Small Outline Package [TSSOP] U-4 AUZ-L7 40 C to +5 C 4-Lead Thin Shrink Small Outline Package [TSSOP] U-4 Z ohs Compliant Part BSC COPLANAITY MAX SEATING PLANE COMPLIANT TO JEDEC STANDADS MO-53-AB A 04 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08-0-0/4(B) ev. B Page 5 of 5