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1 AD-AI 130 SPERRY SYSTEMS NANAEGMNT HUNTSVILLE AL. F/. 1./2 DESIGN GUIDE. BUILT-IN-TEST IfITI AND BUILT-IN-TEST EQUIPME4T (I-ETCIU) UNCLASSIFIED SP ORSNI/RL-CR-A1-4 NL Ap, si OAA I llnlllllll2nl IIIIIIIIIIIhh Em m hhmmmmenl mhhhhhhhnh

2 C) TECHNICAL REPORT RL-CR-81-4 \ - DESIGN GUIDE BUILT-IN-TEST(BIT) and BUILT-IN-TEST EQUIPMENT (BITE) ARMY MISSILE SYSTEMS FINAL REPORT Sperry Crpratin Sperry Systems Management 1112 Church Street untsville, AL FOR Grund Equipment and Missile Structures Directrate US Army Missile Labratry }. "15 April 1981 F:?deftc~i7. Areen~al, AIl~~bamm Apprved fr public release; distributin unlimited. 3! FOFJ JUL 7S PREVIOUS EDITION IS 08OLETE

3 UNCLASSIFIED / 1,.,/ SECURITY CLASSIFICATION OF THIS PAGE (When Data Entred) REPORT DOCUMENTATION PAGE ' / READ ISTRUCTIONS BEFORE COMPLETING FORM 1. T12. OV TACCESSION N 3. RECIPIENT'S CATALOG NUMBER 4. TIT!-E (and SubtJ.....S. TYPE OF REPORT & PERIOD COVERED " Design Guide, Built-ln-Test (BIT) and " )i.:final Technical Reprt, Built-In-Test Equipment (BITE) fr Army Missile St Q R EPORT NUMBER ) SP _71 7. AUTHOR(&) 8. CONTRACT OR GRANT NUMBER(@) Sperry Crpratin LIAAK4O-79-D PERFORMING ORGANIZATION NAME AND ADDRESS 10. PRO.A4M ELEMENT. PROJECT, TASK ARW &WORK UNIT NUMBERS Sperry Crpratin Sperry Systems Management 1112 hurch Street Hint-yillp, Al irf 11 I1. CONTROLING OFFICE NAME AND ADDRESS 1 R.EPORT OATI, Army M-le Cmmand 41 Aprttpl-81, 6230 &3-IL16230SA21400 a" er - I At~n DR~I-Kr -'13. NUMBER OF PAGES Redstne Arsenal, AL MONITORING AGENCY NAME & ADDRESS(If different frm Cntrlliln Office) IS. SECURITY CLASS. (..lvfl-p r d " Cmmander Unclassified U. S. Army Missile Cmmand ATTN: DRSMI-RLD ISa. DECLASSIFICATION/DOWNGRADING Redstne Arsenal, AL SCHEDULE 1S. DISTRIBUTION STATEMENT (f this Reprt) - Apprved fr public release; distributin unlimited. 17. DISTRIBUTION STATEMENT (f the abetract entered In Blck 20, It different frme Reprt) IS. SUPPLEMENTARY NOTES 19. KEY WORDS (Cntinue n reverse side It necessary and Identify by blck number) Autmatic Test Equipment Built-In-Test (BIT) Built-In-Test Equipment (BITE) Design Guide 12. AITUACT" (Cmwta - wrin frt.. eamy md ideruttf by blck numbr) This reprt dcuments the first draft f a design guide and has been prepared as an aid t the prject manager, beginning with the cnceptual phase thrugh develpment, and as a guide t the system design engineer cncerned with the incrpratin f built-in-test (BIT) and built-in-test equipment (BITE) int the weapn system. It is nt the intent f this dcument t detail the "hw t" but rather t identify thse subject areas that need t be cnsidered - in determining the requirement fr BIT. DO,1473 EDITIN OF I NOV S1 IS OSOLETE 7 SEU U UNCLASSIFIED I O S ( en SECURITY CLASSIFICATION OF TIS PAGE (Whent Date Entered)

4 I I I.. April 17, 1981 SP DESIGN GUIDE BUILT-IN-TEST (BIT) AND BUILT-IN-TEST EQUIPMENT (BITE) FOR ARMY MISSILE SYSTEMS Prepared By SPERRY CORPORATI ON Sperry Systems Management-Huntsville Huntsville, Alabama Prepared Fr U.S. ARMY MISSILE COMMAND ARMY MISSILE LABORATORY, DRSMI-RLD. Redstne Arsenal, Alabama Fr Cntract N. DAAK40-79-D-O020 Delivery Order N. 0043

5 TABLE OF CONTENTS SECTION PAGE 1.0 INTRODUCTION Frewrd Purpse f Guide Definitin f BIT/BITE Applicatin f Guide Reference Dcuments BIT/BITE APPLICATION TO SYSTEM MAINTENANCE Maintenance Levels Testability Requirements BIT/BITE Versus ATE BIT Cmpatibility with ATE System Maintenance Cncept Requirements BIT as a Design Requirement BIT REQUIREMENT ANALYSIS The System Engineering Prcess System Operatin Maintenance Cncept Replaceable Units Test Requirements Fault Islatin External Test Equipment Interface BIT Perfrmance Requirements Cst Criteria Skill Levels and Manning Requirements Failure Mde and Effects Analysis BIT DESIGN REQUIREMENTS - GENERAL BIT Design Check List BIT Specificatins and General Requirements Purpse Active Versus Passive Functinal Level Tested On-Line Versus Off-Line Versus Interleaved Inductive Versus Deductive BIT Centralized Versus Distributed Testability Design Requirements Engineering Design Handbks Redundancy Fault Tlerances

6 TABLE OF CONTENTS (Cnt'd) SECTION PAGE 4.7 Busing and Signal Fan-Outs Sftware Versus Hardware Micrprcessr and BIT COMMUNICATION SYSTEMS Design Objectives Cmmunicatin Systems Special Cnsideratins Perfrmance Specificatins Envirnmental Requirements BIT Cnsideratin BIT Cverage BIT Self-Test Fail-Safe Cmmunicatin Systems Errr Detectin Specific Equipment Appraches Mdems Line Drivers and Receivers Encders and Decders Receivers Transmitter Antennas GUIDANCE AND CONTROL SYSTEMS System Operatin Inertial Guidance and Cntrl System Operatin Radar Tracking System Operatin Laser Tracking System Operatin Vide Tracking System Operatin Infrared Tracking System Operatin Guidance and Cntrl System Perfrmance Specificatin Inertial Guidance and Cntrl System Perfrmance Requirements Radar Tracking System Perfrmance Requirements Laser Tracking System Perfrmance Requirements... Vide Tracking System Perfrmance Requirements Infrared Guidance and Cntrl System Perfrmance Requirements

7 TABLE OF CONTENTS (Cnt'd) SECTION PAGE 6.3 Envirnmental Requirements BIT Cnsideratins BIT Cverage Self-Test Fail Safe Prelaunch Testing Pst Launch Testing POWER SYSTEMS Design Objectives System Operatin Special Cnsideratins Perfrmance Specificatins Y.5 BIT Cnsideratins Specific Equipment Appraches Pwer Surces Pwer Cnverters Pwer Regulatrs BASIC BIT/BITE DESIGN OUTLINE Intrductin BIT Detectability Level Specificatin BIT System Designs Base Test Pint (Sensr) Lcatin Fault Cde Matrix BIT System Evaluatin Design Example REFERENCES AND BIBLIOGRAPHY APPENDIX A ENGINEERING DESIGN HANDBOOKS DISTRIBUTION LIST

8 LIST OF ILLUSTRATIONS FIGURE PAGE I Tlerance Cne Typical Data Receiver Blck Diagram Typical BIT Self-Test Inputs Typical Data Transmitter Blck Diagram Inertial Guidance and Cntrl System Blck Diagram Radar Guidance and Cntrl System Blck Diagram 73 7 Typical Missile Pwer System Cnfiguratin General System Blck Diagram

9 SECTION 1.0 INTRODUCTION 1. I FOREWORD This design guide has been prepared as an aid t the prject manager, beginning with the cnceptual phase thrugh develpment, and as a guide t the system design engineer cncerned with the incrpratin f built-in-test (BIT) and built-in-test equipment (BITE) int the weapn system. It is nt the intent f this dcument t detail the "hw t" but rather t identify thse subject areas that need t be cnsidered in determining the requirement fr BIT. During the develpment f a weapn system, emphasis is usually placed n design f the basic system t meet perfrmance requirements with supprt requirements given a much lwer pririty in bth time and dllars. There is evidence that this apprach may well cntinue as the csts f weapn systems increase and dllars becme mre difficult t btain. Hwever, if life-cycle cst gals are t be met the supprt requirements must be addressed early enugh t influence the testability f the design. Maintainability cnsideratins such as perfrmance mnitring, BIT, BITE, n-line versus ff-line test, and accessibility must be addressed early in the initial prgram develpment phase. The cmplexity f tday's mdern weapn system dictates that the means fr testing be cnsidered and identified during the system cncept definitin, that the use f BIT be cnsidered as a means f meeting maintenance and peratinal gals, and that the testing addresses the ttal life-cycle csts. Bth the prject manager and the designer must make numerus decisins based n trade studies. These decisins effect bth hardware and philsphies f peratin. This guide is intended as an aid in making thse decisins. 5

10 Sme f the infrmatin prvided in the design guide is the distillatin f available infrmatin cntained in!avmatinst , Built-In-Test (BIT) Design Guide', and RADC-TR , A Design Guide fr Built-In-Test PURPOSE OF GUIDE is t: The fundamental purpse f the Built-In-Test Design Guide Imprve weapn system perfrmance in terms f equipqent readiness and availability. T imprve equipment testability. T accmplish this, the design guide will be a surce f reference t all levels f prject/prgram management, designers, and the varied engineering disciplines. As a guide it is intended t discuss ptins available rather than a hw-t-design handbk. The user will be acquainted with areas t be cnsidered in develping the rle BIT will have within the ttal weapn system. The verriding purpse f this guide, therefre, is t influence the reader t ensure the early cnsideratin f the requirement fr BIT t supprt the Army Missile Systems. 1.3 DEFINITION OF BIT/BITE MIL-STD-1309, Definitins f Terms fr Test, Measurement and Diagnstic Equipment, defines thse terms nrmally assciated with test, measurement and diagnstic equipment (TMDE). The definitin f BIT and BITE as stated in the standard are as fllws: Built-In-Test (BIT) A test apprach using BITE r self test hardware r sftware t test all r part f the unit under test. 6

11 Built-In-Test Equipment (BITE) Any device which is part f an equipment r system and is used fr the express purpse f testing the equipment r system. BITE is an identifiable unit f the equipment r system. Unless therwise stated, the definitins cntained in MIL-STD apply t this guide. Where needed r apprpriate, definitins will be cntained within this guide t minimize the need t refer t the referenced military standard. 1.4 APPLICATION OF GUIDE This BIT Design Guide is intended t prvide guidance t the weapn system planner, the weapn system prject r prgram manager, the system designer, the detailed equipment designer, the test engineer, the sftware prgrammer, and the test equipment designer. The user at the weapn system level wuld include planners, estimatrs, peratins research analyst, and specificatin writers. The guide can be applied during the pre-dsarc phase and the acquisitin phase as well as the detailed design phase by prviding guidelines f the ptins available. The specific use f the guide will be at the directin f the prgram manager. The guide is rganized t prvide the mre general infrmatin in Sectins 2.0 thrugh 4.0 and the Army Missile System details in Sectins 5.0 thrugh REFERENCE DOCUMENTS The fllwing lists thse dcuments, military standards, specificatins, etc. that are applicable t BIT and BITE. MIL-STD Military Standard Definitins f Terms fr Test, Measurement and Diagnstic Equipment 7

12 - I _ - MIL-STD Military Standard Test Prvisins fr Electrnic Systems and Assciated Equipment, Design Criteria Fr AR Maintenance f Supplies and Equipment Maintenance Cncepts 0 AR RDT&E f Materiel fr Extreme Climatic Cnditins MIL-STD Envirnmental Test Methds MIL-STD Lgistic Supprt Analysis PAM Lgistic Supprt Mdeling 0 TM Integrated Lgistic Supprt - Implementatin Guide fr DOD Systems and Equipments 0 TM Integrated Lgistic Supprt (ILS), Maintenance Engineering Analysis Data System (MEADS) 0 MIL-STD Maintainability Prgram Requirements (Fr Systems and Equipment) MIL-H Human Engineering Requirements fr Military Systems, Equipment and Facilities MIL-STD Cnfiguratin Cntrl - Engineering Changes, Deviatins and Waivers MIL-STD Definitin f Effectiveness Terms fr Reliability, Maintainability, Human Factrs and Safety 8

13 SECTION 2.0 BIT/BITE APPLICATION TO SYSTEM MAINTENANCE 2.1 MAINTENANCE LEVELS Within the Department f the Army, fur categries f maintenance are used. These categries are: Organizatinal Maintenance Direct Supprt Maintenance General Supprt Maintenance Dept Maintenance The categries are used t designate the scpe f maintenance t be perfrmed at the varius cmmand levels. these maintenance categries as fllws: Army regulatin AR defines a. Organizatinal Maintenance Organizatinal maintenance is the respnsibility f the unit cmmander in maintaining the peratinal readiness f equipment assigned r under his cntrl. This categry f maintenance includes preventive maintenance services and thse rganizatinal level repairs authrized in apprpriate technical publicatins. - b. Direct Supprt Maintenance Direct supprt maintenance nrmally is assigned t and,perfrmed by designated TOE r TDA maintenance activities 'in direct supprt f using rganizatins. The repair f 9

14 end-items r unserviceable assemblies is perfrmed in supprt f using rganizatins n a return-t-user basis. c. General Supprt Maintenance General supprt maintenance nrmally is assigned t and perfrmed by designated TOE r TDA maintenance units r activities in supprt f individual Army area supply peratins. This categry f maintenance cnstitutes the principal materiel verhaul means available t the Field Army Cmmander in maintaining his materiel assets. General supprt maintenance units and activities repair r verhaul materiel in accrdance with maintenance standards fr each item t btain ready fr issue cnditin based upn the supprted Army area supply requirements. When required, general supprt maintenance units may prvide supprt n a return-t-user basis fr equipment beynd the capacity f direct supprt units. d. Dept Maintenance Dept maintenance nrmally is assigned t and perfrmed by designated TDA industrial-type activities r cmmercial cntracts. This categry f maintenance assists in satisfying ttal Department f the Army materiel requirements by verhaul r rebuild f unserviceable assets requiring maintenance beynd the capability f general supprt maintenance units r activities. Dept maintenance may be perfrmed verseas during wartime as necessary and feasible t supprt military peratins in general r fr specific cmmdities. Perfrmance f crrective maintenance at any level f maintenance requires test equipment. The basic divisin in test equipment is either n-line test r ff-line test using either manually perated r autmatic 10

15 test equipment. An effective rganizatinal level n-line test capability using BIT prvides fr an imprved effectiveness at the ther maintenance levels when the ttal system test requirements cnsider all levels f maintenance. BIT at the system level can be a useful test when utilized at the," maintenance levels. 2.2 TESTABILITY REQUIREMENTS Testability has thse characteristics that permit verificatin f system perfrmance and the islatin f faulty cmpnents r subsystems t sme apprpriate pre-determined level. With tday's cmplex weapn systems, the need t design fr testability is recgnized as a basic mandatry requirement t be levied n all new equipment design in rder t meet the established maintenance gals. The incrpratin f testability int the equipment design is basic in satisfying a maintenance cncept that accunts fr the apprpriate supprt trade-ffs and levels f maintenance actins required fr a particular weapn system. Design fr testability must cnsider all levels f maintenance frm Organizatinal,Direct Supprt, General Supprt t Dept Level and address bth the hardware aspects f the system as well as the sftware. Testability at the Organizatinal Level can utilize n-line test with BIT and perfrmance mnitring systems r self-test functins. At the ther maintenance r repair levels, testability can be accmplished using ff-line test equipment including ATE as well as BITE that can functin independent f the ttal weapn system. A cmbinatin f appraches can be used t implement testability at the different maintenance levels. Early develpment f testability int the basic design and management attentin t this is essential t accmplishing the verall testability requirement. Of equal cncern is the need t establish a cmmn system test design that is nt nly cmprehensive but cmpatible 11

16 with the ATE selected fr the particular weapn system. Withut a cmmn testability apprach the cst and cmplexity may be prhibitive. The design fr testability shall be included as an integral part f the system engineering effrt. The requirements r specificatins fr testability must be established in the early stages f the system design. Prgram management shuld ensure that testability requirements are cntractually impsed n the equipment develper. Testability f prime equipment design is directly related t the degree f engineering emphasis placed n the design frm its inceptin and cntinued thrughut its develpment. The initial design must cntain prvisins fr testability and supprtability features which lend themselves t imprved peratinal readiness while implementing sund system engineering design principles. Functinal designs shuld prvide fr cmplimentary verlapping testability features, integrated with BIT and ATE cmpatible design features. In designing fr testability, the Failure Mde and Effects Analysis (FMEA) is a significant task. The FMEA affrds a check t determine that the system will nt be adversely affected by a malfunctin and will determine the level f repair. In additin, BIT requirements are specified and the failure mdes are defined. The failure Mde and Effects Analysis is further discussed in Paragraph 3.11 f Sectin 3.0, 2.3 BIT/BITE VERSUS ATE The Built-in-Test and Built-in-Test Equipment are nt in cmpetitin with Autmatic Test Equipment; rather, bth are essential elements in the system cncept. Such cnsideratins as state-f-theart, weight, cst, test time, and missin readiness requirements dictate the trades that must be made by the design engineer in determining the use f BIT/BITE and ATE as well as manual testing. The 12

17 design engineer must be respnsible in his design fr specifying the requirements fr bth BIT/BITE and ATE as part f a ttal weapn system cncept. During the initial equipment design, BIT can be incrprated with relative ease. Much f tday's electrnics cntain a micrprcessr r cmputer which further simplifies the incrpratin f readiness testing as well as diagnstics testing. If the equipment develpment has prgressed beynd a certain pint, it may be necessary t utilize external test equipment even thugh it may be mre cstly than having incrprated BIT during the initial equipment design. 2.4 BIT COMPATIBILITY WITH ATE Test requirements must be established at the weapn system level. The requirements fr testing must be analyzed at that level fr cherent tests between maintenance levels and t btain duplicate test results. Where BIT is used t further islate the failure in rder that the part be repaired, the BIT tlerance band must be wider than that fr ATE. T d therwise, the failure detected by BIT will nt be verified by the ATE. The never ending circle is bvius - with the unit returned t peratin after ATE verifying its prper peratin and BIT again rejecting it. Figure I depicts the widening tlerance band between levels f maintenance. Nte als the increase in the test equipment tlerance r accuracy maintenance levels. 2.5 SYSTEM MAINTENANCE CONCEPT REQUIREMENTS This guide is nt intended t define the maintenance requirements fr any given weapn system in either specific r generic terms. The frmulatin f the weapn system requirements are first defined by life cycle gals. system these gals culd be: Fr a system being replaced by a newer and updated 13

18 TOLERANCE BAND 04 + LEVELS OF MAINTENANCE \ / ORGANIZATI ONAL DIRECT SUPPORT SOLID AREA INDICATES / TEST EQUIPMENT ACCURACY AT THE DIFFERENT " MAINTENANCE LEVELS \ / \ / DEPOT NOMINAL DESIGN- VALUE Figure 1. Tlerance Cne 14

19 Less equipment Less maintenance at a specific maintenance level Fewer perating persnnel Fewer replaceable line items The maintenance cncept is based n meeting specific life cycle gals which are established at the system level. defined t achieve these gals culd be: The cncept Maximum use f perating persnnel at rganizatinal level fr maintenance with minimum skill required. Replacement at majr assembly level utilizing easily remvable plug-in assemblies. Minimize number f spares required at Organizatinal Level Maintenance. The abve are examples f system gals and maintenance cncepts that culd be established at the system level. In additin, the use f BIT and BITE culd be defined as a maintenance requirement t meet specific system gals. Bth prgram management and designers shuld cnsider the use f BIT/BITE as a means f effectively meeting established life cycle cst gals and the ensuing maintenance cncept. In many cases a system requirement which is established t meet a specific life cycle cst gal may nt be as realistic in real life as intended. Fr example, a maintenance system dictates the use f BIT/BITE and its design is based n a specific skill level being available and utilized fr the maintenance actins specified. Faced with a vlunteer Army, and pssibly supplemented with draftees during 15

20 a crisis, it is certainly pssible that the skill level required is either nt available r exists at the lw end f the scale in capability. It behves the designer, when incrprating BIT/BITE int the system design, t cnsider wrst pssible case and design accrdingly. Weapn sphisticatin remains ur edge ver the enemy, and the electrnics in tday's weapn system leads in bth state-f-theart and sphisticatin. The availability f skills needed t maintain nt nly tday's weapn systems but thse f tmrrw will cntinue t be a majr prblem. Weapn system designers may nt be able t design less sphisticated circuits but the design f BIT int these circuits must address, in-depth, the skill prblem facing tday's Army. 2.6 BIT AS A DESIGN REQUIREMENT Ideally, the requirement fr incrprating BIT int the basic design shuld be a cntract requirement impsed at the prgram level. Even mre basic wuld be that the ttal weapn system cncept recgnize the requirement fr BIT. This is nt t imply that unless there is a basic prgram requirement r cntractural authrity specifically fr BIT that it cannt be incrprated int the design. T satisfy ther system requirements may well dictate the use f BITtj-,The implementatin f BIT int the basic equipment design culd be dn, t meet availability requirements, maintainability gals, mean-time t repair gals, test requirements, etc. When BIT is specified as a system requirement, it is imprtant that it's incrpratin be an inherent design f the basic electrnic unit. The early intrductin f the test and maintenance requirements int the initial functinal design will result in an effective BIT design. This will require that the design engineers be equally qualified in the design fr testability as they are in the system design. Since this is nt always pssible r practical, it is necessary that the design engineers in their respective disciplines maintain a clsely crdinated effrt t 16

21 achieve the desired results. Incrprating BIT int the basic equipment design can be an effective means f increasing weapn system availability and readiness while reducing the level and cmplexity f maintenance. Other advantages include a reductin in supprting test equipment including ATE, reduced maintenance and ther lgistics supprt csts, and imprved fault islatin capabilities. Althugh BIT designed int the basic system will increase the frnt-end design csts, the trade-ff in availability and reduced maintenance csts will mre than ffset any disadvantages. The ttal life cycle cst f the system that incrprates a well engineered BIT design will be cnsiderably imprved ver the system withut BIT. 17 m m

22 SECTION 3.0 BIT REQUIREMENT ANALYSIS 3.1 THE SYSTEM ENGINEERING PROCESS The system engineering prcess is defined as "a lgical sequence f activities and decisins which transfrms an peratinal need int a descriptin f system perfrmance parameters and preferred system cnfiguratin. One f the tls used as part f the system engineering prcess is design-t-cst (DTC)/life-cycle cst (LCC) trade-ff analysis. This analysis assists in ptimizing system cnfiguratin and making thse tradeffs between system perfrmance parameters and cst in a way which minimizes the peratinal impact f these decisins. This prcess ptimizes system cnfiguratin frm the maintenance pint f view by establishing the mst favrable mdularity fr the specific maintenance cncept being evaluated. The definitin f replaceable and repairable units is part f this general prcess which affects bth design-fr-testability and built-in-test (BIT) design gals. Thus, bth n-line and ff-line autmatic testing requirements becme part f the trade-ffs assciated with develping the system cnfiguratin. Specific autmatic testing applicatins are evaluated as elements f the alternative cnfiguratins and maintenance cncepts used in the ptimizatin prcess."1 3 Beginning with the basic system cncept defined thrugh peratins research and technical feasibility studies and the initial system requirements having been set frth, the peratinal and functinal requirements are defined and translated int prgressively mre detailed peratin and supprt functinal sequences. Ultimately thrugh iteratin, a detailed set f perfrmance requirements will be cmpiled and used as a cmmn base in specifying design requirements, perfrmance specificatins, test requirements, lgistic supprt, etc. If the system is t be cntracted t industry, the requirements analysis wuld be cnducted t that level necessary fr preparatin f thse specificatins required fr cntract definitin. 18

23 As the prgram develps, cmplete analysis wuld be required including the Lgistics Supprt Analysis (LSA) which encmpasses all aspects f the system end-item design including perfrmance requirements fr the end-items and their cmpnents. Within the system engineering prcess the analyses, including LSA, is cnducted n an iterative basis thrughut the acquisitin cycle. The prgram size, cmplexity, and schedule will determine the number f iteratins and the depth required; The BIT requirements analysis is a prtin f a ttal systems apprach that includes a test requirements analysis supprted by an verall system level requirements analysis and the lgistics supprt analysis. There is n frmalized methdlgy fr cnducting a BIT Requirements Analysis such as there is fr the Lgistic Supprt Analysis (LSA) as defined in MIL-STD Hwever, there is a need fr this analysis fr the purpse f verifying that the requirements fr fault detectin and fault lcalizatin are satisfied. Items that must be lked at during analysis fr determining the requirements fr BIT are identified in this sectin. Much f the infrmatin needed is develped frm the LSA and ther frmalized analysis. 3.2 SYSTEM OPERATION The system designer must be respnsible fr the integrated design f all elements f a system if it is t meet the system peratinal requirements. Overemphasis r underemphasis n a particular aspect f a system can result in nt meeting the systems requirements fr bth its peratin and its supprtability. Frm a system standpint, the design f any element is interdependent with the design f any ther element in the system. The design f any system, subsystem, r end-item shuld nt prceed withut cnsideratin f the design f the ther systems, subsystems, and end-items. While specific peratinal requirements may vary between systems, it is necessary that all systems be integrated if a cherent design is t be realized. 19

24 As with ar integrated system design t meet specific peratinal requirements, the BIT requirements must be established at a system level and be integrated with all aspects f the system design, peratin, and supprt requirements. BIT can nt be an afterthught during the prime equipment design but must be an integral part f the system design and peratin. Overall test cnditins must reflect the true system perating cnditins if BIT is t effectively mnitr the readiness status f the weapn systen,. 3.3 MAINTENANCE CONCEPT The maintenance cncept prvides authrity and guidance t the maintenance planner. The cncept establishes the levels f maintenance, types f maintenance, and maintenance cnstraints. The cncept cvers pssible failures that may ccur at any pint during the s. eduled activities cvered by the peratins cncept. The maintenance cncept embraces the nn-success path and is primarily cncerned with the treatment f unscheduled events r failures s that the system can be returned t the success path. Scheduled maintenance such as lubricatin, clant replacement, and time sensitive parts replacement are als cvered by the maintenance cncept. The preliminary maintenance cncept prvides a functinal descriptin f the tasks required and designates the maintenance level at which each task will be perfrmed. The cncept is hardware riented and thus prtins are keyed t the functinal elements defined in the system functinal analysis. The cncept is the result f trade-ff studies and as such is an integral part f the system cncept ptimizatin. It is really the crnerstne f the structure against which all cst elements are determined and establishes the level at which line replaceable units (LRU's) will be repaired. The preliminary maintenance cncept is the key element f life cycle csting and determines the best way t maintain the prime weapn system. 20

25 The maintenance cncept is flexible in that it allws fr multiple cncept levels fr different systems, e.g., missile, fire cntrl, launcher, etc. During develpment f a maintenance cncept, a trade-ff analysis is a vital part if ptimum benefits are t be realized. As the prgram develps, these trade-ffs are prgressively refined. The maintenance cncept becmes a majr driving factr in determining the maintainability cnsideratins such as perfrmance mnitring using BIT/BITE, n-line versus ff-line test equipment, cmpnent interchangeability, mdularizatin, accessibility, criticality, standardizatin, and human engineering factrs. Including the requirement fr BIT in the initial develpment f a maintenance cncept is the mst cst effective methd f incrprating BIT int the basic design. The need t implement BIT int the weapn system as a means f achieving life cycle cst gals may nt be apparent if the lgistic supprt analysis, as specified in MIL-STD , is nt perfrmed. This guide has been prepared with the assumptin that this analysis, which is required fr all majr acquisitins, will be perfrmed. Failure t apply this standard and ther specified standards will affect the usefulness f this guide. 3.4 REPLACEABLE UNITS BIT can be designed t test a system t any functinal level required as determined thrugh the system analysis and reflected by the maintenance cncept. The level f testing required will vary between systems. As an example, the level f testing fr an inertial guidance system, packaged as ne majr assembly, culd be tested at the verall system level with the replaceable unit (RU) being the cmplete assembly. In a cmmunicatins system, the RU culd be a plug-in card assembly. BIT can be designed t detect and islate faults dwn t the chip level, if required, depending n the maintenance cncept. At the rganizatinal maintenance level the fault islated by BIT shuld be t ne easily replaceable mdule whether it be a system, subsystem, assembly, r card. During 21

26 develpment f the maintenance cncept the level f repair, strage f replacement units, and skill level required will be cnsidered in determining the replaceable units. While defining the BIT requirements fr the RU, it is imprtant that ther testing requirements be cnsidered. Cmpatibility with bth autmatic and manual test equipment shuld be a mandatry requirement fr all electrnic and electrical equipment design. Functinal and diagnstic test pints shuld be prvided t allw testing at the RU's cnnectr. When test requirements need additinal circuit data fr fault islatin, and test pints thrugh the cnnectr are nt available, circuit prbe pints shuld be prvided. 3.5 TEST REQUIREMENTS The test requirements dcument (TRD) (Ref MIL-STD-1519) is the fundatin fr the identificatin f the test prgram, prcedures, and equipment. The TRD is the result f the test requirements analysis, which is part f the lgistic supprt analysis, and shuld be accmplished early in the prgram t avid the time and cst penalties incurred by delaying until the equipment is designed. The key t successful testing is the develpment f a frmal analysis resulting in cnsistent test prcedures and requirements within well defined bundaries. Thrugh the incrpratin f BIT, t satisfy test requirements tgether with requirements fr bth autmatic and manual testing that are cmpatible with BIT, the equipment reliability and availability are imprved. In additin, mre accurate and faster fault islatin can be accmplished thereby ensuring that the necessary perfrmance test requirements are met. In view f the benefits that can result frm bth BIT and ATE, it is even mre imprtant that accurate and well-rganized test requirements be prvided. As with any analysis, the utput is a reflectin f the quality f the input data. The effrt expended n btaining and/r develping quality input data will be well wrth it in terms f an imprved utput. 22

27 3.6 FAULT ISOLATION The level f BIT required t lcate the malfunctin is directly related t the mean-time-t-repair (MTTR) requirement fr the system. The ttal repair time at the rganizatinal maintenance level is the sum f the fllwing basic steps: Lcatin Islatin Remval Replacement Checkut The abve five steps assume that the LRU (line replaceable unit) is the majr assembly level. If plug-in units within an assembly are the RU then tw additinal steps f disass,-mbly and assembly are required. These seven steps are: Lcatin Islatin Disassembly Remval Replacement Reassembly Checkut 23

28 The use f BIT at the rganizatinal maintenance level can virtually eliminate the lcatin time and the islatin time. The design f BIT int the weapn system design shuld be such that the fault can be islated t ne specific majr assembly that is easily remved and replaced. If further islatin f the fault is required thrugh the use f additinal test equipment, either autmatic r manual, then that maintenance shuld be limited t general supprt r dept level maintenance. System readiness and availability are f prime imprtance. It is necessary therefre that in maintaining peratinal readiness, the BIT be designed t fault islate t ne majr cmpnent and that remval and replacement f that ne cmpnent can be accmplished within a minimum f time. With the use f BIT the checkut time, the last step in returning a system t a readiness state, can be significantly reduced especially when the fault was initially detected by BIT. The checkut step culd include alignment, calibratin r ther adjustments. At the rganizatinal level, these activities shuld be avided whenever pssible. Nt nly culd these tasks require a higher skill level than needed fr the system peratin but the time required culd exceed that allcated fr returning the system t a readiness cnditin. It is imprtant t remind urselves that the mst sphisticated weapn system is useless if it is nt n-line. When faults d ccur, the time required t crrect shuld be the very minimum within cst cnsideratins. 3.7 EXTERNAL TEST EQUIPMENT INTERFACE The design f the basic system must cnsider the interface requirements fr external test equipment, be it ATE r manual. Depending upn the size and cmplexity f the prgram, interface cntrl drawings and dcumentatin may be necessary. The interface cntrl drawing wuld depict the interrelatinship f the end-item physical and functinal design characteristics. 24

29 In additin t the interface requirements between the prime equipment and external test equipment, the interface between the BIT design and external testing must be cnsidered. The infrmatin available frm BIT culd be data that is required t be used fr external testing, either autmatic r manual. Frm past experience, interface prblems can be bth cstly and time cnsuming during develpment and testing. Prblems can be minimized thrugh early definitin f the external ATE and the specific interfaces with BIT. The extensive use f cmputers and micrprcessrs in tday's weapn systems can reduce the interface prblem between BIT and ATE t a sftware prgramming prblem prviding the infrmatin available frm BIT and any additinal infrmatin required by ATE is available at the cnnectr interface. 3.8 BIT PERFORMANCE REQUIREMENTS The prcess which leads t the definitin f system perfrmance requirements starts with the translatin f system missin requirements int basic functinal sequences f peratins t describe hw the missin will be accmplished. The determinatin f ttal system requirements begins with identifying and analyzing the functins required t perate, cntrl, maintain, supprt, prduce, assemble, integrate, test, and deply the prime missin equipment as a basis fr determining the perfrmance and design requirements fr supprting equipment, facilities, prcedures, skills, and lgistics supprt. The analysis being an interative prcess will prgress thrugh mre detailed requirements until cmplete perfrmance requirements are identified. Hw each system level functin is t be accmplished must be brken dwn int bth qualitative and quantitative perfrmance requirements t be levied upn each system element. System r subsystem perfrmance standards are the basis fr verifying, during the system test and evaluatin prgram, that the system design meets the stated perfrmance requirements. 25

30 II * * I *..... Based n the maintenance cncept and thrugh analysis, quantitative requirements are defined fr BIT (and/r BITE). The fllwing are examples f typical BIT perfrmance requirements, sme f which are taken frm existing Army Missile Systems: Fault Detectin Nt less than 98 percent detected by the peratr using BIT. r Given a faulty system, the prbability f a "failed" indicatin shall be nt less than: 90 percent fr missile with "X" seekers 80 percent fr missile with "Y" seekers 95 percent fr missile less seeker 90 percent fr launcher electrnics 95 percent fr "Z" system electrnics and/r Given a faulty system, the prbability f a "gd" indicatin shall be nt mre than: 10 percent missile with "X" seekers 20 percent fr missile with "Y" seekers 5 percent fr missile less seeker 10 percent fr launcher electrnics 5 percent fr "Z" system electrnics r 26

31 Given a gd system, the prbability f a "gd" indicatin shall be nt less than 98 percent. r Given a gd system, the prbability f a "failed" indicatin shall be nt mre than 2 percent. r BIT shall detect failures (and ut f tlerance) which represent at least 90 percent f the system (r subsystem) prbable failures. Fault Lcalizatin Nt less than 98 percent lcalized by peratr using BIT. Availability The BIT design shall have an peratinal availability f nt less than 95 percent when perating in the system envirnment. r The maintenance man-hurs fr bth preventive and crrective per equipment perating hur rati f r less. 0 Repair Time The time t repair a system with BIT at the Organizatinal level is anther way t state the BIT availability. 27

32 MTBF The MTBF f the BIT design shall be at least a factr f tw in imprvement ver the prime equipment design. r The MTBF f the BIT shall be nt less than 500 perating hurs. Reliability Reliability in an expressin f MTBF f the system. 0 False Alarm Rate The false alarm rate f BIT shall nt exceed 3 percent f the fault detected. Maintainability The MTTR will be "X" minutes frm fault detectin. The abve quantitative BIT perfrmance requirements are intended as examples nly. Each Army Missile System Prgram must develp their specific perfrmance requirements tailred t that system. 3.9 COST CRITERIA Life Cycle Cst (LCC) analysis is a basic tl used in the evaluatin f lgistics resurce requirements and is used in cnjunctin with such items as system effectiveness and technical perfrmance in determining cst effectiveness. The LCC serves t define areas f high supprt csts as a result f design decisins, defines the impact f peratinal requirements r supprt plicy alternatives, and prvides a means fr evaluating built-in test versus external supprt equipment 28

33 be it ATE r manually perated test equipment. Whenever pssible, cst factrs shuld be based upn pertinent data prvided by the prcuring activity frm surveillance f peratinal systems. It is essential that the methd f supprting the weapn system be carefully cnsidered because f the significant effect f supprt n the ttal prgram life-cycle cst. It is imprtant that bth BIT and external test equipment be lked at in rder that the ptimum apprach r mix be identified and the cst trade-ffs be perfrmed. In perfrming trade-ffs f candidate designs t determine the extent f BIT and/r external test equipment t be used, the apprpriate trade-ff elements must be defined and weighed, and the perfrmance and/r cst parameters they effect have t be calculated. As a general rule, the incrpratin f BIT int the system as part f the basic prime system design will imprve system availability and reduce the ttal life-cycle cst SKILL LEVELS AND MANNING REQUIREMENTS The Lgistic Supprt Analysis (LSA) identifies the persnnel, training, and skills required fr supprt f the weapn system and supprt equipment. Crdinatin shuld be maintained with the design activity s the effect f design changes can be reflected in the training plan. The analysis prvides identificatin f the requirements fr trained peratrs and supprt persnnel fr all levels f maintenance. and training data resulting frm the LSA include number f persnnel Persnnel required, the skill levels, skill specialties training requirements, and training material required. The incrpratin f BIT int the basic design fr prviding a system readiness check and fr fault lcatin and islatin shuld result in a lwer persnnel skill level required at the Organizatinal maintenance level. The design f BIT int the basic equipment shuld address the skill levels and manning requirements t minimize bth f thse requirements. 29

34 3.11 FAILURE MODE AND EFFECTS ANALYSIS An analysis f significant imprtance in ptimizing a design fr testability is the Failure Mde and Effects Analysis (FMEA). The FMEA assures that malfunctins will nt adversely affect the system. It prvides a check t determine the level f repair and the BIT requirements fr that system. In additin, the specific functinal failure mdes and their effects are defined. The FMEA is a cntinuing effrt, affecting system and equipment design and the lgistics supprt system. The first requirement in the perfrmance f an FMEA is t establish the basic perfrmance, safety, maintenance, and inspectin criteria and t identify the elements f the functins f a system, subsystem, r cmpnent t the apprpriate level in relatin with the established criteria. This is accmplished thrugh the establishment f detailed equipment and functinal blck diagrams f the system and its peratin. Fr each f the identifiable element r functins, the failure mdes and their effects will be determined. The effects will be cnsidered in three categries as fllws: The effect f the failure by itself withut cnsideratin f ther realted cmpnents r functins. The effects f a failure in cmbinatin with ther elements f the system r ther functins s as t determine if there is a cmpunding r accumulatin f results. The effect f the failure n the ttal system r subsystem peratin. It is this identificatin f the failure effects in an rderly and lgical manner that prvides the ability t evaluate the systems peratin in ters f testability, preventive maintenance, peridic inspectin, BIT requirement, and reliability. 30

35 The initial failure analysis is perfrmed n a preliminary design and examines functinal failures at the subsystem level. The critical elements identified are assigned pririty fr further examinatin t identify assemblies and subassemblies that may fail with missin critical effects. These items are investigated in detail as t failure mdes and failure rates f cmpnents and parts. Prmpt attentin is thus directed t design imprvements in the sensitive and mst respnsive areas. These critical areas als becme candidates fr incrpratin f BIT. In general, the fllwing tasks and requirements are directly related t r dependent upn the results f the FMEA. BIT requirements Test plans and prcedures Design reviews Math mdel reliability predictin and allcatin Reliability demnstratin tests Preventive maintenance and maintainability Lgistic Supprt Analysis Hazard and safety analysis The FMEA is a valuable tl fr assessing the need and the adequacy f BIT. The initial FMEA based n the preliminary design will prvide the ptimum tl fr the identificatin f BIT requirements. is recgnized that prgram management may delay and/r eliminate the requirement fr FMEA due t cst cnstraints. It shuld be recgnized, It 31

36 hwever, that the lnger this analysis is delayed the mre difficult it becmes t influence the basic design up t a pint where it is n lnger cst effective t d s. It may be expedient t delay r even eliminate the R4EA requirement, but t d s is t ignre the ttal life-cycle gals. It shuld be nted again that failure t apply the analysis tls discussed in this sectin will affect the usefulne s f this design guide. 32

37 SECTION 4.0 BIT DESIGNI REQUIREMENTS - GENERAL 4.1 BIT DESIGN CHECK LIST Self-test prvisins shall be an inherent design f the weapn system electrnic equipment and prvide fr perfrmance evaluatin and fault islatin. The use f such BIT designs shall nt jepardize the peratin r perfrmance f the specific electrnic equipment. The intentin f this prvisin is as stated in MIL-STD-415: "BIT prvisins shall be added t an item fr the sle purpse f testing the item. They shall be simple in design and peratin, accurate, easily maintained, preferably mre reliable than the circuit prviding perfrmance, and shall nt degrade the perfrmance f the item in which they are incrprated. BIT prvisin shall prvide ptimum cnvenience f use and peratin. The design f cntrls and readut devices shall be such that they can be easily used and interpreted by lw skill persnnel." The designer incrprating BIT int the basic equipment design needs t cnsider sme basic BIT requirements, many f which are needed as inputs t the system and lgistic requirements analysis. As a guide t the BIT designer, the fllwing checklist is prvided'. a. The number f test pints which shuld be mnitred n a semicntinuus basis b. The number f test pints which shuld be mnitred daily, weekly, and mnthly 33

38 c. The number f test pints which shuld be mnitred n a demand-basis nly d. The number f test pints which are required t islate failures r indicate trends at the black-bx, mdule r subassembly, printed-circuit bard, part, r circuit levels e. The number f test pints which can be cnverted t dc vltage (0 t +10 Vdc) using resistive dividers nly and the degree f accuracy required f. The number f test pints which can be cnverted t dc vltage (0 t +10 Vdc) using active resistance netwrks and the degree f accuracy required g. The number f test pints requiring ac-t-dc ccnversin and the degree f accuracy required h. The number f test pints requiring AF-t-dc cnversin and the degree f accuracy required i. The number f test pints requiring RF-t-dc cnversin, the frequencies, and the degree f accuracy required j. The number f test pints requiring RF pwer-t-dc vltage cnversin, the ranges, frequencies, and the degree f accuracy required k. The number f test pints requiring VSWR-t-dc vltage cnversin, the maximum VSWR expected at what frequencies, and the degree f accuracy required 34

39 I. The number and types f ther mnitr cnverters which are required m. The number f test pints which require sme kind f stimulus generatrs n. The number f test pints which can be cntact clsures t grund, the required current capacities, and the vltages t be switched. The number f test pints which can be cntact clsures t available pwer, the required pwer, current capacity, and vltages p. The number f test pints requiring signal generatrs, the frequencies, the amplitudes, the degree f wave purity, impedances, and the degree f accuracy required q. The number f test pints requiring pulse generatrs, the amplitudes, lad impedances, pulse widths, rise times, fall times, tlerable drp, plar~ties, and pulse trains r. The number f test pints requiring special stimulus generatrs and their types s. The cst f each cnverter listed in items e. thrugh 1. t. The cst f each stimulus generatr in items m. thrugh r. u. The MTBF f the system as designed v. The MTTR withut BIT w. The mean-dwn-time (MDT) withut BIT 35

40 x. The MTTR with BIT y. The MDT with BIT z. The MTBF fr BIT aa. The verall system MTBF with BIT bb. The MTTR BIT shall be lw, i.e., 10 minutes maximum cc. The amunt f spare memry available fr sftware testing dd. The amunt and kind f intercnnecting hardware required ee. The cupling and islatin prblems which are anticipated fr each test pint ff. The kind and level f nise which can be tlerated at each test pint gg. The cntributin t ttal pwer cnsumptin due t BIT hh. The impact n equipment mdularity as a result f additinal hardware functins prvided fr BIT ii. The impact f additinal BIT circuitry n equipment temperature prfiles, cling requirements, and ther envirnmental factrs ij. The pprtunity t substitute micrprcessr system elements fr hardwired BIT cntrl and mnitring functins - Sme f these items are taken frm the BIT Design Guide prepared fr the Chief f 4aval aterial, NAV1IATIINST

41 kk. Passive BIT circuits mnitr key pints f a system withut the need fr signal injectin. The greater percentage may mnitr dc vltages r ac signals that are t be present. The system need nt be interrupted fr BIT evaluatin purpses. Active BIT systems inject a signal at a given pint (such as the input f a radar receiver), and measure the respnse at an utput prt. In mst applicatins the system wuld nt be in an peratinal mde during these tests. Whichever apprach is used depends upn the scenaris f pssible applicatins and whether such interruptins can be tlerated. The chice f methds must be determined frm these aspects at an early time f the system design phase: Shuld I interrupt, r is it better t use passive methds? 11. When designing BIT circuitry, bi-stable multivibratrs r flip-flps are ften used. During a pwer-up phase the lgic states f these elements are randm, unless special precautins are taken. Temprarily false data "bits" may trigger a malfunctin alert during this perid. A reset functin must be initiated. This can be avided by either time-delay r builtin reset circuits. It is als imprtant t avid the autmatic premature shutdwn f a circuit because a vital, related sectin was nt yet peratinal at a given instant during turn-n. Frce-fail circuits are ften activated by a BIT failure in anther sectin. BIT failure activatin must be retarded and the time delay specified fr each such related assembly during the early design phase f the system. Interchangeability requirements demand such cnsideratins. 37

42 mm. The BIT shall have high reliability circuits n the rder f 100,000 hurs MTBF. nn. The BIT architecture and test algrithms shall be standardized thrughut the weapn system equipment.. The BIT indicatrs shall be readily visible t the peratr. pp. The BIT circuitry shall be resident n the same functinal mdule in which it is mnitring whenever pssible. qq. The incrpratin f BIT shall make maximum use f existing micrprcessrs and/r cmputers vithin the system. rr. The incrpratin f BIT int the weapn system shall have n effect n the functinal circuitry, shall nt effect the safety f peratin, and shall fail passively, i.e., be fail safe. ss. Calibratin r alignment f BITE circuitry shall be limited. The BIT perfrmance requirements in Paragraph 3.8 cntain additinal items t be cnsidered by the equipment designer when incrprating BIT int the weapn system. 4.2 BIT SPECIFICATIONS AND GENERAL REQUIREMENTS The design f BIT is a cmplicated prcess. BIT includes every cncept used t detect and islate a fault and prvides a means fr checking the system readiness withut the use f external test equipment. The cmplexity f BIT ranges frm the indicatr lamp that lights when an equipment pwer switch is turned n t the use f a resident cmputer fr the generatin f test signals and evaluatin f the system respnse. BIT can be cntinuusly perated, interleaved with ther peratins r initiated n 38

43 cmmand. It includes hardware sensrs, sftware, and firmware. Its particular mechanizatin and utilizatin in a system are f curse determined by the designer and the system requirements resulting frm analysis. The careless design f BIT can result in a near useless system ignred by the peratr and maintenance persnnel. BIT can be categrized in several different ways such as: Purpse, i.e., detectin, islatin crrectin and/r predictin Active versus passive Functinal levels tested On-line versus ff-line versus interleaved Inductive versus deductive Centralized versus decentralized The result is a matrix f pssible BIT classes with each class having its use t meet a designers particular need. In mst cases a cmbinatin f classes will be used as the mst cst effective means f meeting specific requirements. A brief discussin f these six categries f BIT fllws Purpse There are tw main purpses fr BIT. One is t detect a failure which als serves the functin f islatin t a specified, predetermined level, as an aid t maintenance. The ther functin f BIT is t crrect a failure. This can be accmplished by a failure triggering thrugh BIT the transfer frm a failed mdule t a redundant mdule. Failure predictin can als be perfrmed by BIT in such areas as a vibratin 39

44 level being an indicatin f an imminent failure Active Versus Passive The interrgatin f a mdule by a test signal and then evaluates the respnse is an example f active BIT. Passive BIT wuld mnitr system perfrmance withut generating a test signal Functinal Level Tested BIT can be designed t test at the system level, subsystem mdule level, printed circuit bard, r even the part level. The level depends n bth the maintenance cncept and the resulting system level analysis and the lgistic supprt analysis. The maintenance requirements and the assciated life-cycle cst trade studies will determine the apprpriate functinal level r levels fr BIT On-Line Versus Off-Line Versus Interleaved On-line passive BIT is in peratin while the system is perating. Off-line active BIT will check the systems peratin while the system is nt perfrming its missin. It is als pssible that the active BIT is used when the system is perating but a particular mdule is nt perating; in fact an entire system can be tested withut interrupting peratin. This is referred t as interleaving BIT. Interleaving can be an effective means fr maintaining system cnfidence withut disrupting a missin fr specific testing. BIT can be used t indicate failures, be used t mnitr the well-being f the system, and assist in lcating a malfunctin. The designer must decide the cmbinatin f BIT required fr the specific system based n analysis and systems cncept Inductive Versus Deductive BIT Inductive BIT cncludes that if a specific set f measured functins are within their stated tlerance limits then a single unmeasured functin must als be within its stated tlerance limit. 40

45 Deductive BIT assumes that if a certain functin is within a stated tlerance limit then all the variables invlved in generating that functin must be within their stated tlerance limit Centralized Versus Distributed Centralized BIT wuld be individual systems tgether with a central cmputer r micrprcessr which cntrls the system and can prvide interleave tests. Usually less hardware is required in the centralized BIT. If each BIT circuit has but ne functin, such as test ne mdule, it is distributed. Distributed BIT has the advantage that a system can be taken ff-line and cntinue t use BIT fr further failure diagnsis. The mst imprtant f all "General Design Requirements" is that BIT CANNOT be cnsidered an afterthught. As discussed in Sectin 3.0, BIT must be an integral part f the design prcess and be cnsidered in the cncept definitin and included as part f the frmal (and infrmal) analysis. Imprtant general design cnsideratins and items that shuld be cnsidered fr inclusin in the specificatins fr BIT are the fllwing: Availability Requirements Reliability Requirements MTTR Fault Definitin Detectability Level 41

46 Fault-Islatin Level False-Alarm Rate Self-Test Requirements Extent f Operatr Participatin Sftware Cnstrains (Memry Capacity) Design-Grwth Limits Design Cst Gals Fail-Safe Prvisins Fault Indicatrs Special BIT Features Calibratin Requirements The reliability f BIT shuld exceed that f the hardware being tested. If this is nt the case, the prbability f failure f the BIT may be almst as great as the prbability f failure f the unit under test. A failure in the BIT circuit shuld nt affect the weapn system perfrmance. Whenever feasible, the BIT input and utput shuld be sufficiently islated frm the nrmal channels s that any failure in the BIT will nt cause a system failure. The use f high-reliability and burned-in parts as well as integrated circuits is recmmended. BIT shuld be kept as simple as pssible but be as effective as required t meet peratinal needs. The type circuitry use fr BIT shuld be, if feasible, the same type used in the basic system. 42

47 The BIT prtective circuitry shuld be designed t be fail-safe, i.e., fail passively. As an example, if a wire breaks r a cnnectr is left discnnected, the fault will be detected and the system prtected. All pssible input-stimuli cmbinatins, when ecnmical, shuld be cnsidered t eliminate the pssibility f a gd cnditin fraudulently indicating a fault. Self-test f BIT is an imprtant cnsideratin since an undetected BIT failure whi!h incrrectly indicates a system failure will increase maintenance time by directing the maintenance persnnel t the wrng area. 4.3 TESTABILITY DESIGN REQUIREMENTS Design fr testability (DFT) is a basic bjective t be levieg as a requirement by the Army n all future missile systems. Imprved peratinal readiness and reduced perating and supprt csts can nt be realized unless DFT beciit.s a cntract requirement similiar t system perfrmance. It is difficult t specify reasnable and cst-effective testability requirements that can be cntractually stated and enfrced. The fllwing design guides are generic in nature and represent the typical standards that exist thrughut industry. It is suggested that they serve as a basis fr defining testability design requirements fr bth the designer and the prcurement activity. Mdule Layut Prvide sufficient space between adjacent cmpnents and place cmpnents in a standard rientatin Edge Cnnectr Utilize a standard cnnectr with keying capability Use a standird lcatin fr cmmn functin, e.g., pwer, grund, and analg signals 43

48 Prvide adequate edge cnnectr pins fr the cntrl and visibility f the circuits Ensure that adjacent cnnectr pins cannt shrt and cause damage t the circuitry n the mdules Partitining 0 Design mdules int easily testable functinal partitins - d nt divide functins between tw r mre mdules Islate analg and digital circuitry 0 Subdivide large lgic circuits with lw visibility int partitins Test Pints Prvide sufficient test pints fr fault diagnsis/visibility Types - DIP pins, external cnnectnr, stand-ffs, and pads Als cnsider space fr IC lcatins, built-in multiplexer fr selectin f test pints, and shift registers t shift ut test pint data Nise Prpagatin Prvide adequate decupling f vltages at each IC r grup f IC's and at mdule cnnectr Supply Vltages 0 Minimize the number f vltage supplies per mdule 0 If mre than ne vltage supply, ensure that a randm turn n/ff sequence will nt damage mdule circuitry 44

49 . I I l~i I.. Lgic Families Minimize lgic families if pssible; if nt, chse cmpnents that are cmpatible bth electrically and mechanically Input/Output Interface Ensure that an additinal 60 pf lad will nt adversely affect perfrmance f mdules during testing Prvide minimal lad n bard input signals and maximum drive capability n utput signals 0 Buffer clck and reset lines alng with flip-flp and latched utputs Initializatin Prvide reset (set) lines fr efficient external initializatin f memry elements Avid self-initializing cunter 0 Avid the cnnectin f set and clear inputs t the same signal elements Lgic Race and Timing Design fr wrst-case timing 0 Avid designs whse functinal peratin will invlve lgic race and timing 45

50 Free-Running Clcks Allw fr the disablement f internal free-running clcks and the insertin f an external test clck signal Feedback Lps 0 Segment digital feedback lps n mdules such that during testing the lps can be pened and testing perfrmed n bth the segmented and clsed lp Bused Lgic Allw fr visibility and cntrl f bus Avid use f wire AND's and OR's in the circuit design Adjusting Elements Avid the use f ptentimeters and adjustable capacitrs LSI Prvide fr the cntrl and visibility f all functins assciated with micrprcessrs and memry elements Cnsider the utilizatin f a scket fr cmplex LSI's Prvide a means fr the cntrl f the bard activity rate 4.4 ENGINEERING DESIGN HANDBOOKS The Engineering Design Handbk Series f the Army are a crdinated series f handbks cntaining basic infrmatin and fundamental data useful in the design and develpment f Army materiel and systems. The handbks are authritative reference bks f practical infrmatin and quantitative factrs helpful in the design and develpment f Army materiel s that it will meet the tactical and the technical needs f the Army. 46

51 Appendix A cntains a list f these handbks as f May 1979, with bth the AMC Pamphlet number and the Defense Dcumentatin Center* and Natinal Technical Infrmatin Service (DDC/NTIS) dcument number. 4.5 REDUNDANCY Design fr redundancy must cnsider the criticality f the functin t a particular missin r peratin as well as the impact n maintainability, testability, and prgram life-cycle csts. The existing technlgy f large-scale integratin (LSI) circuits allws fr easy incrpratin f redundancy as well as BIT int a new design withut an appreciable impact n weight, size, and even cmpnent cst. Prir t the integrated circuits, cst, weight, and size were a deterrent t incrprating redundancy. In existing equipment, including redundancy wuld in all prbability prve t be very cstly. A trade-ff analysis must be perfrmed t establish the redundancy fr a particular electrnic design. The criteria which will impact the trade-ff decisin t incrprate redundancy at either the system level r the circuit r functin level are: Reliability requirements Missin essential functins and availability criteria Minimum level f allwable degraded mdes Backup requirements, either manual r autmatic Maintainability requirements Testability limitatins DOC is nw called the Defense Technical Infrmatin Center (DTIC) 47

52 Human factrs including available skill level f persnnel fr maintenance, in particular at the Organizatinal level 0 Weight, size, and cst 0 Impact n circuit functins including electrmagnetic interference Lgistic supprt including spare requirements Incrpratin f redundancy at the system level, the functin level, the unit level r the cmpnent level shuld nt be an arbitrary decisin by a designer but shuld be subjected t a deliberate and frmal review, crdinated with and part f an verall systems and lgistic supprt analysis. Redundant circuits may be active r passive. BIT shuld be utilized t prvide the fllwing: In either case, Prvide a perfrmance evaluatin f bth circuits. Prvide infrmatin t the system peratr that ne f the redundant circuits (r systems, cmpnents, etc.) has failed. This infrmatin shuld be prvided even if there is an autmatic switch-ver frm ne circuit t the ther. Prvide infrmatin t the peratr if there is a deteriratin in ne f the circuits. In the event cmputer sftware is used t prvide vting functins and t indicate autmatic transfer between redundant circuits, the data prcessing design must take int accunt the expanded memry requirements. 48

53 4.6 FAULT TOLERANCES A circuit analysis shuld be cnducted t determine the acceptable tlerance levels fr each electrnic unit. Use f a nminal fault tlerance parameter measurement fr all levels f testing will nt be acceptable. It will be necessary t take int accunt the tlerance limits f each functinal chain, thereby prviding fr the allwable cumulative variatins at the varius levels f maintenance and repair. Figure 1 represents this tlerance cne r trfe. The functinal tlerance limits f each test level shall be assigned early in the design phase and reviewed in cnjunctin with the level f repair identified by bth the LSA and the maintenance cncept. 4.7 BUSING AND SIGNAL FAN-OUTS Busing and signal fan-uts may be necessary in circuit designs t allw fr multiple surce/sync signal cnditining and lgic transfers. Busing techniques are cmmnly used in interface cmmunicatins between subsystems and internal t the electrnic units fr such things as pwer, grunding, enabling circuits, sync r clck signals and the like. Testability and ambiguity cnsideratins are largely influenced by this design feature, and special attentin needs t be given in the incrpratin f BIT s that unambiguus islatin f the fault can be determined. Failures frm circuits using cmmn busing can cause a large grup f fault indicatins invlving many systems, subsystems, and units. The BIT designer must be especially aware f this situatin and design BIT s that the actual fault is islated t the specific unit. The BIT capability fr circuits such as pwer surces, clck circuits, sync signals, etc., shuld be designed s that the specific signal can be mnitred independent f the functinal circuit. This can be accmplished, thrugh autmatic initiatin by BIT, t islate the signal at its surce. 49

54 Often the failed cnditin can be islated in a pwer-ff state thrugh resistance measurements. This type testing fr fault islatin lends itself t the ff-line testing using ATE r manual test equipment. The designer f BIT must cnsider the need fr external testing and be cmpatible with it. Failures resulting in laded, shrted, r pen cnditins present a different situatin where testing at the signal surce will nt islate the failure shuld the fault be dwnstream frm the surce. Again the designer incrprating BIT must cnsider this situatin. Assuming a centralized cmputer, sftware prgramming can readily islate the fault. 4.8 SOFTWARE VERSUS HARDWARE Tday's technlgy favrs the cmputer r micrprcessr and sftware apprach ver that f hardware especially as related t traditinal analg circuitry. Many f the current hardware functins have been reduced t sftware algrithms and transfer functins. Sftware plays an imprtant rle in testability designs and can ffset the added prductin cst f a hardware apprach. While the sftware up-frnt csts may be high, it is flprf nce develped, and ver the life f the prgram can be cst effective resulting in a lwer-life cycle cst. Once the decisin has been made that BIT will be included in the weapn system and the level f BIT defined, it must then be determined t what extent hardware and/r sftware will be used in implementing the BIT system. Hardware in the frm f hardwire has its place in BIT. An example wuld be a pwer-n indicatr light. Hardwire lgic circuits are standard in many circuits, and even with a mre sphisticated sftware apprach, the use f hardwire in a BIT system has its applicatin. A drawback using a straight hardware apprach is that fault islatin requires that the peratr 50

55 (Organizatinal level) r maintenance persnnel be prvided prcedures ana trubleshting aids as BIT in this situatin will nt necessarily fault-islate t a replaceable unit. Sftware n the ther hand ffers many advantages. Sftware, f curse, implies using a cmputer r micrprcessr. Many weapn systems cntain a cmputer fr its peratinal functins. In this situatin, if the cmputer can be shared between the peratinal and test functins, the cst assciated with including BIT can be minimized. In thse cases where a system cmputer is nt available, the micrprcessr can be a very cst effective apprach. The sftware apprach fr BIT ffers many advantages. It can ffer a cmplete system check autmatically, including fault-islatin t the RU level. In additin, the sftware can be mdified t accmmdate system changes. With sftware there is the additinal capability f a memry system which can be useful in identifying a system (r cmpnent) deteriratin prir t failure. This aspect f using sftware can prvide the designer with a very pwerful test tl. Several cnsideratins shuld be kept in mind when designing a BIT system using sftware. 0 It is essential t islate the system data frm the test data. This is true fr bth the input as well as the utput. If the test signals are nt inhibited at the utput, they may be misinterpreted by the interfacing hardware as a cmmand r as fraudulent data. When mnitring the utput f a given functinal area, it is essential t prvide adequate tlerance. The amunt f tlerance will depend upn the specific applicatin. 51

56 The input stimuli shuld be kept at a minimum level t minimize their effect upn perfrmance. Input stimuli shuld be chsen t clsely resemble nrmally accepted data. Therefre, if data are supplied inadvertently t an interfacing unit, a malfunctin will nt be created in that unit. Als, stimuli shuld nt be selected s as t cause fraudulent cmmands which might be detrimental (i.e., firing cmmands, etc.). Existing data netwrks shuld be used whenever pssible. This will greatly reduce cst and als prvide testing f interface circuitry. The key ptimized fault islatin is judicius selectin f mnitring pints. Whenever pssible, a cmmn mnitring pint shuld be utilized t test mre than ne functinal area. The pssible increase in cmputer size which may be necessary fr the inclusin f BIT must be cnsidered when initially designing the ttal system. 4.9 MICROPROCESSOR AND BIT The additin f special circuits t a cmplex system fr the purpse f perfrming BIT has, as a gal, the detectin and diagnsis f faults. If the system design bjective is a lng-term MTBF then the BIT infrmatin can be used t switch t a gd spare. The system designed t prvide a lw MTTR can use BIT infrmatin t pin-pint the failed part. The micrprcessr is an attractive candidate fr use in BIT applicatins since it ffers the ptential fr a flexible apprach t testing as well as a means f standardizing BIT hardware ver a wide range f mdules. The micrprcessr may be used fr such things as 52

57 parity and ther cde cmparisns as well as statistical characterizatin and dynamic signal verificatin. The incrpratin f BIT is a useful apprach in meeting the reliability and testability gals established fr the system. The ability t accurately evaluate ttal life-cycle csts will determine if the micrprcessr can be applied as an effective BIT element. 53

58 SECTION 5.0 COMMUN I CATION SYSTEMS 5.1 DESIGN OBJECTIVES The primary bjective f designing a built-in-test (BIT) capability int the cmmunicatin sectins f a weapn system is t increase the prbability that required infrmatinal transfers will be accmplished within the prper time pericds. This gal is reached by maintaining the current status f all functinal elements in the cmmunicatin system s that alternative rutings can be selected if perfrmance degradatins r failures shuld ccur. Additinal benefits expected frm the inclusin f BIT are: Reductin f the pssibility that infrmatin may be misinterpreted due t degradatin r failure f elements in the cmmunicatins link. Imprvement in the MTTR f the system. Prvisin f failure infrmatin t assist and speed the repair f prblems. 5.2 COMMUNICATION SYSTEMS SPECIAL CONSIDERATIONS Cmmunicatin systems interface with mst f the ther sectins f a weapn system and handle a variety f data. They perate with frequencies as high as light waves and as lw as dc, with pwer levels frm micrwatts t megawatts. This can make it difficult t verify the prper peratin f sme areas. Hwever, mst areas can be checked thrugh the careful selectin f sensrs and assciated circuitry r by inference thrugh the peratin f interfacing stages. 54

59 Often the cmmunicatin links between varius elements f a weapn system will cnsist f multiple channels, many f which perfrm similiar functins. This ffers a redundancy ptential that usually is nt available with ther systems. Hwever, t prperly utilize this ptential the verall system must be designed fr that type peratin and needs a BIT capability t assist peratr cntrl f data ruting. If autmatic peratin f the system is intended, then BIT is required in rder fr the system t functin. It may nt be identified as such by the designed and may nt prvide cmplete indicatr utputs, but the mnitring and fault detectin circuitry must be there t enable autmatic transmissin link selectin. As the cmplexity f weapn systems increases, the nu her f data channels required als increases. Because many f these channels are functinally similiar and d nt require full time data flw, it becmes feasible t multiplex sme f the data channels and reduce t:.e number f transmissin circuits. This creates a unique situatin fr BIT since a single test pint can be used t mnitr several data channels. The evaluatin f the signals frm this test pint can be quite cmplex and culd require elabrate and cstly circuitry if perfrmed cnventinally. Hwever, the availability f inexpensive micrprcessrs prvides an excellent methd f perfrming this task alng with ther BIT functins if desired. There may already be micrprcessrs in the weapn system with spare capability that culd be utilized fr this r ther similiar BIT requirements. Cmmunicatin systems quite ften are spread ver large areas with different sectins separated by cnsiderable distances, thus making it difficult t perfrm certain tests. Fr example, it may nt be feasible t transmit a test pattern ver a circuit and back t the rigin fr checking in real-time since this wuld require a separate return circuit. It may be necessary t stre the test pattern and send it back ver the same link fr verificatin r it may nt be pssible t perfrm the test. 55 I

60 An additinal unique characteristic f cmmunicatin systems is their dependence n the insphere, which is an external, uncntrllable factr fr sme radi frequency links. This can prduce a circuit that perates intermittently during adverse prpagatin cnditins, which requires that failure mnitring circuitry be able t discern between these cnditins and equipment failure. Otherwise, peratr interventin will be necessary when the link appears inperative. 5.3 PERFORMACE SPECIFICATIONS The design f a cmmunicatin system shuld include BIT t prvide a quick and reliable indicatin f the system status t the user. He needs t knw whether the system is functining; and if nt, t what degree its capability has been degraded. The design f the BIT shuld be such that a measure f the systems peratin is cnstantly available t the user t assist his peratinal decisins. T enable a BIT system t be prperly implemented, a valid set f perfrmance specificatins must be established. It is imprtant fr a failure t be indicated nly when the cmmunicatin system has experienced a hard failure r a degradatin that prevents the reliable peratin f a system element. A system is nrmally designed t perfrmance specificatins that exceed the peratinal requirements fr the system t ensure adequate perfrmance after sme degradatin in the field. This allwable field degradatin is usually part f the perfrmance specificatins and establishes a basis fr setting BIT threshld levels. The perfrmance f the system may decrease belw the expected field degradatin level and still perate acceptably. This wuld be a wrst case level f peratin fr the system and a better n-g threshld fr BIT. This threshld must be set at the prper level because t high a setting wuld generate excessive failure indicatins and result in unnecessary maintenance. Cnversely, a BIT threshld level that is t lw culd allw a system t degrade belw an acceptable peratinal level and be unable t accmplish its missin befre a failure is indicated. 56

61 Threshld levels are mre ften applied t analg circuits because they generally exhibit a graceful degradatin f perfrmance with time. Digital circuits usually perate prperly r nt at all. Hwever, in data transmissin ver cmmunicatin circuits the errr rate can increase gradually until it crsses a threshld f useability. A measure f this errr rate can prvide a gd verall digital circuit test. 5.4 ENVIRONMENTAL REQUIREMENTS When BIT circuits are being designed and BIT threshld levels are being established, cnsideratin must be given t effects prduced, by the peratinal envirnment. This shuld include nt nly temperature, humidity, shck, and vibratin but als susceptibility t radiated and cnducted electrmagnetic energy. Since sme cmmunicatin systems utilize high pwer transmitters, the BIT circuitry may be subjected t sufficient energy levels t shift their perating pints and cause false indicatins f failure r inability t detect actual failures. Electrmagnetic envirnmental requirements shuld be specified s that designers can include the necessary shielding, filtering, and packaging t prevent peratinal prblems. 5.5 BIT CONSIDERATION Implementing BIT in cmmunicatin systems requires cnsideratin f many f the same factrs that must be evaluated fr the ther sectins f a weapn system. In additin, elements peculiar t cmmunicatin systems must be cnsidered, such as whether r nt t measure the nise level f a receiver. Trade-ffs will be necessary between the percentage f BIT cverage, the added reliability intrduced, the imprved maintainability, and the cst f the additinal circuitry BIT Cverage It is cmmn practice t replace entire systems r subsystems when a failure is detected during testing. This is usually required 57

62 because the level f instrumentatin is nt adequate t islate the failure t a mdule within a system. One result f this is a cstlier spares inventry. Figure 2 shws a typical data receiver blck diagram. This receiver culd be cnstructed n ne circuit bard, but mre likely it wuld be divided int tw r three sectins. A typical arrangement wuld have blcks A, B, and C n ne bard, blcks D, E, F, and G n a secnd bard, and blck H n a third. If each bard is prperly instrumented, a failure culd be islated t a single bard and nly that bard replaced. Otherwise, the entire receiver wuld be replaced. The extent t which BIT is implemented can be carried belw the circuit bard level if desired. Fr example, if bard ne fr the receiver in Figure 2 cnsists f blcks A, B, and C, it might be instrumented at pints 1 thrugh 5. A failure in the scillatr (blck C) wuld cause imprper readings at pints 4 and 5. the bard wuld be replaced at the rganizatinal level and the failure indicatin passed alng t the direct supprt rganizatin t assist in its repair. The percentage f cverage fr BIT ii determined thrugh crdinatin f the failure mde analysis, the weapn system maintenance plan, and interrelated cst cnsideratins BIT Self-Test Testing f BIT circuitry can be accmplished in several ways. One f the better appraches is t build int the circuits the capability fr self-testing. In mst BIT mnitrs a test input r a cntrl lead can be added which will allw the circuit t be actuated externally, thus verifying its peratin frm that pint ut t the indicatr. Fr analg input circuits the test input can smetimes be the input used fr calibrating the circuit. Figure 3 shws pssible circuits with self-test inputs fr analg and digital BIT mnitrs. '58

63 LLJ -j et) V) > CML I-4 Z LLI 59

64 +V BOARD INDICATOR MON ITOR POINT INPUT TEST INPUT: ISOLATION ~~AMPLIFIER m COMPARATOR FAULT OUTPUT INDICATION RE F A. ANALOG MONITOR +V +V BOARD S INDICATOR TEST INPUT MONITOR MON ITOR INPUTINU GATE BUFFER INDICATION FAULT OUTPUT B. DIGITAL MONITOR Fiaur 3. Typical BIT Self-Test Inputs 60

65 Manual r autmatic testing f BIT circuits can be utilized depending n the particular weapn system design philsphy. If a central cmputer is used t cntrl the BIT system, then a desirable mde f peratin wuld be fr the cmputer t sequentially actuate the test input t each mnitr and verify its utput. An alternative wuld be t actuate all mnitrs simultaneusly and scan each ne fr the prper utput. Manual testing f the BIT circuits can be accmplished by applying the input stimuli manually and verifying that crrect utputs ccur. In either case, utputs f BIT circuits which cntrl events such as shutting ff pwer due t vervltage must be disabled during testing Fail-Safe BIT circuitry shuld be designed t be as fail-safe as practical. The mnitr input shuld be cnfigured s that a high level represents nrmal peratin and a lw level represents a failure. A lss f signal int the mnitr wuld prduce a lw input and a failure indicatin. Therefre, a bad cnnectr, a brken wire r, in sme cases, a shrt circuit wuld als appear as a fault t the BIT system. Other fail-safe pssibilities include the use f redundant circuits and vting circuits. Because f requiring additinal hardware, these apprache- wuld prbably be used nly in critical areas r where high reliability was specified. 5.6 COMMUNICATION SYSTEMS A cmmunicatin system is used t transmit cntrl and data signals between the va-ius elements f a weapn system. These signals will primarily be digital and can be carried ver cable links and air links. Digital data is transmitted in either a parallel r a serial frmat. The parallel frmal requires a circuit fr each bit in a data wrd and generally uses a secnd grup f parallel circuits fr management functins. This type f data bus is ften used by a cmputer central prcessing unit t interface with ther equipment and is useable t a maximum distance f abut 15 meters. 61

66 Only ne circuit is required fr transmissin f data in a serial frmat. Data bits are transmitted sequentially alng with additinal bits fr prtcl functins and errr detectin, when used. When mre than ne channel f data is required, several pssibilities exist. If time permits, each channel can be sent in sequence ver a single circuit. When simultaneus transmissin is required, a separate circuit can be used fr each channel r all channels can be multiplexed nt a single r minimum number f circuits. Mst cmmunicatin links utilize radi frequency emissins, metallic cnductr cables, r fiber ptic cables t cnvey infrmatin between lcatins. RF links are used fr lng distances and fr cmmunicating with mving vehicles. Metallic cnductr cables have traditinally been used fr intercnnectins between fixed pints. Hwever, fiber ptic cables are being used increasingly because f their light weight, wide bandwidth, and resistance t interference. 5.7 ERROR DETECTION data. Several techniques are available t detect errrs in transmitted One methd requires repetitive transmissin and cmparisn f each character. Vting lgic can then be used fr crrectins. An bvius disadvantage t this methd is the increase in transmissin time required. The mst cmmnly used methd is the parity bit. By adding a bit at the end f each data wrd, all wrds can be made t have an dd (r even) number f lgic "nes". Any wrd that deviates frm this pattern has an errr. N infrmatin is included fr crrecting errrs s retransmissin f bad wrds r the entire message may be necessary when errrs ccur. 62

67 Anther technique fr detecting errrs is transmissin f the data back t the sender fr verifying. This can be accmplished ver the same circuit when the quantity f data and time cnstraints allw. Otherwise, a secnd circuit will be required. 5.8 SPECIFIC EQUIPMENT APPROACHES Mdems Mdems are used at each end f data circuits t interface between intercnnecting cables and user equipment when lng cables are invlved. They cntain the circuitry needed t cnvert data int audi frequency signals, ne fr a lgic "1" and anther fr a lgic "0", fr transmissin ver cables, and circuitry t cnvert back t lgic levels fr receptin. They als cntain circuitry fr peratinal cntrl such as end-f-transmissin detectin. Mdems are used fr full duplex and fr half duplex circuits. A full duplex circuit uses different audi tnes fr send and receive which allws simultaneus transmissin in bth directins. A half duplex circuit uses the same frequency tnes fr send and receive and therefre nly perates in ne directin at a time. A full duplex circuit can be tested by transmitting a knwn message ver the system and back t the rigin fr checking. This wuld be dne in a test mde and wuld verify the send and receive functins at each end f the cable. A half duplex circuit can be tested in a similar manner except the message must be stred at the remte end and then transmitted back t the rigin. Cntinuus testing f just the mdems can be accmplished by the additin f sme circuitry. When a mdem is transmitting, a receiver culd cnvert the audi frequencies back t digital data fr cmparisn. When a mdem is receiving, a secnd receiver culd perate in parallel with the mdem receiver and their utputs cmpared. 63

68 5.8.2 Line Drivers and Receivers Line drivers ard receivers are used t transfer data ver cables up t apprximately 1 kilmeter lng. The maximum allwable distance is a functin f the data rate and envirnment. Line drivers and receivers are available in tw distinct grups; ne fr unbalanced lines and the ther fr balanced lines. The unbalanced drivers and receivers evlved frm standard lgic circuits and perate with data signals n a single line referenced against system grund. Balanced line drivers accept nrmal lgic inputs and generate differential utputs while balanced line receivers reverse the prcess. The differential signal des nt depend n system grund fr a reference, s it prvides gd rejectin t cmmn mde nise and level shifts f the grund system between each end f the line. The best test f a cmplete circuit is the lpback test where the data is returned t the rigin fr verificatin. This f curse requires a secnd circuit fr real-time testing r strage if the same circuit carries the data in bth directins. The individual line drivers and receivers culd be cntinuusly mnitred but any reliability increase wuld nt be wrth the increase in cmplexity. Therefre, this apprach is nt recmmended Encders and Decders An encder is used t cnvert data int special frmats, such as Manchester, t increase the resistance t nise r t imprve synchrnizatin and clck regeneratin at the receiving end. A decder perfrms the reverse by cnverting data back frm a special frmat t nn-returnt-zer (NRZ). Regeneratin f a clck signal in synchrnizatin with the data stream is als generally perfrmed by the decder circuitry. Testing f encders and decders can be perfrmed separately r as part f the cmmunicatin circuit. The cmplete circuit can be tested using the lpback methd where the received data is returned t the rigin fr verificatin. This type f testing may nt be feasible except in a 64

69 test mde. Cntinuus testing f an encder culd be perfrmed by decding its utput and cmparing this with the input data stream. A decder culd be tested cntinuusly by paralleling a secnd decder and cmparing the tw utputs Receivers A blck diagram fr a receiver cnfigured fr receiving data is shwn in Figure 2. This receiver culd lgically be divided int three sectins with blcks A, B, and C n ne circuit bard, blcks 0, E, F, and G n a secnd circuit bard, ard blck H n a third circuit bard. Test pints 1 thrugh 11 are identified as pssible BIT mnitr pints. Due t the frequencies and amplitudes invlved, sme f these test pints will be very sensitive t any additinal circuitry. Test pints 1 and 2 are especially sensitive and are nt recmmended fr BIT mnitring. The utputs f the first and secnd scillatrs can be mnitred by simple RF detectr circuits which wuld cnvert the signals int dc levels prprtinal t their amplitudes. The dc wuld then g t level detectrs that wuld generate fault indicatins if the signals fell belw present values. If the receiver is intended fr peratin n mre than ne channel, the first scillatr culd have an external frequency cntrl input. If it is desired t verify that the scillatr switched t the prper frequency, then a much mre cmplex BIT circuit wuld be necessary. One pssibility is a discriminatr with a dc utput prprtinal t the input frequency. This utput wuld n t the input f a cmparatr with a trip pint cntrlled by the frequency cntrl input t the scillatr. The utput f the first mixer, test pint 5, will be a lw level signal and will need amplificatin befre a simple amplitude detectr can 65

70 be used. Hwever, integrated circuits are available that were designed as IF amplifier-audi detectrs and shuld be suitable fr cnverting the mixer utput t a dc level that can be cnnected directly t a cmparatr. A failure will be indicated when an input signal t the receiver is nt present. The utputs f the first IF, the secnd mixer, and the secnd IF shuld have sufficient amplitudes s that simple detectrs can be used t cnvert the signals t dc levels. These levels shuld then be cmpared t reference values t verify that adequate signals are present. Again, a failure will be indicated when an input signal t the receiver is nt present. The demdulatr/bit synchrnizer shwn in blck H is similar t the receive half f the mdems described in paragraph The usual input is tw audi frequency tnes which must be cnverted int serial digital data. A clck signal is generated and synchrnized with the incming data in the bit synchrnizer prtin. As with the mdem, it is necessary t duplicate the circuitry and cmpare the tw utputs t verify prper peratin Transmitter A blck diagram fr a typical data transmitter is shwn in Figure 4. Many variatins are pssible in the exact way the functins are accmplished but the general arrangement shuld be similar. A pwer supply is nt shwn but wuld be necessary t prvide the prper vltages. This supply wuld be mnitred with BIT circuits as described in Sectin 8.0 f this design guide. The numbered test pints n the blck diagram are pssible measurement lcatins fr BIT mnitrs. A simple detectr circuit t 66

71 = C) CLL xw CC 5 CD CLL M:- LLI 0 U-U 4- LJ C) CC67 C

72 Ii I I -L,,.... cnvert the signals t dc levels can be used at lcatins 2, 3, 4, 5, 7, 8, 10, and 11. The dc levels wuld then be measured by threshld detectrs t verify that the signals exceed minimum requirements. The tne generatr shwn in blck A is similar t the transmit prtin f the mdem described in paragraph 5.8.1, and fr the mst effective results, shuld be tested the same way. This wuld require that a demdulatr circuit cnvert the utput at test pint 2 back t a digital signal fr cmparisn with the input. A simpler test that wuld nly verify the amplitude f an utput at test pint 2 wuld be perfrmed as described in the preceding paragraph. If the transmitter is intended fr peratin n mre than ne channel, the secnd scillatr (blck F) culd have an external frequency cntrl input. Verificatin that the scillatr switches t the prper frequency will require mre cmplex BIT circuitry. One pssibility is a discriminatr with a dc utput prprtinal t the input frequency. This utput wuld g t the input f a cmparatr with a trip pint cntrlled by the frequency cntrl input t the scillatr. The directinal cupler (blck J) prduces tw dc utputs; ne prprtinal t frward pwer and the ther prprtinal t reflected pwer. The difference in these tw parameters is a measure f the utput frm the pwer amplifier in blck I. The signals frm the directinal cupler are used by the utput cntrl circuit t maintain a cnstant pwer level ut f the transmitter and t prtect the pwer amplifier. This is accmplished by reducing the utput as a functin f the reflected pwer, which is an indicatin f a prblem with the caxial cable r antenna. The directinal cupler utputs shuld be mnitred by BIT circuitry. This will require amplifiers because these utputs are generally less than 1 vlt in amplitude. If the transmitter design des nt include 68

73 blcks J and K, a directinal cupler shuld be added fr the BIT circuit. An indicatin f the transmitter utput can be btained frm an RF detectr cnnected t test pint 12, but this is nt the recmmended apprach Antennas Cmmunicatin system antennas will generally be fixed with mnidirectinal patterns r directinal with a mechanical psitining system. BIT can mnitr t verify that psitining systems respnd prperly t mvement cmmands. The utput f the selsyn at the antenna can be cmpared with the cmmand t determine if the prper mvement is indicated. This methd assumes that the antenna selsyn is perating crrectly. If verificatin f the selsyn is als desired then a separate psitin mnitring device, such as a gear-driven ptentimeter, can be added. Antennas shuld be matched t the impedance f the caxial cable and bth the receiver and transmitter. With a receiver it is nt a cirtical factr, and a change in impedance will nly result in a decrease in received signal strength. Hwever, with a transmitter a mismatch will cause pwer t be reflected back t the transmitter which can damage the utput stage. If the transmitter has a directinal cupler in the utput it can be used t mnitr the antenna system. If nt, ne shuld be added s that reflected pwer and its relatin t frward pwer can be cntinuusly mnitred. A threshld shuld be established fr indicating a failure cnditin but the actual values shuld be peridically recrded. By tracking these measurements the cnditin f the antenna can be mnitred and the failure pint can be predicted, allwing maintenance t be perfrmed at nncritical times. 69

74 SECTION 6.0 GUIDANCE AND CONTROL SYSTEMS The guidance and cntrl system is ne f the mst critical cmpnents f a weapn system in regards t system perfrmance requirements. The guidance and cntrl system must perfrm satisfactrily thrughut the missin, nt nly t steer the weapn t within the lethal range frm the target, but als t prvide cntrl ver ther cmpnents f the weapn system such as the prpellant system. Because f its cmplexity, the guidance and cntrl system is a prime candidate fr incrpratin f BIT and BITE, primarily t minimize fault detectin and islatin times and thereby maximize weapn system readiness and availability. The mst widely used types f guidance and cntrl systems are electrnic (inertial guidance and cntrl r radar tracking), electr-ptical (vide r laser tracking), and infrared (heat seeking). The inertial guidance and cntrl system is ideally suited fr weapn systems used against fixed targets when it is desirable t have n inflight radi cmmunicatins with the weapn system. The infrared guidance and cntrl system is used against mbile and fixed targets that emanate radiatin in the infrared spectrum r that reflect infrared when illuminated by an external surce. The radar, laser, and vide tracking systems are used against either mbile r fixed targets that d nt radiate. 6.1 SYSTEM OPERATION Inertial Guidance and Cntrl System Operatin An inertial guidance and cntrl system is a highly cmplex electr-mechanical system, which cntinuusly cmputes the vehicle velcity 70

75 and psitin, and the directin and range t a predetermined target. Figure 5 shws a typical inertial guidance and cntrl system. The heart f the system is a stable instrument platfrm with freedm f rtatin abut three rthgnal axes. Each axis is cntrlled by a gyr-cntrlled serv lp. These serv lps maintain a desired platfrm attitude with respect t the earths surface. The instrument platfrm hlds, in additin t the gyrs, accelermeters t measure vehicle acceleratins alng each f the platfrm axes. An n-bard cmputer integrates the accelermeter utputs t btain vehicle velcity and distance frm the launch site, and prvides trquing signals t the gyrs t maintain the prper platfrm rientatin. By preprgramming the cmputer prir t launch with the launch and target crdinates, the cmputer can determine the vehicle's present psitin and range and directin t the target. The cmputer prvides the steering signals t the vehicle autpilt and can als prvide shutdwn signals t the prpellant system, based upn vehicle velcity and desired flight pattern Radar Tracking System Operatin A radar tracking system utilizes the reflectin f electrmagnetic radiatin frm the target t determine range and directin t that target. Figure 6 shws a typical radar guidance and cntrl system. A pulse generatr prvides the basic timing f the system; namely, the pulse t cntrl the transmit phase, and sync signals t the cmputer t determine the time delay between transmit and receive signals and t the antenna phase cntrl. The antenna phase cntrl shifts the radiatin pattern f the antenna between successive transmissins. this manner, fur successive transmissins will radiate in fur rthgnal directins slightly displaced frm the vehicle lgitudinal axis. difference in signal strength f the received signals frm these transmissins is used by the cmputer t derive the directin f the target and t generate the prper steering signals t the vehicle autpilt. The In 71

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77 0 E-4 - z V) M -4-E-4 E > Z 0 WI - 00 F-4 E-4 z 10 WO E ZE 0. z w- 73U

78 6.1.3 Laser Tracking System Operatin The laser tracking system peratin is almst identical t the peratin f the radar guidance and cntrl system. The majr differences are that the radiatin is in the ptical spectrum instead f the RF spectrum, and lens systems are used instead f an antenna Vide Tracking System Operatin A vide tracking system, as cmmnly used n air-t-grund missiles, requires manual interventin t prvide the steering signals t the missile. A frward-lking TV camera is munted in the nse f the missile, and electrical utputs f the camera (sync and vide signals) are transmitted t the launch vehicle via radi link where they are displayed n a vide screen t the peratr. The peratr then uses a jystick t send the desired steering signals t the missile via a return radi link Infrared Tracking System Operatin The infrared system is a passive-type guidance and cntrl system which detects and tracks infrared (heat) radiatin emanating frm the target t steer the missile t that target. The system may als be used against targets that d nt generate infrared radiatin, prvided that a frward bservatin pst can illuminate the target with infrared radiatin and the target reflects a detectable prtin f the illuminatin. The heart f the system is a detectr array capable f detecting nt nly the radiatin but als the angular difference between the directin f the target and the missile lngitudinal axis. In mst systems the angular difference is measured in tw rthgnal directins, transverse t the missile lngitudinal axis. The guidance cmputer measures these angular differences and transmits steering signals t the missile t reduce the errrs t zer. 74

79 6.2 GUIDANCE AND CONTROL SYSTEM PERFORMANCE SPECIFICATION Since the tactical missin f a guidance and cntrl system is t cntrl and steer the weapn system t a pint which is within lethal range f the target, verall system accuracy is a prime cnsideratin in the establishing perfrmance requirements fr the guidance and cntrl system, alng with envirnmental and reliability cnsideratins. During the cnceptual phase f initial design, trade-ff studies must be perfrmed t establish individual cmpnent perfrmance criteria which will satisfy the verall system perfrmance requirements Inertial Guidance and Cntrl System Perfrmance Requirements The accuracy f an inertial guidance and cntrl system is dependent t a great degree n the perfrmance f the inertial instruments and their assciated serv lps. Accelermeter sensitivity must be sufficient t measure slight acceleratins, and the scale factr and bias must be cntrlled t minimize errrs in determining velcities and distances. Critical parameters fr the gyrs are: sensitivity, which must be sufficient t prevent large platfrm pinting errrs under acceleratin and vehicle maneuvering; gyr drift, which must be minimized t prevent accumulative platfrm pinting errrs; and trquing scale factr. Gyr spin mtr excitatin must be cntrlled t prevent extraneus gyr drift frm changes in angular mment. the gyr spin mass. In additin, the cmputatinal capabili rf quidance cmputer must be sufficient t determine vehicle psictip and velcities t the degree f accuracy required by the missin Radar Tracking System Perfrmance Requirements The perfrmance f a radar tracking system is determined by its maximum range, pinting accuracy, and its range determinatin. The maximum range is dependent n the peak utput pwer f the transmitter, the receiver sensitivity, and the frequency stability f bth the 75

80 transmitter and receiver. The pinting accuracy is dependent n the antenna alignment and the beam width r the radiatin pattern f the antenna. The accuracy f the range determinatin is mstly dependent n the stability and granularity f the timing circuits, and t a lesser degree n the antenna beam width which shuld be narrw enugh t minimize receptin f all signals except direct reflectin frm the target Laser Tracking System Perfrmance Requirements The perfrmance requirements fr a laser tracking system are almst identical t thse fr a radar tracking system with the difference that an ptical system is utilized instead f an antenna Vide Tracking System Perfrmance Requirements The critical parameters in a vide tracking system are: the ptical alignment f the camera t the vehicle axis; the field f view f the lens system; and the sensitivity f the camera, which determines its ability t prvide a usable vide image t the peratr at extreme range and under varius light cnditins. The depth-f-field and/r fcus f the lens system must be adequate t prvide a clear image f the target area Infrared Guidance and Cntrl System Perfrmance Requirements The range and accuracy f an infrared guidance and cntrl system is largely determined by its sensr array. The sensitivity f the infrared detectrs must be great enugh t detect the target radiatin at sufficient range t allw missile maneuvering, yet nt great enugh t lck nt errneus surces. Where multiple detectrs are utilized, the sensitivity f each shuld be balanced t the extent that a target directly ahead will prvide equal utputs frm all detectrs. The field-f-view f the sensr array shuld be narrw enugh t exclude 76

81 general backgrund radiatin and enable lck-n t an individual target and wide enugh t allw detectin f the target within a reasnable pinting angle frm the missile flight path. 6.3 ENVIRONMENTAL REQUIREMENTS Since guidance and cntrl systems are partially r whlly cntained in the missile airframe, their design cnsideratins must include the missile envirnment. This envirnment includes shck and vibratin, acceleratin, temperature and misture extremes, and barmetric pressure variatins. Size and weight f the system, in as much as they affect the range, and aerdynamics f the missile are anther cnsideratin. 6.4 BIT CONSIDERATIONS The primary bjective f designing built-in test capabilities int guidance and cntrl systems is t increase the prbability that the weapn system will be delivered t a pint within lethal range f the target. This gal is reached by determining the status f all functinal elements in the guidance and cntrl system s that crrective actin can be taken in the event f system degradatin r cmpnent failures. Additinal benefits btained frm the inclusin f BIT are: Reductin in the MTTR f the system thrugh imprved fault islatin. 0 Reductin in skill levels f maintenance persnnel BTT Cverage In many guidance and cntrl systems, a failure during testing necessitates changeut f majr assemblies r the expenditure f cnsiderable man-hurs t islate the malfunctin t the mdular level. This is 77

82 required because the level f external instrumentatin is nt adequate t islate the failure t a specific mdule within the system. This practice results in a cstly spares inventry and/r excessive system dwntime. With prper utilizatin f BIT capabilities, failure islatin t mdular levels can be achieved. Fr the typical inertial guidance and cntrl system depicted in Figure 5, the three gyrs, azimuth reslver, accelermeters, drive mtrs, and angle readuts are all cntaiij within the platfrm structure. The serv amplifiers are munted in a secnd assembly, and the cmputer is the third majr cmpnent. With prper instrumentatin, such as at pints 1 thrugh 11, and selective stimuli applied t each platfrm axis, a failure can be islated t a single ne f these cmpnents. Fr example: a defective "X" gyr, when trqued, will give errneus signals at pints 1 and 2 when the platfrm azimuth axis is at zer degrees, and will give errneus signals at pints 1 and 6 fr a platfrm azimuth f 90 degrees. Fr each individual guidance and cntrl system, the extent f BIT cverage is determined by failure mde analyses, the weapn system maintenance plan, and related cct cnsideratins Self-Test Testing f BIT circuitry can be perfrmed in several ways. In systems that cntain digital cmputers, the cmputer can be utilized t perfrm all ff-line system testing, including self-check f BIT circuitry with minimal peratr interventin. A typical test sequence fr this type f system wuld be as fllws: A cmputer self-test prgram cnsisting f memry tests, arithmetic lgic tests, and cntrl lgic tests. 78

83 A cmputer-cntrlled check f analg and digital interface circuitry with cmputer utputs tied back t cmputer inputs. This test wuld als prvide indicatins t an peratr t check utput interface circuitry. 0 Cmputer-cntrlled testing f the entire guidance and cntrl system. This series f tests wuld cnstitute the prelaunch test sequence Fail Safe BIT circuitry must be designed t be as fail safe as practical. The reliability, as measured by MTBF, shuld apprach an rder f magnitude greater than the remainder f the system hardware. the circuit design shuld be cnfigured t enhance the peratinal reliability. In additin, Fr example, digital inputs t BIT shuld be cnfigured such that an active r high state represents the nrmal perating state, with a zer r lw state denting a failure. In this manner, pr cnnectins, pen circuity, and grund faults are readily detected. Redundant r vting lgic type f circuits can be utilized in critical areas where high reliability is a requirement Prelaunch Testing Prelaunch testing f guidance and cntrl systems cnsists f exercising all peratinal mdes f the system and verifying prper respnses t test stimuli. The type f tests will vary accrding t the type f system. Fr a typical inertial guidance and cntrl system, the test scenari fllws a basic building blck f integratin and calibratin testing: 79

84 - IJ I I! I!. - Verificatin f Platfrm Cntrl Circuitry Platfrm serv lcs are tested in bth caged and stabilized mdes f peratin. A grss check f gry trquing circuits is perfrmed, and the platfrm angle readut devices are tested fr prper utput. Instrument Calibratin Using knwn input stimuli (earth rtatin rates and gravitatinal attractin), gyr trquing scale factrs and drift cmpensatin, and accelermeter scale factrs and biases are established and/r adjusted. Operatinal Tests The system is exercised thrugh a sequence f pseudperatinal sequences while mnitring platfrm angular errrs and cmputed psitin. During the level alignment mde, the platfrm is trqued by the accelermeters t achieve zer gravity n the level axis instruments, and the level axis deviatins are measured. In the azimuth alignment mde, earth rate trquing fr a specified heading is applied t the gyrs, the platfrm is placed in a gyr-cmpassing mde, and the final azimuth and level axis errrs are measured and tested t be within design specificatins. In the free-flight mde, the system perates in its nrmal pst-launch mde, and platfrm angle errrs and cmputed psitin are measured and tested. be within the specified limits. Fr an infrared tracking system, prelaunch tests wuld include checks f the infrared detectr sensitivity and the directivity f the sensr head. These tests require a infrared surce as a test stimulus. 30

85 l I I I * I I i i,.. This surce must be cntrlled in bth the magnitude f radiatin and its relative lcatin with respect t the missile. Prelaunch testing f laser r radar tracking systems wuld include measurement f the transmitter pwer and beam width as well as the directivity and sensitivity f the receiver sensrs and/r antenna. In additin, a check f the range determinatin circuitry shuld be perfrmed using a delay circuit t synthesize a receiver input signal Pst Launch Testing Pst launch testing f guidance and cntrl systems is basically a mnitr-type f checking t detect catastrphic failures which culd seriusly impair the weapn system effectivity. Fr example, in an inertial guidance and cntrl system the lss f gyr spin mtr excitatin wuld result in a lss f stable platfrm reference and errneus accelermeter utputs, causing the weapn t veer drastically frm the desired flight path. By mnitring the excitatin and/r accelermeter signals, the failure wuld be detected and apprpriate crrective actin, such as reducing the steering signals t null and abrting any fuze signal based upn a pssible errneus range calculatin, culd be effected. 81

86 SECTION 7.0 POWER SYSTEMS 7.1 DESIGN OBJECTIVES The pwer supply sectins f weapns systems shuld be designed with a built-in-test (BIT) capability t prvide an increased assurance f peratinal readiness at all times. By including BIT, the mean-timet-repair (MTTR) is reduced, thus prviding an increase in system availability. Out-f-tlerance cnditins and failures in ther parts f weapns systems due t incrrect supply vltages will be reduced with a cnsequent imprvement in reliability. 7.2 SYSTEM OPERATION Pwer systems can be divided int three sectins: pwer surces, pwer cnverters, and pwer regulatrs. Table 1 lists sme f the mre cmmn types in each divisin. Sme pwer systems may nt require all three sectins; whereas, ther systems may use multiple cmbinatins f the three. Figure 7 shws a blck diagram f a typical pwer system fr a small missile. If the missile had a built-in guidance system it wuld prbably als require 400 Hz ac, and the pwer system wuld include a mdule fr cnverting dc t ac. Sme missiles derive their internal pwer frm an Auxiliary Pwer Unit (APU) which usually perates n high pressure gas stred in the missile. An APU utput f 400 Hz ac can directly pwer the guidance system and can be cnverted t the prper dc levels fr perating ther electrical systems. T reduce the strage requirements in missile, external pwer is utilized during standby and part f checkut. The system is then switched t internal pwer fr the last part f checkut and launch. The peratin f the pwer system n bth external and internal pwer shuld be verified with BIT circuitry. The BIT mnitrs can ensure that internal pwer is functining prperly befre the system is switched frm external. 82

87 LLIn LnL CDC LUL cu LU 0 Lu c (

88 Table 1. Pwer System Divisins Pwer Surces Pwer Cnverters Pwer Regulatrs Batteries DC t DC Linear DC t AC Switching Auxiliary Pwer Units AC t DC AC AC t AC Mtr-Generatr Sets A mtr-generatr set is nrmally used t prvide ac pwer fr a fire cntrl unit. The pwer is ruted t the varius sectins f the fire cntrl unit where cnverters and regulatrs prvide the particular vltages required by individual pieces f equipment. In cases where several items use a specific vltage such as 28 Vdc, ne regulatr will perate a bus, and the pwer will be ruted as required. Decupling filters are then used at each lad t prevent undesirable interactins between units. The fire cntrl unit pwtr system shuld cntain sufficient BIT circuitry t cntinuusly define the peratinal status and pin-pint any failures t specific lcatins. 7.3 SPECIAL CONSIDERATIONS Since a pwer system feeds pwer t all areas f a weapns system, it is imprtant t maintain cntinuus mnitring n all utputs. The prper peratin f a weapns system is dependent n all vltages being crrect. Sme equipment als requires the applicatin f vltages in a particular sequence and smetimes with time delays. Fr instance, a pwer amplifier tube in a transmitter requires up t 2 minutes between applicatin f filament and plate vltages t allw the cathde t reach perating temperature. Bth vltages can safely be remved at the same time. A cmputer requires that its basic vltage, usually 5 vlts, be applied prir t all ther vltages and remved after the thers. These special time 84

89 sequence funtins perfrmed by the pwer system shuld be verified by BIT mnitrs. The BIT circuitry can be prgrammed t inhibit imprper sequences r time delays. When a failure ccurs in a pwer system utput, the vltage may g high and prduce catastrphic results in any equipment cnnected t that utput. Crwbar circuits are smetimes used t detect such an vervltage cnditin and shrt the utput. This will cause a fuse r circuit breaker t pen and prtect the lads frm the vervltage. If it is desired t test a crwbar circuit, it must be discnnected frm the pwer supply and stimulated with the required vltage t verify trip actin. The trip vltage shuld be remved and a lwer vltage applied t verify that it des nt trip belw the required pint. After successfully cmpleting these tw tests, it wuld be recnnected t the pwer circuit. A BIT circuit wuld need t be specially designed fr the crwbar test and wuld nly be actuated n manual r cmputer cmmand. A BIT mnitr nrmally perates frm the pwer utilized by the ther circuits in an area. Hwever, the BIT circuits mnitring pwer systems need a separate r redundant surce f pwer s that a single vltage failure will nt render the BIT circuit inperative. This is especially imprtant if autmatic switchver t backup mdules is anticipated. 7.4 PERFORMANCE SPECIFICATIONS Specificatins fr pwer system utputs and input pwer requirements fr all ther systems must be evaluated t determine realistic settings fr the BIT mnitrs. When several mdules perate frm a pwer bus, their input requirements will prbably be smewhat different. The mst critical f the input requirements must be used fr determining the BIT mnitr settings. 85

90 I -!E I I 1 I - BIT circuitry shuld be used t mnitr intermediate pints within pwer systems. Fr example, in Figure 7 mnitring the input and utput t each f the three vltage regulatrs wuld prvide infrmatin fr islating a failure t the cnverter r a regulatr. Acceptable perfrmance specificatins must be established fr all these intermediate pints s that limits fr the BIT mnitrs can be determined. 7.5 BIT CONSIDERATIONS Many factrs must be cnsidered when implementing BIT int a pwer system. The gal is t imprve the reliability f the weapn system; therefre, BIT circuitry must be reliable itself. BIT design shuld be riented fr fail-safe peratin s that any failures in BIT circuits r intercnnecting cables will result in a failure indicatin. BIT mnitrs shuld als include prvisins fr self-testing s that prper peratin can be verified whenever necessary. The extent f BIT cverage must be established. It will nrmally extend dwn t the smallest element that is plug-in replaceable. Hwever, additinal test pints may be specified in plug-in elements t imprve their testability during higher echeln maintenance. The amunt f BIT cverage shuld be determined thrugh crdinatin f the failure mde analysis, the lgistic supprt analysis, the weapns system maintenance plan, and interrelated cst cnsideratins. 7.6 SPECIFIC EQUIPMENT APPROACHES Pwer systems will require a diverse series f measurements t cmpletely define their perating characteristics. Predminant amng these is the determinatin that vltage levels fall within prescribed upper and lwer limits. This measurement will be required at numerus pints in a pwer system and can utilize a standard sensr that can be prgrammed fr vltage level and plarity. Test pint lcatins and types f measurements fr the different elements that cmprise a variety f pwer systems are examined in the fllwing paragraphs. 86

91 7.6.1 Pwer Surces Three general types f pwer surces cmmnly used in weapns systems are batteries, auxiliary pwer units, and mtr-generatr sets (see Table 1). Each type perates differently and therefre presents unique mnitring requirements Batteries - Batteries are nrmally used where a limited amunt f pwer is required and ther surces are nt cnveniently available. They can prvide pwer at a lw rate fr a lng time r at a high rate fr a shrt time. All batteries have internal leakage current which gradually reduces the stred energy at a rate dependent n the internal cnstructin f the battery and the strage temperature. The charge state f a battery shuld be mnitred t ensure that adequate energy is left t accmplish its required task. battery and its intended use. The BIT circuitry used will vary depending n the type f There are many different batteries with varying characteristics, but they can be gruped int tw majr categries which are: Prime - must be replaced when discharged Secndary - can be recharged when necessary Bth types f batteries shuld have a sensr t mnitr the terminal vltage. This is a reasnable measure f the charge state n mst batteries, especially if dne under lad. Sme batteries, nicklecadmium is a gd example, have such a flat discharge curve that is is difficult t determine the charge state frm the terminal vltage. On these the vltage measurement des reveal if the battery is cmpletely discharged, if ne r mre f the cells are shrted, r if the internal resistance has increased s the battery will n lnger handle the required lad. 87

92 Prime batteries in weapns systems are nrmally replaced at scheduled intervals t ensure that wrkable batteries will be in place when needed. If BIT sensrs are used t mnitr the status f these batteries, the cnfidence level will be increased since early failures can be detected. The BIT circuitry shuld nt btain its perating pwer frm these batteries but frm an external surce such as the pwer that perates the missile circuitry during testing. When secndary batteries are used t pwer a system, peratinal testing can be perfrmed, and the batteries can then be recharged t full capacity t be ready fr future use. When lng-term strage is required, peridic charging r trickle charging is used t maintain full capacity. The terminal vltages f these batteries will vary ver a wide range between the n-lad charging situatin and the full-lad discharging situatin. Sensrs fr tw lw vltage threshlds and ne high vltage threshld are needed t prvide adequate mnitring f their cnditin. One lw threshld shuld be the minimum allwable vltage under lad with n input frm a charger. The ther lw threshld shuld be the minimum acceptable vltage reached during charging, and the high threshld shuld be the maximum acceptable vltage reached during charging. The utput frm the sensr mnitring the minimum vltage attained during charging will indicate a failure except fr the latter prtin f the charge cycle. Cnsequently, this indicatin shuld either be part f a manual test r shuld be qualified fr nly the apprpriate time perids Auxiliary Pwer Units - An Auxiliary Pwer Unit (APU) shuld have BIT mnitrs n all utputs t check fr lw vltage and high vltage, and when apprpriate, fr frequency accuracy. Since an APU will be perated nly during a launch sequency r fr testing, the utput mnitrs can be activated fr nly thse time perids. Hwever, if the missile is als tested using external pwer in place f the APU, the BIT sensrs can als be used t mnitr the external pwer. This will require the sensrs t 88

93 be cnnected beynd any devices used t switch between pwer surces. If it is als desired t mnitr the APU utput befre transferring frm external pwer, then a switching arrangement will be required fr the sensrs, r separate sensrs must be used. Mst APU's derive their pwer frm cmpressed gas which is stred in a high pressure cntainer until needed. The pressure in this cntainer must be regularly checked t ensure that an adequate supply f gas is available. A BIT sensr can be used t cntinuusly mnitr this pressure and prvide a status utput t a central lcatin. Transducers are available that prduce an analg utput relative t input pressure r that switch levels digitally at preset values f pressure Mtr-Generatr Sets - Fire cntrl units nrmally receive their perating pwer frm Mtr-Generatr (MG) sets. When pssible, energy frm lcal pwer grids is utilized, but MG sets are maintained fr backup in case f lcal pwer failure and becme the prime surce during emergency cnditins. This input pwer t fire cntrl units will be cnverted t the varius levels required t perate the different systems, but shuld be mnitred at the input t verify that it stays within prper limits. An MG set cnsists f a generatr cupled t the utput shaft f typically a diesel engine. The engine is perated at a relatively cnstant speed s the generatr utput frequency will be within tlerance. There are several parameters relative t prper peratin f the engine that shuld be mnitred. The amunt f fuel remaining The engine clant temperature 89

94 The battery vltage The lubricating il pressure When cmmercial pwer is being used and the MG set is nt in peratin, the fuel remaining and the battery vltage shuld cntinue t be checked t assure system readiness at all times. The BIT sensr mnitring il pressure wuld need t be inhibited with the engine nt perating t prevent a false failure indicatin Pwer Cnverters Pwer cnverters are used t change input pwer t the ac and dc vltage levels required fr perating the different sectins f weapns systems. They als cnvert 60 Hz r dc pwer t 400 Hz when this frequency is needed. The utputs frm pwer cnverters can be used directly r can be ruted thrugh regulatrs when clser tlerances are required. Fur basic types f pwer cnverters are listed in Table 1. The tw cnverters used t prvide ac pwer will nrmally use switching techniques t maintain high efficiency. The frequency f the utput pwer is held t any necessary tlerance range by use f the prper internal cntrl elements. Hwever, the frequency shuld still be mnitred by a BIT sensr t verify that it is within the desired limits. The amplitude f the utput ac is regulated in sme cnverters. In thers, the utput is directly prprtinal t the input vltage with additinal variatins prduced by lad changes. Fr these units any regulatin must be accmplished external t the cnverters. All cnverter utputs shuld be mnitred with BIT circuitry except where a cnverter and a regulatr are cmbined n a single PC card. In that case, the cnverter utput shuld be brught t a test pint t imprve the testability f the PC card in the event f failure. 90

95 7.6.3 Pwer Regulatrs Regulatrs are used t reduce, t acceptable limits, the variatins in pwer prvided t equipment. Vltages direct frm pwer surces can vary ver a relatively wide range just due t the nrmal perating characteristics f the surces. Fr example, the utput vltage frm a battery can decrease by as much as 15 percent as its energy is depleted. Additinal variatins will be prduced by changes in the lad. Sme pwer cnverters include regulatin against input variatins and smetimes against lad changes n ne utput. If multiple utputs need regulatin r if tighter specificatins are necessary, the separate regulatrs must be used. There are tw types f regulatrs generally used fr dc vltages - linear and switching. Linear regulatrs prvide the best regulatin, least ripple, and quickest respnse t lad changes while switching regulatrs prduce the highest efficiency with the smallest and lightest package. The chice f which ne is used is based n specific requirements fr a particular pwer system and can be a cmbinatin f the tw. Bth regulatr types shuld have BIT mnitrs n their inputs and utputs. When mre than ne regulatr is perated frm the same pwer cnverter utput, it is nt necessary t duplicate the mnitrs. A single BIT sensr can mnitr several regulatr inputs and the pwer cnverter utput cmmn t them. T prevent duplicatin, yet prvide cmplete cnverage, BIT mnitrs shuld be specified fr pwer cnverter and pwer surce utputs rather than regulatr inputs. If vervltage crwbars are used in the pwer system, they shuld be n the utputs f the regulatrs. This des nt bviate the need fr BIT sensrs n the utputs. The crwbars will prvide prtectin against catastrphic failures; whereas, the BIT sensrs will detect lng-term vltage changes, either high r lw, due t circuit drift. The BIT sensr high threshld level shuld therefre be set belw the crwbar trigger level. 91

96 Regulatrs are smetimes used n 60 Hz ac pwer t reduce the vltage variatins. These regulatrs nrmally utilize magnetic principles and cnsequently are heavy and bulky. They are very reliable but their utput shuld still be mnitred with a BIT sensr. Regulatin f 400 Hz ac pwer is usually accmplished at the pwer cnverter when needed. If the cnverter itself des nt regulate its utput vltage, this functin can be perfrmed by regulating the input t the cnverter. In effect, a dc regulatr ahead f the cnverter wuld be cntrlled by the ac ut f the cnverter t maintain the prper ac vltage. This same type regulatin can be used fr ac t ac pwer cnverters als, since they cnvert input ac t dc then cnvert this dc t the utput ac. A BIT sensr shuld mnitr the dc level frm the regulatr utput t the cnverter input. 92

97 SECTION 8.0 BASIC BIT/BITE DESIGN OUTLINE 8.1 INTRODUCTION The utline cntained in this sectin summarizes the steps required fr the cst effective inclusin f BIT/BITE in the develpment f Army Missile Systems. The design prcedures are applicable t mechanical/electrical systems and subsystems dwn t a level f detail dependent n available data and the stage f system design. A prime requirement fr the cst effective applicatin f BIT/BITE is that the fllwing design prcedures be incrprated early in the system design. Redesign f cmpleted designs is a cstly methd f implementing BIT/BITE. BIT systems have been functinally used as g/n-g devices fr many years n mechanical, electrical, and chemical systems. Hwever, they were called alarms. Life-cycle csting has emphasized the high cst f maintenance in terms f fault lcatin and islatin times as well as the maintenance skill level required t service mdern weapns. Reductin f this cst has led t the requirement that BIT nt nly prvide g/n-g signals, but that fault islatin and fault lcatin times be reduced. This reductin in maintenance time is accmplished by including, in the hardware design, test pints, sensrs, and indicatrs t adequately mnitr the significant equipment faults that can ccur. Adequate Mnitring Lcate and islate the fault t the rep aceable hardware as determined by the level f maintenance being perfrmed. Significant Faults Thse faults with the best chance f ccurring and which nave the largest fault islatin and lcatin times. k.

98 AO.A SPERRY SYSTEMS MAMASEMENT HUNTSVILLE AL pea DESISOd S4JDE, BUILT-ZN-TEST AND BUILT-IN-TEST EQUIPMENT I-EC u) r D!.10 ffffffffffff APR al OAACS UNCLASSIFIED SP ORSNI/RL-Clt-81-4N 212

99 The abve requires that BIT equipment be designed t accmplish the wrk f a highly trained technician, thus reducing the maintenance skill level requirements. BIT system design t accmplish the abve cnsists f: Quantitatively specifying BIT as required by system availability as shwn in paragraph 8.2. Evaluating candidate BIT systems based n the system blck diagram used fr FMEA as shwn in paragraph 8.3, and determining that the BIT detectability level specificatin has been met. 8.2 BIT DETECTABILITY LEVEL SPECIFICATION The perfrmance specificatins fr BIT are discussed in Sectin 3.0, paragraph 3.8, f this Design Guide. The BIT level f detectability (k) is f prime imprtance and is gverned by the system availability requirement as defined in Equatin (1). Detectability is determined by first cmputing the jint detectability/maintainability prbability km(t r ) frm which k is set t determine maintainability, Equatin (3). The mean-time-t-repair (McT) is then assessed, Equatin (4). The details f these steps are as fllws: Availability (peratinal readiness) f the system as time (ta) is: A(t r ) = R(t m ) + [km(tr)][l - R(t)], (1) where R(t ) Prbability that the system will survive the specified missin f duratin tm withut failure, t = Specified turnarund time, r maximum dwntime fr repair f system, 94

100 k = Prbability that if a system failure ccurs it will be detected during system checkut, and M(t r ) = Prbability that a detected system failure can be repaired in time, tr, t restre the system t peratinal status. System analysis determines missin reliability R(t m), missin availability A(t r), and km(t r) is determined frm Equatin (1) as: A~tr) - R(tm) km(tr) = l -R(t) (2) km(t ) is the jint prbability, given that a system failure has ccurred, that the failure will be detected and repaired within turnarund time t r ' BIT detectability level (k) is set by system analysis t determine the maintainability requirement as: km(t r ) M(t r) k (3) Equatin (3) means that M(t r) percent f all system repair actins must be cmpleted within the specified turnarund time (t r). The mean-time-t-repair (McT) is cmputed frm the maintainability requirement as: Mr -t MCT (4) = lnllm(tr)( 95

101 8.3 BIT SYSTEM DESIGNS Candidate BIT systems fr design are derived in a cst-effective manner by lcating integral sensrs at prper test pints fr perfrmance mnitring and fault islatin. The test pint selectin is based n prbability f failure data fr each functinal area s that the measurements are biased in the areas mst likely t fail. Naturally sensr feasibility and cst must als be taken int cvnsideratin fr a csteffective BIT design. The fllwing paragraphs illustrate a straightfrward methd f test pint (sensr) selectin based n the system functinal blck diagram (Figure 8) used in the FMEA. The design cnsists f the fllwing: 0 Initially, test pints (sensrs) are lcated n all inputs and utputs f the functinal areas f the system blck diagram. A fault cde matrix is made fr the sensrs. 0 Varius sensr sets are evaluated using the fault cde and failure data. Finally, the BIT detectability level is cmputed and evaluated t meet the specificatins Base Test Pint (Sensr) Lcatin A general system blck diagram shwing inputs and utputs frm each functinal area is depicted in Figure 8. The functinal areas represent electrical and/r mechanical subsystems and crrespnd t Line Replaceable Units (LRU's) as defined by the level f maintenance. Sensrs are shwn at each input and utput. It shuld be nted that this is the ultimate in sensr requirements and maximizes the cst f sensrs. The bject f the fllwing fault cde establishment and sensr set evaluatin is t reduce the number f sensrs required t design a cst-effective BIT system. 96

102 < 00 U(- OCCA S- cm (A ( c 0 LOL 97u

103 8.3.2 Fault Cde Matrix Based n the system blck diagram, a fault cde is established. The fault cde is a matrix tabulating the functinal area failed versus sensr number sensing a fault cded as 0 r sensing a n-fault cded as a 1. The fault cde as derived frm Figure 8 wuld be as shwn in Table 2. Table 2. Fault Cde Matrix Functinal Area Sensr N. Failed f N Fault l The abve fault cde is simplified by assuming that all sensrs dwnstream f a fault indicate that a fault has ccurred. This is nt necessarily true, but the sensr immediately fllwing the failed LRU must indicate a fault fr crrect BIT fault islatin. The fault cde is evaluated fr redundant sensrs and the degree f functinal area islatin. Clumns 7, 8, and 9 f Table 2 are identical, thus tw f the sensrs are redundant. Als, identical clumns 2 and 3 indicate that ne f these sensrs may be redundant. Redundant sensrs can be eliminated if the utputs they are mnitring are 100 percent dependent; i.e., sensrs 7 and 8 are mnitring a cmmand utput f functinal area number 6, and if bth sensrs fail when this functinal area fails, the 98

104 utputs are 100 percent dependent. Sensrs 2 and 3 are mnitring utputs f FA2. Bth sensrs will Lnly fail if there is a failure in cmpnents cmmn t the tw channels. Als similar rws in the fault cde matrix shw that the sensrs cannt discriminate between faults in these functinal areas; i.e., failures in functinal areas 6 and 7 cannt be lcalized in the fault cde by sensrs nly. It is necessary t replace ne unit, either 6 r 7, and repeat the test t islate the failure. Having eliminated the redundant sensrs, engineering judgement must be used in terms f failure prbabilities t assure that: Sensrs islating frequent faults are mst desirable. Unique fault cde patterns and minimum number f substitutins are mst desirable. The prbability f a given LRU failure can be fund frm: P = 1 - e - T, (5) where P is the prbability f failure, is the failure rate per lo 6 hurs, and T is the missin time BIT System Evaluatin The ultimate BIT system, as shwn in Figure 8, measures all inputs/ utputs, and islates t-i the lwest pssible level. LRU and sensr evaluatin data is used in a straightfrward manner t vinimize the number f sensrs required t meet the BIT detectability specificatins. Tables 3 and 4, using the general system blck diagram shwn in Figure 8, illustrate a methd f tabulating the LRU and sensr data required fr analysis. This data and the 99

105 fault cde matrix (Table 2) are the data base frm which varius sensr sets can be frmed fr evaluatin. The prcess f evaluatin t designate the use r eliminatin f varius sensrs is illustrated by the fllwing: Redundant sensrs are eliminated by nting duplicate clumns in the fault cde matrix (Table 2) while taking int cnsideratin the dependency relatinship tabulated in clumn 5 f Table 3. 0 LRU islatin pssibilities are fund by nting duplicate rws in the fault cde matrix (Table 2). LRU candidates are fund by evaluating clumns 4, 6, 7, and 8 (Table 3). Thse with the largest X, M CT, TFL, and TFI are prime candidates fr BIT. The sum f clumns 2 and 3 (Table 3) is a measure f the number f sensrs required t islate a given LRU. The larger the number f inputs and utputs, the higher the cst in sensrs. LRU's with a minimum number f inputs and utputs shuld be cnsidered fr BIT islatin. Sensr failure rates, clumn 3S f Table 4, must be balanced against the sensr fault indicatin rate, clumn 2S, t minimize false alarms. In rder wrds, a sensr failure rate eqivalent t its false alarm rate will result in numerus false alarms by the BIT system and cause mistrust by peratinal persnnel. 0 Feasibility, cst, and cmputatinal requirements must be cnsidered t measure the benefits f adding a particular sensr. 100

106 Clumn 7S (Table 4) emphasizes the basic past use f BIT as an alarm device. Clumn 8S (Table 4) is used t evaluate the cst/benefit f BIT. Table 3. LRU BIT Evaluatin Data TI (Mean- (Fault (Fault (x Time- Lca- Is- (Maint. (Maint. t- tin latin Skill Skill (LRU (Input (Output Failure (Output Repair Time Time Level Level (FA) Sensr Sensr Rate 6 Depen- Withut'Withut Withut Withut With N. N.) N.) xlo) dency) BIT) BIT) BIT) BIT) u BIT) 1-1 MCT1 TFL1 T FI X 2 2 D23 MCT2 TFL2 TFI 2 3 X 2-3 D X3 MCT3 TFL3 TF X 4 MCT4 TFL4 T F 4 5 2,4,5 6 x 5 MCT5 TFL5 TFI5 6 6,8 7 x 6 7 D79 MCT6 TFL6 TFI 6 9 x6-9 D 910O x 7 MCT7 TFL7 iti A 8 MCT8 TFL8 TI 8 Clumns 1, 2 and 3 are cmpleted frm the system blck diagram. Clumn 5 is a measure f the dependence (D) f multiple utputs which have cmmn cmpnents and is a functin f the number f cmpnents 101

107 and/r failure rates. One-hundred percent dependency between utputs means that if ne utput fails the ther als fails and can be cmputed as: D C, (6) C+AD where D is the dependency f utput i n utput j, AC is failure rate f cmpnents cmmn t utputs i and j, and AD is failure rate f cmpnents peculiar t the i utput. Clumns 4, 6, 7, 8, 9 and 10 are cmpleted frm FMEA and maintenance analysis data. Table 4. Sensr BIT Evaluatin Data is 2S 3S 4S 5S 6S 7S 8S (Fault (Cmpu- (Mean at Failure tatin (Required Time- (Sensr Rate Rate (Feasi- Require- fr G/ T- N.) X10 6 ) X10 6 ) bility) (Cst) ments) N-G) Repair) 1 F 1 ASl N MCTSI 2 F 2 AS 2 N MCTS2 3 F 3 AS 3 N MCTS3 4 F 4 AS 4 N MCTS4 5 F 5 A 5 N MCTS5 6 F 6 A$6 N MCTS6 7 F 7 AS7 N MCTS7 8 F 8 A$8 N MCTS8 9 F 9 AS 9 N MCTS9 10 F 10 ASO Yes MCTSIO 102

108 Clumn IS tabulates the sensrs frm the system blck diagram. Clumn 2S is cmputed by summing the failure rates f LRU's causing the sensr t indicate a fault. Fr instance: F 4 = 1 + X2-3 + x 4 (7) Clumn 3S and 8S are btained frm FMEA and maintenance data. Clumn 7S is frm system analysis. Clumn 4S, 5S, and 6S are based n analysis f the particular sensr hardware requirements and can vary frm a weighted scale f I t 10 t detailed dllar and/r man-hur requirements. Sensrs are eliminated frm Figure 8 based n the abve criteria, and the varius sensr sets are evaluated using failure data as fllws: BIT Detectability Level (BDL) BDL u (8) BIT Islatin Level (BIL) BIL -ux NI (9) u where A is the failure rate withut BIT, Au is the failure rate f cmpnents undetected by BIT, and ANI is the failure rate f cmpnents nt islated by BIT. 103

109 Cmparisn f the abve cmputed levels with specificatins determines whether the varius sensr sets meet the requirements. example, using sensrs 1, 6 and 9 in Figure 8: E EXL i- X8 BDL= (8) i BIL = i- ( 8 ) = (X 2 +X 3 +X 4 +X 5 +X 6 +X 7 ) -X (X 8 ) (9) Fr Design Example Based n the previus criteria and the assumptins: X 1 <X 2 2, 2 _ 3,' 3,X 4 ; sensr set 1, 6, 7, 8, 9 and 10 wuld be picked. Sensrs 7 and 8 wuld be eliminated by redundancy cnsideratins; leaving sensrs 1, 6, 9 and 10. The BIT Detectability Level (BDL) and the BIT Islatin Level (BIL) wuld be cmputed fr these sensrs as: u _ (10) 1 - u- NI X i -(X 2 +X3 +A 4 +X5+X6+X7+X 8 ) B IL - -- X. 1 (11) u 1 where A is the failure rate withut BIT = sum f all LRU X's, X is the failure rate f cmpnents undetected by BIT; i.e., u this is zer since sensr N. 10 faults n all failures, and ANI is the failure rate f cmpnents nt islated by BIT; i.e., this is the same as A i- I since LRU N. 1 is the nly functinal area islated by the abve sensr set. 104

110 -- -- It is bvius frm the abve that the BIL fr this sensr set is very bad and anther set f sensrs shuld be selected. The abve prcedure is fllwed until sensr sets are btained satisfying the BDL and BIL specificatins. An ptimum set f sensrs can then be selected based n the imprvement in mean crrective maintenance time (MCT) using the frmula: Ex itr. - Xj TS.+XBTRB MCT Mi xi, (1RB (12) where X. = failure rate f the ith unit, TR. = mean-time-t-repair the ith unit withut BIT, N. = failure rate f the jth unit which cntains BIT, TS = time saved in repair f the jth unit by incrprating BIT, X B = failure rate f BIT circuitry, and TRB = the time required t repair failed BIT circuitry. T S = TLI,- TLI = Time saved by incrprating BIT, where TLI, TLI = mean time required t perfrm fault lcatin and islatin with n BIT, and = mean time required t perfrm fault lcatin and islatin aided by BIT. 105

111 BIT Detected N BIT Lcatin time 0 TL Islatin time FIT I T I N where T L F1 = lcatin with n BIT, = number f cards in fault-islatin set, N = ttal number f cards, and T I = islatin time when FI =

112 REFERENCES AND BIBLIOGRAPHY 1. NAVMATINST , Built-In-Test (BIT) Design Guide, Naval Electrnics Labratry Center, 23 April RADC-TR , A Design Guide fr Built-In-Test (BIT), Rme Air Develpment Center, Air Frce Systems Cmmand, April Acquisitin Planning Guide fr Autmatic Testing Applicatins 4. Industry/Jint Services Autmatic Test Cnference and Wrkshp n Advanced Test Technlgy Management Acquisitin Supprt, April 3-7, Wiltn P. Chase, Management f System Engineering, Jhn Wiley and Sns,

113 APPENDIX A ENGINEERING DESIGN HANDBOOKS Dcument N. Handbk (Used by DDC N and NTIS) Title 100 AD **Design Guidance fr Prducibility IO1 ADA Army Weapn systems Analysis, Part One 102t 103t *Army Weapn Systems Analysis, Part Tw *Selected Tpics in Experimental Statistics With Army Applicatins 104 AD Value Engineering 106 AD Elements f Armament Engineering, Part One, Surces f Energy 107 AD Elements f Armament Engineering, Part Tw, Ballistics 108 AD Elements f Armament Lngineering, Part Three, Weapn Systems and Cmpnents 109 AD Tables f the Cumulative Binmial Prbabilities 110 AD Experimental Statistics, Sectin 1, Base Cncepts and Analysis f Measurement Data ill AD Experimental Statistics, Sectin 2, Analysis f Enumerative and Classificatry Data 112 AD Experimental Statistics, Sectin 3, Planning and Analysis f Cmparative Experiments 113 AD Experimental Statistics, Sectin 4, Special Tpics 114 AD Experimental Statistics, Sectin 5, Tables 115 AD Envirnmental Series, Part One, Basic Envirnmental Cncepts 116 ADA Envirnmental Series, Part Tw, Natural Envirnmental Factrs 108

114 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 117 ADA Envirnmental Series, Part Three, Induced Envirnmental Factrs 118 ADA-Ol5 179 Envirnmental Series, Part Fur, Life Cycle Envirnments 119 ADA Envirnmental Series, Part Five, Glssary f Envirnmental Terms 120 AD Criteria fr Envirnmental Cntrl f Mbile Systems 121 AD Packaging and Pack Engineering 123 AD Hydraulic Fluids 124 ADA Reliable Military Electrnics 125 AD **Electrical Wire and Cable 127 AD Infrared Military Systems, Part One 128(S) ADC Infrared Military Systems, Part Tw (U) 130 AD Design fr Air Transprt and Airdrp f Materiel 132 ADA Maintenance Engineering Techniques (MET) 133 ADA Maintainability Engineering Thery and Practice 134 AD **Maintainability Guide fr Design 136 AD **Servmechanisms, Sectin 1, Thery 137 AD **Servmechanisms, Sectin 2, Measurement and Signal Cnverters 138 AD Servmechanisms, Sectin 3, Amplificatin 139 AD Servmechanisms, Sectin 4, Pwer Elements and System Design 109

115 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 140 AD Trajectries, Differential Effects, and Data fr Prjectiles 150 AD Interir Ballistics f Guns 158t -- *Dynamics f Ballistic Impact, Part One 159(S)" -- *Dynamics f Ballistic Impact, Part Tw (U) 160 AD Elements f Terminal Ballistics, Part One, Kill Mechanisms and Vulnerability 161 AD Elements f Terminal Ballistics, Part Tw, Cllectin and Analysis f Data Cncerning Targets 162(SRD) AD Elements f Terminal Ballistics, Part Three, Applicatin t Missile and Space Targets (U) 163(C) t ADC Basic Target Vulnerability (U) 165 AD Liquid-Filled Prjectile Design 170(S) AD Armr and Its Applicatins (U) 175 AD Slid Prpellants, Part One 177 AD **Prperties f Explsives f Military Interest 179 AD Explsive Trains 180 AD Principles f Explsive Behavir 181 ADA Explsins in Air, Part One 182(SRD) ADC Explsins in Air, Part Tw (U) 185 AD Military Pyrtechnics, Part One, Thery and Applicatins 186 AD Military Pyrtechnics, Part Three, Prcedures and Glssary 110

116 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 187 AD Military Pyrtechnics, Part Three, Prperties f Materials Used in Pyrtechnic Cmpsitins 188 ADA-O Military Pyrtechnics, Part Fur, Design f Ammunitin fr Pyrtechnic Effects 189 AD Military Pyrtechnics, Part Five, Bibligraphy 191 AD System Analysis and Cst Effectiveness 192 AD Cmputer-Aided Design f Mechanical Systems 193k ADA Cmputer-Aided Design f Mechanical Systems, Part Tw 196 ADA Develpment Guide fr Reliability, Part Tw, Design,fr Reliability 197 ADA Develpment Guide fr Reliability, Part Three, Reliability Predictin 198 ADA Develpment Guide fr Reliability, Part Fur, Reliability Measurement 199 *Develpment Guide fr Reliability, Part Five, Cntracting fr Reliability 200 ADA Develpment Guide fr Reliability, Part Six, Mathematical Appendix and Glssary 201 ADA Helicpter Engineering, Part One, Preliminary Design 202 ADA Helicpter Engineering, Part Tw, Detail Design 203 AD **Helicpter Engineering, Part Three, Qualificatin Assurance 204 AD Helicpter Perfrmance Testing ill

117 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 205 ADA Timing Systems and Cmpnents 210 AD **Fuzes 211 AD Fuzes, Prximity, Electrical, Part One 212(S) AD Fuzes, Prximity, Electrical, Part Tw (U) 213(S) AD Fuzes, Prximity, Electrical, Part Three (U) 214(S) AD Fuzes, Prximity, Electrical, Part Fur (U) 215 AD Fuzes, Prximity, Electrical, Part Five 235 AD Hardening Weapn Systems Against RF Energy 238 ADA Recilless Rifle Weapn Systems 240(C) AD Grenades (U) 242 AD Design fr Cntrl f Prjectile Flight Characteristics 244 AD Ammunitin, Sectin 1, Artillery Ammunitin - General, with Table f Cntents, Glssary, and Index fr Series 245 AD Ammunitin, Sectin 2, Design fr Terminal Effects 247 AD Ammunitin, Sectin 4, Design fr Prjectin 248 AD Ammunitin, Sectin 5, Inspectin Aspects f Artillery Ammunitin Design 249 AD Ammunitin, Sectin 6, Manufacture f 250 AD Guns - General 251 AD Muzzle Devices 252 AD **Gun Tubes Metallic Cmpnents f Artillery Ammunitin 112

118 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DOC N and NTIS) Title 253 t -- *Breech Mechanism Design 255 AD Spectral Characteristics f Muzzle Flash 260 AD Autmatic Weapns *Mrtar Weapn Systems 270 ADA Prpellant Actuated Devices 280 AD **Design f Aerdynamically Stabilized Free Rckets 281(SRD) AD Weapn System Effectiveness (U) 283 AD Aerdynamics 284 AD Traj ectri es 285 AD Elements f Aircraft and Missile Prpulsin 286 AD Structures 290 AD Warheads - General 298' -- *Rcket and Missile Cntainer Engineering Guide 300 AD ***Fabric Design (Limited Dcument) 312 ADA Rtatinal Mlding f Plastic Pwders 313 ADA Shrt Fiber Plastic Base Cmpsites 314+ *Discntinuus Glass Fiber Reinfrced Plastics 315t *Dielectric Embedding f Electrical r Electrnic Cmpnents *Jining f Advanced Cmpsites 317t -- *Fabricatin f Cntinuus Fiber Reinfrced Plastics 113

119 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 318&- *Materials Engineering fr Plastic Prduct Design 319 *Designing fr NDT Inspectin Techniques fr Structural Cmpsites 327 AD Fire Cntrl Systems - General 329 AD Fire Cntrl Cmputing Systems 331 AD Cmpensating Elements 340 AD Carriages and Munts - General 341 AD Cradles 342 AD **Recil Systems 343 AD Tp Carriages 344 AD Bttm Carriages 345 ADA Equilibratrs 346 AD Elevating Mechanisms 347 AD Traversing Mechanisms 348' -- Design f Twed Artillery Weapn Systems 350 AD Wheeled Amphibians 355 AD The Autmtive Assembly 356 AD Autmtive Suspensins 357 AD Autmtive Bdies and Hulls 358 t ADA Analysis and Design f Autmtive Brake Systems 360 AD Military Vehicle Electrical Systems 114 * -- -

120 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) Dcument N. Handbk (Used by DDC N and NTIS) Title 361 ADA Military Vehicle Pwer Plant Cling 410t ADA Electrmagnetic Cmpatibility (EMC) 411(S) ADC Vulnerability f Cmmunicatin-Electrnic and Electr-Optical Systems (Except Guided Missiles) t Electrnic Warfare, Part One, Intrductin and General Apprach t Electrnic Warfare Vulnerability (U) 412(C) ADC Part Tw, Electrnic Warfare Vulnerability f Tactical Cmmunicatins (U) 413(S) ADC Part Three, Electrnic Warfare Vulnerability f Grund Based and Airbrne Surveillance and Target Acquisitin Radars (U) 414(S) ADC-0O8 830 Part Fur, Electrnic Warfare Vulnerability f Avinics (U) 415(S) ADC-0O8 831 Part Five, Optical/Electrnic Warfare Vulnerability f Electr-Optic Systems (U) 416(S) ADC Part Six, Electrnic Warfare Vulnerability f Satellite Cmmunicatins (U) 417(S) Vulnerability f Guided Missile Systems t Electrnic Warfare (U) 445 AD Sabt Technlgy Engineering 4 70t ADA Metric Cnversin Guide 475t *Quality Engineering 480' *Safety Engineering Design Guide fr Army Materiel *UNDER PREPARATION - NOT AVAILABLE ***LI4ITED DOCUMENTS ARE NlOT FOR SALE **REVISION UNDER PREPARATION BY NTIS tdarcom-p

121 APPENDIX A ENGINEERING DESIGN HANDBOOKS (Cnt'd) These Handbks are available t Department f the Army activities by submitting an fficial requisitin frm (DA Frm 17, 17 Jan 70) directly t the Cmmander, Letterkenny Army Dept, ATTN: SDSLE-AJD, Chambersburg, PA "Need t Knw" justificatin must accmpany request fr classified Handbks. Requestrs - DOD, Navy, Air Frce, Marine Crps, nnmilitary Gvernment agencies, cntractrs, private industry, individuals, universities, and thers - wh are registered with the Defense Dcumentatin Center (DDC) and have a Natinal Technical Infrmatin Service (NTIS) depsit accunt may btain these Handbks frm the DDC. T btain classified dcuments frm the DDC, "Need t Knw" must be established by the submissin f DD Frm 1540, 1 Jul 71. Requestrs, nt part f the Department f the Army nr registered with the DDC, may purchase unclassified Handbks frm the Natinal Technical Infrmatin Service, Department f Cmmerce, Springfield, VA All Handbks carry the prefix AMCP 706- unless therwise indicated. 116 'I

122 DISTRIBUTION LIST N. f Cpies DRSMI-R, Dr. McCrkle 1 DRSMI-RPR 3 DRSMI-RPT (Recrd Cpy) 1 (Reference Cpy) 1 DRSMI-LP, Mr. Vigt 1 Defense Technical Infrmatin Center 12 Camern Statin Alexandria, VA lit Research Institute 1 ATTN: GACIAC 10 West 35th Street Chicag, IL U.S. Army Materiel Systems 1 Analysis Activity ATTN: DRXSY-MP Aberdeen Prving Grund, MD DRSMI-RLD 20 DRSMI-XA 1 DRSMI-RGG DRSMI-CF 1 DRSMI-HD 1 DRSMI-PE 1 DRSMI-DT 1 DRSMI-RS 1 DRSMI-ROL 1 DRSMI-VI 1 DRSMI-HA 1 DRSMI-LC 1 DRSMI-MP 1 Sperry Systems Management Church Street Huntsville, AL ATTN: R. L. Heifner I 117

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