OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard

Transcription

1 Reprin from Proceedings 7h IEEE/SIGDA Grea Lakes Symposium on VLSI, GLS-VLSI 1997 Urbana-Champaign, Illinois, U.S.A., March 15 17, 1997 : Objecoriened Logicsimulaion Implemening he VITAL Sandard Josef Fleischmann, Rolf Schlagenhaf, Marin Peller, and Norber Fröhlich Insiue of Elecronic Design Auomaion Technical Universiy of Munich D Munich, Germany Absrac In a VHDL-based design flow for applicaion specific inegraed circuis, VITAL provides a uniform mehodology for developing ASIC libraries for signoff simulaion. The VITAL Sandard includes specialized rouines for describing behavior and iming of ASIC cells and inegraes backannoaion via Sandard Delay Forma (SDF). One of he key issues of he VITAL iniiaive was o accelerae simulaion performance a gae level by allowing only a resriced se of VHDL. In his paper, we presen an efficien implemenaion of he VITAL-Sandard in our objecoriened, even-driven logic simulaion ool. Firs promising resuls concerning simulaion performance compared o convenional VHDL-Simulaors are given. 1 Inroducion The specificaion and design of digial sysems is coninously moving owards higher levels of absracion. This is due o he increasing availabiliy of auomaed or semiauomaed EDA-ools and he growing accepance of hardware descripion languages like VHDL or Verilog. Neverheless, iming simulaion of he final nelis a logic level is sill an imperaive sep in he ASIC design cycle before sign-off. In he pas, here has been no uniform mehodology for sign-off simulaion based on VHDL. This was due o several facors: As a maer of fac, here has been no indusryacceped mehodology for modeling asic cells in VHDL. The iming model provided by VHDL was no accurae enough for sign-off. Simulaion performance a gae level was oo low compared o dedicaed logic simulaion engines. Because of he lack of ASIC libraries, designers using VHDL had o swich o Verilog or use specialized gae level simulaors for sign-off simulaion. During he VITAL Iniiaive (VHDL Iniiaive Towards Asic Libraries), major semiconducor suppliers and EDA ool vendors worked ogeher on he VITAL model developmen specificaion [IEE96] which has been adoped by he IEEE (IEEE ) in December The goal of his sandard is o provide a uniform and efficien modeling syle wih sufficien iming accuracy for sign-off simulaion based on VHDL. While enabling a uniform mehodology for developing ASIC libraries, he focus was also on significanly improving simulaion performance a logic level. Since is sandardizaion, he VITAL concep has been inegraed ino numerous commercial VHDL simulaion ools. The VITAL package can be used wih any VHDL simulaor, as i is enirely wrien in VHDL. Bu for improving performance of he simulaion, he simulaion kernel iself has o be modified in order o ake advanage of he VITAL resricions. The poenial for faser simulaion sems from he fac ha only well defined iming procedures have o be used when describing an ASIC cell and he possible modules for calculaing delays and checking for iming violaions have o appear in a sricly defined order. Our approach for improving simulaion performance a gae level differs from he VHDL simulaor vendors approach, as we do no sar from a fully-fledged VHDL simulaion sysem and ry o accelerae he VITAL subse for he simulaion of neliss. The developmen of (Objecoriened Logicsimulaion Implemening he VITAL Sandard) was raher based on he dedicaed logic level simulaion ools LDSIM [KA90, Kro89] and OSIM [Sch93]. The paper is organized as follows: In secion 2, we give a shor inroducion ino he VITAL Modeling Specificaion for hose who are no ye familiar wih his new sandard. In secion 3 we highligh some deails abou he implemenaion of he new objecoriened logic simulaion ool. Firs resuls from simulaed benchmark circuis and a performance comparison o a commercial VHDL/VITAL simulaor are shown in secion 4. In he final secion, some 51

2 concluding remarks and an overview of our fuure work is presened. 2 VITAL Modeling Syle Wihin a VHDL-based design flow, he VITAL Sandard esablishes a uniform forma for he descripion of library cells for iming verificaion. In more deail, he following aspecs are covered by he VITAL concep: Model developmen guidelines for ASIC cells and resricion of he applicable se of VHDL Timing rouines for defining emporal behavior and iming checks for deecing and conrolling iming violaions Primiives for modeling funcionaliy of cells Sandardized generic parameers for backannoaion of layou dependen delay parameers via SDF (Sandard Delay Forma) Cell Inpu Pors Delay Block Negaive Consrain Block VITAL Level 0 Eniy: Timing Generics VITAL Level 1 Archiecure: VITAL Process Sensiviy Lis Timing Check Secion Funcionaliy Secion Pah Delay Secion VITAL Primiive Concurren Proc. Call Cell Oupu Pors In Figure 1 an overview is given of he building blocks of a VITAL library cell and he order in which hey have o be specified. There are wo levels of modeling in VI- TAL (a uorial inroducion o VITAL can be found in [Lev95, Sch95]): VITAL level 0 rules are resriced o he eniy inerface and hese rules include a fixed variable naming convenion for iming generics in order o enable SDF backannoaion. VITAL level 1 guidelines apply o he archiecure of he model: Here i is possible o model wire delays, negaive consrains, iming checks, funcionaliy and individual pah delays in he depiced order using he procedures and funcions from he VITAL package. The se of applicable VITAL iming modules and he logical order in which hey have o be specified is sricly defined. This fac can be exploied for a more efficien implemenaion for he sake of speeding up gae level simulaion. 3 Implemenaion As a saring poin for he new implemenaion, he objec-oriened simulaion ool OSIM [Sch93] was used. OSIM conains classes for implemening an even-driven simulaor: Evens, even queue adminisraion, boolean primiives, signal models, inpu and oupu modules. I is based on a specific logic modeling specificaion originally presened in [Kro89]. During he developmen of OSIM, one requiremen was o decouple he simulaion kernel from he model of he circui o be simulaed. This was done by using a sric objecoriened approach, hus faciliaing laer reuse of he simulaion kernel for various applicaions. Wihin he even-driven logic simulaor, here are hree main groups of objecs which are insaniaed during he simulaion: Objecs, which represen he circui o be simulaed Even objecs, which propagae informaion during he simulaion run Objecs, which implemen he simulaion cycle Due o he objec-orienaion of OSIM i was possible o implemen in a relaively shor period of ime. A more deailed descripion of he differen logic modeling syles in OSIM and VITAL and implemenaional deails are given in [Pel96]. OSIM and are very good examples for sofware reusabiliy and code readabiliy when sricly adhering o an objec-oriened programming paradigm. Objecs for Represenaion of he Circui Figure 1. Srucure of a VITAL-Model [IEE96] During simulaion, he circui is represened by a number of various communicaing simulaion objecs. These 52

3 A C B QA NOT_C QB Figure 2. Example circui F 1 Q objecs. This way, componen evaluaions are riggered by preceeding circui elemens and daa is exchanged. Thus, here is quie a similariy beween he naural signal flow in a circui and is realizaion in he simulaor. There are special objecs which represen iming relaed behavior of he circui. They can generae evens, which are scheduled by he even adminisraion and execued by he SimObj iself laer. By he daa hiding mechanism of he objec-orienaion paradigm, he funcion of a componen is oally hidden wihin iself. Therefore, he objecs can have very differen funcions wihou muual inerference. In for example, here exis componens for wire delays (SimDel), gaes (e.g. SimPrimAND) and sae ables (SimPrimSaeTable) besides ohers. Differen asks are realized wihin he componens, for example seup and hold ime check (VialSeupHoldCheck) and appropriae selecion of pah delays (VialPahDelay01). Figures 2 and 3 show, how a circui is represened by a se of objecs wihin he simulaor. Each recangle is an insance of a SimObj. Besides he already menioned componens for wire delays and gaes, objecs for simulaion of primary inpu signals, recording of signals and fanou represenaion are depiced. Even Objecs F primary in SimInDig signal recorder SimRecDig fanou SimDis 1 wire delay SimDel nand SimPrimNAND inverer SimPrimINV Figure 3. Inernal Represenaion in he Simulaor are dynamically creaed and conneced o each oher a he beginning of a simulaion run. Unforunaely, he classes for circui represenaion of OSIM could no be used for, because he elemen and signal modeling of OSIM and VITAL differ. Neverheless, several base classes could be used as a saring poin for refinemens, hus reducing he required ime for developing he new ool. All componens of he circui model are insances of differen classes derived from he uppermos base class SimObj. Therefore, hey can all be muually conneced corresponding o he circui nelis. By hese connecions, signal changes can be propagaed o succeeding Corresponding o he discree even simulaion paradigm, each non-immediae signal change wihin he circui mus be coded in an even objec. They are all dynamically generaed during he simulaion run, hen execued and finally deleed. Due o he significanly differen signal modeling concep in VITAL, new even classes became necessary. They were implemened by inheriance from exising base classes for evens. Therefore i was possible o reuse big pars of he complex even adminisraion of OSIM for. Concerning even handling here is a difference beween and oher VHDL simulaors: The normal preempion mechanism of VHDL is subsiued by an alernaive which is more suiable for fuure parallelizaion of he simulaor. In, invalidaed evens are no preemped immediaely when he mos recen even is insered in he even adminisraion. Insead, hey are deleed jus before heir originally scheduled execuion. Normal preempion would desroy he lookahead [LL90] of he simulaion model, which is a basic condiion for he parallizaion mehod TIME WARP [Jef85]. The alernaive mehod realized in keeps he lookahead, bu does no have any impac on he simulaion oupu. In order o implemen his mehod, he normal VHDL even had o be exended by wo values: Generaion ick of he even Gen 53

4 even ype (INERTIAL or TRANSPORT) The disincion beween INERTIAL and TRANSPORT evens is necessary only for special siuaions during glich deecion. Normally, a componen generaes eiher one or he oher ype of evens during he whole simulaion run corresponding o is VITAL descripion. Gen is he more imporan value for correc even handling. The opology componen, which creaes an even, has a ick couner. I is increased a every VHDL dela cycle. When generaing a new even, he opology componen ses Gen of he new even o he same value as is own ick couner. This value is used laer when he even is scheduled. Then we decide wheher his even is sill valid and mus be execued or if i has o be ignored because of causaliy reasons. The decision is done by comparing he even ick wih a second reference ick RefExe wihin he opology objec. If he even is valid and execued, RefExe is se o he ick value of he even. value: Gen: A H L Ref Exe: value: Gen: B H L Ref Exe: T RANSP ORT BUFFER TRise = 10 TF all = 5 H 5 L L 7 H 5 Gen < Ref Exe ev en ignored Figure 4. Even Cancellaion Figure 4 shows an example using a simple buffer wih he delays T Rise = 10 and T F all = 5. In case A he even ordering ( 1, 0 ) during generaion and execuion is he same and no preempion or correcion is necessary. In case B, he even ordering changes. In VHDL even 1 is deleed by preempion, when even 0 is generaed. In our approach, even 1 is cancelled jus before is execuion, because Gen of he even is smaller han RefExe of he buffer objec. Objecs Implemening he Simulaion Cycle Addiionally, here are some objecs which implemen he simulaion cycle iself. The mos imporan ones o menion are he objec which builds and manages he circui opology, and he objec for even adminisraion (even queue). There is only one insaniaion of each of hese objecs and heir lifeime lass over he whole simulaion run. This se of objecs represens he basic funcionaliy of he simulaor kernel. Alhough a slighly differen simulaion cycle had o be implemened for simulaing VHDL, sofware reuse of major pars formerly used in OSIM was possible. 4 Resuls In order o verify he correc funcionaliy of he new simulaor and o be able o compare is performance o commercial VHDL simulaion sysems, we simulaed differen benchmark circuis. For his purpose, we used hree combinaional circuis from he LGSYNTH91 [Yan91] benchmark se (C17, ALU2 and C6288) and a locally developed sequenial circui (ADD4). All simulaion experimens described in his secion were conduced on a single-processor DEC ALPHA 250 4/266 running DIGI- TAL UNIX V3.2. Our simulaor was compiled wih GNU G++ and all experimens wih commercial simulaors were done in compiled mode. An overview of he experimenal simulaion environmen is shown in Figure 5. The VHDL circui nelis is read by a VHDL reader, which has been developed using he GNU BISON and FLEX ools. The reader convers he circui descripion ino an inermediae direced graph conaining signal and componen nodes. This inermediae graph srucure is used by o build all necessary simulaion objecs as shown for he small example in Figure 3. For generaing simuli, we used a simple program for generaing random vecors. A primiive backend is employed for processing he oupufile produced by and visualize he simulaion resuls. A graphical user inerface has no been implemened ye. During simulaion we applied randomly generaed es vecors o he circui inpus. In each experimen, we raced a se of inernal signals and all oupu signals and we go he same simulaion resuls on and he commercial VHDL/VITAL simulaor. The performance figures shown in Figure 6 and 7 are mean execuion imes obained by five independen simulaion runs. The measured cpu ime in experimens wih include he ime for parsing he VHDL circui descripion and he ranslaion o an inermediae graph, he ime o read he simuli file, he ime for circui simulaion and for wriing he race file. 54

5 STIMULI GENERATOR CPU Time [sec] VITAL NETLIST VHDL READER STIMULI FILE INTERMEDIATE GRAPH SIMULATOR ALU2: CPU Time on Decalpha: Tool A Speedup TRACE FILE 200 VISUALIZATION Figure 5. Experimenal Simulaion Environmen Firs, we did some invesigaions on he relaion beween simulaion runime and number of inpu vecors. In Figure 6 i can be seen, ha for our example ALU2 here is a near linear correlaion beween execuion ime and number of vecors for boh he commercial ool and. In our experimens we observed ha he nonlinear endency increases wih he size of he circui and he number of es vecors. This effec may mos likely resul from sideeffecs like he large size (> 20 Mb) of he simulaion oupu files. In Figure 6 you can also see he significan difference in performance beween our new simulaion ool and he commercial sae-of-he-ar simulaor TOOL A 1 : When simulaing he combinaional circui ALU2 we experienced an increase in simulaion speed by a facor beween five and seven depending on he number of inpu vecors. An overview of our firs performance resuls wih he benchmarks simulaed up o now is depiced in Figure 7: We obained a really significan speedup for all circuis simulaed ye. Even more ineresing is, ha he speedup obained by seems o increase wih larger circui sizes and larger ses of inpu vecors. For a more deailed performance invesigaion we are now working on simulaing more and larger benchmark circuis. Furhermore, we are currenly conducing experimens wih oher commercial VITAL opimized simulaors. Our preliminary resuls indicae ha simulaion ool ouperforms TOOL B which is said o be one of he fases VHDL/VITAL simulaors a he momen by a facor beween wo and hree. 1 For reasons of license agreemens, we do no expliciely name any of he employed commercial simulaion ools in his paper Inpu evens Figure 6. Simulaion Runimes for Differen Ses of Inpu Vecors 5 Conclusion and Fuure Work In his paper we presened a new objecoriened evendriven simulaion ool for iming simulaion a gae level implemening he VITAL Sandard. The ool is currenly under developmen and was originally designed o be used in a VLSI design course. Therefore, is no ye capable of parsing an arbirary library of VITAL simulaion models, bu i works on a resriced design library consising of a number of combinaional and sequenial primiives. Alhough here has been no fine-uning of he code for performance ye, he simulaion ool shows significan speedups compared o convenional VHDL simulaion ools a logic level while producing he same simulaion resuls. The focus of curren and fuure work is on he following opics: Furher performance evaluaion and comparison o commercial VITAL opimized simulaors while simulaing larger benchmark circuis 55

6 Rel. Simulaion Runime (CPU-Time) TOOL A [IEE96] IEEE Sandards Board. IEEE Sandard for VITAL Applicaion-Specific Inegraed Circui (ASIC) Modeling Specificaion, IEEE % [Jef85] D. R. Jefferson. Virual Time. ACM Transacions on Programming Languages and Sysems, 7(3): , % 50 % [KA90] H. T. Krodel and K. J. Anreich. An Accurae Model for Ambiguiy Delay Simulaion. In European Conference on Design Auomaion (EDAC), pages , Glasgow, % 5.6s 12.8s 54.1s 304.5s [Kro89] Hans Thomas Krodel. Verfahren zur Logiksimulaion komplexer digialer Schalungen mi flexibler Modellierung. PhD hesis, Insiue of Elecronic Design Auomaion, Technical Universiy of Munich, C ADD ALU C Circui Gaes+FFs Figure 7. Normalized Simulaion Execuion Times [Lev95] [LL90] Oz Levia. Inroducion o ASIC Cells Modeling wih VITAL. In VHDL Forum for CAD in Europe, April Tuorial. Yi-Bing Lin and Edward D. Lazowska. Exploiing Lookahead in Parallel Simulaion. IEEE Transacions on Parallel and Disribued Sysems, 1(4): , Enhance capabiliies of he fronend VHDL reader in order o be able o process hierarchical srucural VHDL designs Implemenaion of a mechanism for backannoaion of layou dependen delay informaion via SDF During he concepualizaion and implemenaion phase of special emphasis has been laid on he abiliy o por he simulaor o a parallel environmen laer. There are already plans for a parallel VITAL simulaor operaing on a worksaion cluser. This endeavor will be guided by our experience in parallel gae level simulaion [SRSB95, FW95] References [FW95] [IEE94] Josef Fleischmann and Philip A. Wilsey. Comparaive Analysis of Periodic Sae Saving Techniques in Time Warp Simulaors. In ACM/SCS/IEEE Workshop on Parallel and Disribued Simulaion (PADS), pages 50 58, Lake Placid, New York, June IEEE Sandards Board. VHDL Language Reference Manual, ANSI/IEEE [Pel96] Marin Peller. Logiksimulaion mi VITAL. Maser s hesis, Insiue of Elecronic Design Auomaion, Technical Universiy of Munich, [Sch93] Rolf Schlagenhaf. Objekorienierer Simulaor für Logikschalungen. Maser s hesis, Insiue of Elecronic Design Auomaion, Technical Universiy of Munich, [Sch95] Seven E. Schulz. Inroducion o VITAL 95. In Menor User s Group Meeing, Tuorial Presenaion. [SRSB95] Rolf Schlagenhaf, Marin K. Ruhwandl, Chrisian Sporrer, and Herber Bauer. Dynamic Load Balancing of a Muli-Cluser Simulaor on a Nework of Worksaions. In ACM/SCS/IEEE Workshop on Parallel and Disribued Simulaion (PADS), pages , Lake Placid, New York, June [Yan91] Saeyang Yang. Logic Synhesis and Opimizaion Benchmarks User Guide, Version 3.0. MCNC, Research Triangle Park, N.C ,