GaN Transistors for Efficient Power Conversion

Transcription

1 GaN Transistors for Efficient Power Conversion Alex Lidow and David Reusch Efficient Power Conversion 1

2 Agenda How GaN works and the state-of-theart Design Basics Design Examples What is in the future? 2

3 How GaN Works and the State-of-the-Art 3

4 Power Switch Wish List Lower On-Resistance Faster Less Capacitance Smaller Lower Cost 4

5 Material Comparison 5

6 State of the Art Theoretical on-resistance vs. blocking voltage capability for silicon, silicon carbide, and gallium nitride. 6

7 GaN Switch V AlGaN GaN 7

8 Now GaN we Switch have a switch That has high voltage blocking V capability, low on resistance, and is very, very fast. AlGaN GaN Depletion Mode = Normally On 8

9 Device Construction Concept Source Gate AlGaN Protection Dielectric Drain GaN Silicon 9

10 What about Normally Off devices? 10

11 Cascode GaN Device Reference: The Status of GaN Power Device Development at International Rectifier, PCIM

12 Cascode Penalty Cascode devices combine a depletion mode GaN transistor with a low voltage enhancement mode MOSFET Drain GaN Improves Gate Si Improves Source 12

13 Enhancement Mode A positive voltage from Gate-To-Source establishes an electron gas under the gate 13

14 Body Diode? A positive voltage from Gate-To-Drain also establishes an electron gas under the gate 14

15 Cross Section of an egan FET 15

16 Electrical Characteristics 16

17 egan FET Reverse Conduction MOSFET + Q RR egan FET + Zero Q RR 17

18 Normalized On Resistance On Resistance vs. Temperature egan FET MOSFET B About 20% Difference At 125 C Junction Temperature ( C) 18

19 Normalized Thershold Voltage Threshold vs. Temperature egan FET MOSFET A Junction Temperature ( C) 19

20 egan FET Transfer Characteristics EPC

21 MOSFET Transfer Characteristics Negative temperature coefficient region of silicon MOSFET Source:

22 egan FET Safe Operating Area 1 ms 10 ms 100 ms DC

23 egan FET Safe Operating Area 1 ms 10 ms 100 ms DC

24 egan FET Capacitances C GS C DS GaN Silicon C GD 24

25 Total Gate Charge BSC057N08NS EPC2001 = 100 V, 5.6 mω typ. BSC057N08 = 80 V, 4.7 mω typ. 25

26 Switching Comparison 100 V egan FET 5.6 mω 80 V Si MOSFET 10.3 mω 10 V/ div 20 ns/ div V IN =48 V V OUT =1 V I OUT =10 A f sw =300 khz L=10 µh egan FET T/SR: 100 V EPC2001 MOSFET T/SR: 80 V BSZ123N08NS3G 26

27 R DS(on) (mω) GaN Improvements x Generation Generation x Drain-to-Source Voltage (V) V GS =5 V 27

28 FOM=Q G R DS(on) (pc Ω) Gate Charge FOM Generation x x 1.4x Generation Drain-to-Source Voltage (V)

29 FOM=Q G R DS(on) (pc Ω) Gate Charge Figure of Merit EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E x x 4.2x Drain-to-Source Voltage (V) 29

30 FOM HS =(Q GD +Q GS2 ) R DS(on) (pc Ω) Hard Switching FOM Generation x x 2.4x Generation Drain-to-Source Voltage (V) V DS =0.5 V DSS, I DS =20 A

31 FOM HS =(Q GD +Q GS2 ) R DS(on) (pc Ω) Hard Switching FOM 100 EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E Si MOSFETs 2014 GaN Transistors x x 8x GaN Transistors Drain-to-Source Voltage (V) V DS =0.5 V DSS, I DS =20 A

32 Miller Ratio Miller Ratio=Q GD /Q GS EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E 2.5x 2x 2.5x Drain-to-Source Voltage (V) V DS =0.5 V DSS, I DS =20 A 32

33 FOM SS =(Q G +Q OSS ) R DS(on) (pc Ω) Soft-Switching Figure of Merit EPC Gen 4 EPC Gen 2 Vendor A Vendor B x x 2.4x Drain-to-Source Voltage (V) V DS =0.5 V DSS 33

34 egan FET Loss Mechanisms Like A MOSFET I²R Conduction Loss Capacitive Switching Losses Gate Drive Losses V I Switching Loss Not Like A MOSFET High Reverse Conduction Loss No Body Diode Reverse Recovery Loss Can be much, much better than comparable silicon MOSFET 34

35 Package Wish List Low parasitic resistance Low parasitic inductance Low thermal resistance Small size Low cost 35

36 Flip-Chip LGA Construction egan FET Silicon Solder Bar Copper Trace Printed Circuit Board Absolute minimum lead resistance and inductance! 36

37 LGA Construction Drain Contacts Interleaving to reduce layout inductance Substrate Gate Source Contacts 37

38 Size Comparison 200 V egan FET D-PAK 5.76 mm² Drawn To Scale 65.3 mm² 38

39 Design Basics 39

40 Design Basics Agenda Requirements for: Gate Driver Dead-time Layout Paralleling Thermal Measurement 40

41 Gate Drive 41

42 Low V GS(on) Overhead V GS(Max) = 6 V 42

43 Minimizing Overshoot V GS egan FET 2 V/ div 80 ns/ div 43

44 egan FET Drive Requirements To avoid overshoot: R G = R G(INT) + R G(EXT) R G 4( L L G C GS S ) R G(INT) R G(EXT) L G C GS L S Minimize gate loop inductance Separate source and sink transistors allowing for separate drive paths 44

45 Minimizing Overshoot V GS egan FET V GS egan FET 1 V/ div 20 ns/ div 45

46 egan FET Driver IC Bootstrap clamp limits (HS) supply Separate inputs allow accurate, dead-time management Optimized drive impedance Reference: Texas Instruments, Gate Drivers for Enhancement Mode GaN Power FETs 100 V Half-Bridge and Low-Side Drivers Enable Greater Efficiency, Power Density, and Simplicity, SNVB

47 Dead-time Requirements 47

48 Reverse Conduction Period V V SW C in T SR V SW V GS_T V GS_SR T Dead t 48

49 egan FET Reverse Conduction MOSFET + Q RR egan FET + Zero Q RR 49

50 Reverse Conduction Period V V SW C in T SR V SW V GS_T V GS_SR T Dead t 50

51 Dead-time Loss (W) Impact of Dead-time egan FET Si MOSFET w/o Q RR 0.2 egan FET w/schottky Dead-Time (ns) V IN =12 V, V OUT =1.2 V, I OUT =20 A, and f sw =1 MHz 51

52 Efficiency (%) Impact of Dead-time Si MOSFET T DEAD 2.5 ns egan FET T DEAD 2.5 ns egan FET T DEAD 5 ns egan FET T DEAD 10 ns w/o Schottky w/ Schottky Output Current (A) V IN =12 V, V OUT =1.2 V, and f sw =1 MHz 52

53 Fixed Dead-time Implementation Single PWM input Buffer RCD filters delay turn-on, but not turn-off Dead-time Inverter To LM5113 High side input To LM5113 Low side input Used on all EPC90XX boards 53

54 Layout 54

55 Ideal Hard Switching V IN I OFF t VR Q GD I DS t CF Q GS2 V DS V GS V PL V TH P tvr V IN I OFF Q GD 2 I G P tcf V IN I OFF Q GS2 2 I G t 55

56 FOM = (Q GD +Q GS2 )*R DSON (pc*ω) 100 V Device Comparison V egan FETs 100 V MOSFETs Q GS2 Q GS Q GS Q GS2 Q GD Q GD Q GD 10 Q GD Q GS V egan FET Gen2 Q GD 100 V egan FET Gen V MOSFET V MOSFET V MOSFET 3 V DS =0.5*V DS, I DS = 10 A 56

57 Power Loss(W) Converter Parasitics C in T SR L S : Common Source Inductance L Loop : High Frequency Power Loop Inductance Power Loss vs Parasitic Inductance Ls L Loop Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, f sw =1 MHz, I OUT = 20 A 57

58 Power Loss (W) Efficiency (%) Package Impact on Efficiency Drain Gate Source SO-8 LFPAK DirectFET Device Loss Breakdown 90 82% 18% Package Die 73% 27% 47% 53% V IN =12V V OUT =1.2V I OUT =20A f sw =1MHz 18% 82% SO-8 LFPAK DirectFET LGA LGA egan LGA FET SO-8 LFPAK DirectFET LGA Switching Frequency (MHz) 58

59 Efficiency (%) Layout Impact on Efficiency Measured Efficiency L Loop 0.4nH L Loop 1.0nH L Loop 1.7nH L Loop 40 V egan FET 2.2nH 40 V MOSFET Output Current (A) EPC Optimal Layout Ref: D. Reusch, J. Strydom, Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium Nitride Based Point of Load Converter, APEC 2013 V IN =12 V, V OUT =1.2 V, f sw =1 MHz, L=300 nh 59

60 Layout Impact on Peak Voltage L Loop 1.0 nh L Loop 0.4 nh 70% Overshoot 30% Overshoot Switching Node Voltage V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=150 nh 60

61 Conventional Lateral Layout Top View Side View Shield Layer 61

62 Conventional Vertical Layout Top View Side View Bottom View 62

63 EPC Optimal Layout Top View Side View Top View Inner Layer

64 Optimal Layout Implementation C IN C IN U 2 U 2 Q 1 Q 1 Q 2 Q

65 Layout Inductance Comparison Top View Test Cases Board Thickness (mils) Inner Layer Distance (mils) Design Design Design Design

66 Power Loss (W) Power Loss Comparison High Frequency Loop Inductance (nh) V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 Lateral Power Loop Optimal Power Loop Vertical Power Loop 66

67 Efficiency (%) Efficiency Comparison V MOSFET Vertical Design 1 40 V egan FET Optimal Design 1 Vertical Design 1 Lateral Design Output Current (A) V IN =12 V V OUT =1.2 V f sw =1 MHz L=300 nh GaN T/SR: EPC2015 Driver LM

68 Voltage Overshoot (%) Voltage Overshoot Comparison Lateral Power Loop Vertical Power Loop Optimal Power Loop High Frequency Loop Inductance (nh) V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=300 nh T/SR: EPC2015 Driver LM

69 egan FET dv/dt (V/ns) Switching Speed Comparison High Frequency Loop Inductance (nh) V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 Optimal Power Loop Lateral Power Loop Vertical Power Loop 69

70 egan FET vs. MOSFET Si MOSFET egan FET 3 V/ div 20 ns/ div V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=300 nh egan FET T/SR: EPC2015 MOSFET T:BSZ097N04 SR:BSZ040N

71 FOM=(Q GD +Q GS2 )*R DSON (pc*ω) Lower Voltage Comparison V MOSFETs Q GS2 Q GS V egan FET Q GS2 Q GD 30 V egan FET Q GS2 Q GD Q GD 25 V MOSFETs Q GS2 Q GS2 Q GD Q GD 0 40V egan FET Gen 2 Q GD 30V egan FET Gen 4 40 V MOSFET 1 40 V MOSFET 2 25V MOSFET 1 25V MOSFET

72 Efficiency (%) Lower Voltage Comparison V Discrete egan FET 40 V Discrete MOSFET 25 V Discrete MOSFET 30 V Module MOSFET Output Current (A) V IN =12 V V OUT =1.2 V f sw =1 MHz L=300 nh 72

73 Switching Comparison 40 V egan FET 30 V Si MOSFET Module 40 V Si MOSFET Switch Node Voltage 3 V/Div 20 ns/ div V IN =12 V V OUT =1.2 V I OUT =20 A f sw =1 MHz L=300 nh 73

74 EPC9107 Demonstration Board V IN =12-28 V V OUT =3.3 V I OUT =15 A f sw =1 MHz 2 x EPC2015 ~3V 15 A OUT V IN =28 V Switching Node Voltage V IN =28 V, I OUT =15 A ~1.1ns rise 15 A 20ns 5 V/ div 74

75 Efficiency (%) Higher Current Devices V MOSFET Module EPC EPC2015 EPC EPC Output Current (A) V IN =12 V V OUT =1.2 V f sw =0.5 MHz f sw =1 MHz 75

76 Power Loss (W) Higher Current Devices V MOSFET Module EPC EPC Output Current (A) V IN =12 V V OUT =1.2 V EPC EPC2023 f sw =0.5 MHz f sw =1 MHz 76

77 Paralleling High-Speed egan FETs 77

78 Parallel Power Devices? 78

79 Unbalanced Loop Inductance Q GS2 Q GD I DS1 I DS V DS I DS2 V GS2 V GS V DS2 V GS1 V TH V DS1 t 79

80 Current Difference (%) Loop Inductance Impact L S =0.10nH L S =0.15nH L S =0.20nH L S =0.25nH L S =0.50nH Loop Inductance Difference (nh) V IN =48 V I OUT =25 A egan FET T/SR: 100 V EPC

81 Single Loop Optimal Layout SR 4 SR 1 T 1-4 SR 1 SR 4 10 V/ div 5 ns/ div V IN =48 V V OUT =12 V I OUT =30 A f sw =300 khz L=3.3 µh GaN FET T/SR: 100 V EPC

82 Parallel Loop Optimal Layout T 1 T 3 SR 1 SR 3 SR 4 SR 4 SR 2 SR 4 T 2 T 4 SR 1 10 V/ div 5 ns/ div V IN =48 V V OUT =12 V I OUT =30 A f sw =300 khz L=3.3 µh GaN FET T/SR: 100 V EPC

83 Efficiency (%) Parallel Layout Performance ǁ egan FETs Proposed Four Distributed Power Loops Design Output Current (A) Conventional Single Power Loop Design V IN =48 V V OUT =12 V f sw =300 khz L=3.3 µh GaN FET T/SR: 4x100 V EPC Layer 2 oz PCB 83

84 Parallel Layout Implementation T 1 SR 1 T 3 SR 3 T 1-4 SR 1-4 SR 2 SR 4 T 2 T 4 V IN =48 V V OUT =12 V I OUT =30 A f sw =300 khz L=3.3 µh GaN FET T/SR: 100 V EPC

85 Maximum Temperature ( C) Parallel Layout Performance Proposed Four Distributed Power Loops Design Output Current (A) Conventional Single Power Loop Design V IN =48 V V OUT =12 V f sw =300 khz L=3.3 µh GaN FET T/SR: 100 V EPC2001 Fan Speed 200 LFM 4 Layer 2 oz PCB 85

86 Parallel egan FET Swithcing 1x egan FET 2x egan FET 4x egan FET 10 V/ div 5 ns/ div V IN =48 V V OUT =12 V I OUT =30 A/ number of devices f sw =300 khz GaN FET T/SR: 100 V EPC

87 Efficiency (%) Parallel Buck in IBC Applications kHz EPC EPC kHz EPC ǁ EPC khz Si Isolated IBC 245 khz Si Isolated IBC Output Current (A) 14 W V IN =48 V V OUT =12 V Fully Regulated IBC 87

88 Efficiency (%) Higher Current Devices V EPC Gen 2 80 V EPC Gen V MOSFET f sw =300 khz f sw =500 khz Output Current (A) V IN =48 V V OUT =12 V 88

89 Power Loss (W) Higher Current Devices V MOSFET EPC EPC2001 EPC EPC Output Current (A) f sw =300 khz f sw =500 khz V IN =48 V V OUT =12 V 89

90 Improved Thermal Performance Fan Speed=200 LFM f sw =300 khz V IN =48 V V OUT =12 V I OUT =30 A 90

91 Thermal 91

92 Thermal Management Silicon Substrate Active GaN Device Region R ƟCA R ƟJC T J R ƟJB R ƟBA 92

93 Packaging Advancements Single Sided Cooling Double Sided Cooling Double Sided Cooling R ƟJB << R ƟJC R ƟJB R ƟJC R ƟJB R ƟJC 93

94 R ƟJB, Thermal Resistance ( C/W) Package Comparisons R θjb_si R θjb_gan Device Area (mm 2 ) 94

95 R ƟJC, Thermal Resistance ( C/W) Package Comparisons R θjc_si R θjc_gan Device Area (mm 2 ) 95

96 Efficiency (%) Performance Comparison V egan FET 40 V MOSFET Output Current (A) V IN =12 V, V OUT =1.2 V, f sw =1 MHz, L=300 nh 96

97 Thermal Comparison GaN is 38% Smaller 13% Cooler V IN =12 V, V OUT =1.2 V, I OUT =20 A, f sw =1 MHz, L=300 nh 97

98 Maximum Temperature (C) Thermal Comparison egan FET MOSFET 0 LFM 200 LFM Output Current (A) V IN =12 V, V OUT =1.2 V, f sw =1 MHz, L=300 nh 98

99 Maximum Temperature ( C) Generation 4 Thermal Performance Natural Convection Output Current (A) V IN =12 V V OUT =1.2 V 200 LFM 400 LFM f sw =1 MHz 99

100 Measurement 100

101 Voltage Measurement Do not use probe ground lead Do not let probe tip touch the low-side die! Ground probe against TP3 OR use wire ground Minimize loop Place probe tip in large via or exposed pad 101

102 Probe Options Tektronix PCB Jack Yokogawa Probe Hand-made Probe Adapter 102

103 High Speed Measurement 4GHz, 40Gsa/s oscilloscope 1GHz, 4Gsa/s oscilloscope 1GHz, 100:1, 1pF / 5k probe 500MHz, 10:1, 10pF / 10M probes 103

104 Design Basics Summary egan FETs raise the bar for power conversion performance Lower resistance per die area Better FOM s Better Packaging Improved PCB Layout Techniques Superior In-Circuit Performance Can parallel devices for higher current Avoid gate overshoot and long dead-times 104

105 Design Examples 105

106 Design Example Agenda Resonant Bus Converter Envelope Tracking Wireless Power LiDAR Class-D Audio 106

107 Resonant Bus Converter 107

108 Figure of Merit (FOM) History In 1989, Baliga derived a switching FOM BHFFOM = 1 R ON,SP C IN,SP In 1995, Kim et al proposed a new FOM NHFFOM = 1 R ON,SP C OSS,SP In 2004, Huang proposed a new FOM HDFOM = R ON,SP Q GD,SP 108

109 Resonant Bus Converter High Frequency DC/DC Transformer L K1 S 1 V GS(Q2,Q4) V GS(S2) Q 1 Q 4 4:1 I LK1 V GS(Q1,Q3) V GS(S1) D V IN + - I PRIM C O I PRIM I LM 48V Q 2 Q 3 L M V DS(Q1) t ZVS V IN L K2 I Lk1 S 2 t 0 t 1 t 2 t 3 Ref: Y. Ren, M. Xu, J. Sun, and F. C. Lee, A family of high power density unregulated bus converters, IEEE Trans. Power Electron., vol. 20, no. 5, pp , Sep

110 FOM=Q G R DS(on) (pc Ω) Gate Charge Figure of Merit EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E x x 4.2x Drain-to-Source Voltage (V) 110

111 P G = Q G V DR f s Output Charge Q OSS t ZVS I RMS P CON V t ZVS I I SW V DS t ZVS V GS t D T S t 111

112 FOM=Q OSS R DS(on) (pc Ω) Output Charge FOM EPC Gen 4 EPC Gen 2 Vendor A Vendor B 2.6x x 1.7x Drain-to-Source Voltage (V) V DS =0.5 V DSS 112

113 FOM=Q G \Q OSS R DS(on) (pc Ω) Soft-Switching FOM Q OSS x x 3.5x Q G Drain-to-Source Voltage (V) FOM SS = (Q OSS +Q G ) R DS(on) 113

114 FOM SS =(Q G +Q OSS ) R DS(on) (pc Ω) Soft-Switching FOM EPC Gen 4 EPC Gen 2 Vendor A Vendor B x x 2.4x FOM SS = (Q OSS +Q G ) R DS(on) Drain-to-Source Voltage (V) 114

115 egan FET vs. MOSFET Resonant Capacitors Secondary Devices Transformer Primary Devices Input Capacitors MOSFET vs. egan FET 115

116 ZVS Switching Comparison T ZVS = 42 ns egan FET V DS MOSFET V DS T ZVS = 87 ns MOSFET V GS egan FET V GS f sw = 1.2 MHz, V IN = 48 V, and V OUT 12 V 116

117 Duty Cycle Comparison D egan FET = 42% D MOSFET = 34% MOSFET V GS egan FET V DS egan FET V GS MOSFET V DS f sw = 1.2 MHz, V IN = 48 V, and V OUT 12 V 117

118 Efficiency (%) Power Loss (W) Efficiency Comparison MHz egan FET 1.2 MHz MOSFET 10 W 12 W 14 W MHz MOSFET 5 A MHz egan FET Output Current (A) Output Current (A) f sw = 1.2 MHz, V IN = 48 V, and V OUT 12 V 118

119 * EPC9105 Bus Converter EPC9105 Demonstration Board V IN, 12 V OUT, 350 W, 1.2 MHz L IN L K1 2 SR V IN+ C IN Q 1 Q 3 4:1 * * Q 6, Q 7 V OUT+ L OUT C RES C OUT V IN- Q 2 Q 4 L K2 2 SR Q 5, Q 8 V OUT

120 Envelope Tracking 120

121 Exabytes per Month Why Envelope Tracking? Source: Cisco VNI Mobile Data Traffic Forecast 66% Compound annual growth rate (CAGR) Same average Reference: Nujira.com website 121

122 Envelope Tracking Envelope Tracking Peak Power Fixed supply PAPR = 0dB Peak efficiency up to 65% Output Probability Average Power Output Power (dbm) 122

123 EPC8000 Series EPC8004 egan FET Gen 3 FOM EPC

124 Hard Switching FOM 124

125 Gate Return Gate Return HB Layout Top Layer Vias to next layer To BUS caps Supply Switch node Drain Sub Top Gate Source S Gate Current orthogonal to drain current Drain Sub Vias to next layer Bottom Gate Ground Source S 125

126 Gate Return Gate Return HB Layout Inner Layer 1 Optimum power loop return To gate drive Drain Sub Optimum gate loop return Source S To gate drive Drain Sub Optimum gate loop return Source S 126

127 Envelope Tracking Prototype Board Bus caps LM5113 EPC8005 EPC8005 SO-8 footprint 127

128 Efficiency High Frequency Efficiency 95% 90% 5 MHz 85% 80% 10 MHz EPC % 70% 65% Output Current (A) V IN =42 V V OUT =20 V 128

129 42V IN, 10 MHz Losses Conduction Switching C OSS Unaccounted losses EPC

130 No-Load Switching 10 MHz switching, no load, large dead-time 10V/div, 100mA/div, 10ns/div Expected commutation based on egan FET C OSS Initially slow rising edge Actual voltage commutation slopes are different, even though currents are the same 130

131 IC capacitance Bootstrap diode Level Shift Parasitic Losses Reverse recovery charge V DD V DD Switch-node rising edge LM5113 half-bridge driver 131

132 Loss Breakdown 10 MHz switching, no load, large dead-time 10V/div, 100mA/div, 10ns/div Switch-node voltage Bootstrap Q RR Actual commutation based on total C OSS including IC capacitance 132

133 42V IN, 10 MHz Losses Conduction Switching C OSS Unaccounted losses EPC

134 egan FET Limited Efficiency Calculated efficiency improvement 134

135 Wireless Power 135

136 Wireless Power The global wireless charging market is estimated to grow to $10B by 2018, a CAGR of 42.6% egan FETs enable higher efficiency and operation at safer frequencies 136

137 25mm Experimental System Setup Coil Feedback egan FETs RF connection Device Coil Device Board 50mm Source Board Source Coil RF connection 137

138 Coil Simplification Simplified representation of coil-set for easy comparison between topologies C devs L devs L src L dev C devp C out Z load Coil Set R DCload 138

139 Single Ended Class-E Switch voltage rating 3.56 Supply (V DD ). C OSS absorbed into matching network. Susceptible to load variation - high FET losses. Coil voltage V DD [V RMS ]. V DD V / I + L RFck L e C s 3.56 x V DD V DS Q 1 C sh Z load 50% I D Ideal Waveforms time 139

140 EPC2012 MOSFET Device Power [mw] FoM WPT [nc mω] SE-CE SE-CE Class-E Device Comparison FOM Gate Power dominant 1000 WPT R DS(on) Conduction Loss dominant Lowest Power Dissipation R DS(on) [mω] Q G Q GD MOSFET egan FET 140

141 Efficiency [%] Output Power [W] % 98.5 % Class-E Analysis Comparison Peak Power Device losses = 279 mw No Heat-Sink Required egan FET Eff. MOSFET Eff. egan FET Pout MOSFET Pout EPC2012 MOSFET 94.4% 85.2% DC Load Resistance [Ω]

142 ZVS Class-D Switch voltage rating = Supply (V DD ). C OSS voltage is transitioned by the ZVS tank. ZVS tank circuit does not carry load current. Coil voltage = ½ V DD [V RMS ]. + V DD V / I C s V DD Q 2 L ZVS V DS I D Q 1 C ZVS ZVS tank Z load 50% Ideal Waveforms time 142

143 EPC8009 EPC2007 MOSFET 2 MOSFET 3 FoM WPT [nc mω] V GS = 10 V Device Comparison ZVS-CD ZVS-CD FOM WPT R DS(on) Q G Q GD 143

144 Efficiency [%] 84 Coil becomes Capacitive Load Variation Results Fixed Supply Voltage Coil becomes Inductive η EPC2012 SE-CE η MOSFET 1 SE-CE η EPC8009 ZVS-CD η MOSFET 2 ZVS-CD η MOSFET 3 ZVS-CD DC Load Resistance [Ω] 144

145 LiDAR 145

146 LIght Detection And Ranging Autonomous vehicles Video games Geology Agriculture

147 LiDAR Courtesy of OmniPulse 147

148 Class-D Audio 148

149 Why egan FETs in Class-D Audio Low R DS(on) & Low C OSS + High Efficiency + High Damping Factor = Low open loop output Impedance = Low T-IMD Fast Switching & No Reverse Recovery (Q rr ) + High output linearity, Low Cross-over Distortion = Low THD 149

150 egan FET Class-D Audio Amplifier Bridge-Tied-Load (BTL) EPC2016 with LM5113 XLR Input ±30 V supply Q 1 L F1 L F2 Q 3 Q 2 C F1 C F2 Q 4 egan FET Power Stage: 250 W into 4 Ω at 440 khz without a heatsink XLR Input RCA Inputs Speaker Connections 150

151 A Look Into the Future 151

152 Breaking Down the Barriers Does it enable significant new capabilities? Is it easy to use? Is it VERY cost effective to the user? Is it reliable? 152

153 Breaking Down the Barriers Does it enable significant new capabilities? Is it easy to use? Is it VERY cost effective to the user? Is it reliable? 153

154 egan FETs are Faster Faster Transistors Faster transistors enable the systems to get smaller, more efficient, and lower cost

155 Key Applications Wireless Power Transmission RF DC-DC Envelope Tracking LiDAR RadHard Network and Server Power Supplies Point of Load Modules Energy Efficient Lighting Class D Audio Various Medical 155

156 Product Revenue Forecast 2018 Envelope Tracking 22% AC-DC 38% WiPo 18% LiDAR 6% DC-DC 9% NRE 1% Lighting 1% Audio 2% RadHard 1% MRI 2% 156

157 Breaking Down the Barriers Does it enable significant new capabilities? Is it easy to use? Is it VERY cost effective to the user? Is it reliable? 157

158 Is an egan FET Easy to Use? It s just like a MOSFET except The high frequency capability makes circuits using egan FETs sensitive to layout The lower V G(MAX) of 6 V makes it advisable to have V GS regulation in your gate drive circuitry 158

159 Educating 159

160 Universities with GaN Transistor Programs Universities all over the world are graduating well-trained engineers experienced in the use of GaN Transistors Virginia Tech University of California at Santa Barbara Rensselaer Polytechnic Institute Hong Kong University of Science and Technology Cornell University Katholieke Universiteit Leuven University of Bristol University of Glasgow University of Sheffield University of Warsaw University of Sydney Massachusetts Institute of Technology Cambridge University National Central University of Taiwan National Taiwan University Chang Gung University University of Florida Florida State University Case Western University Yale University University of Ohio, Toledo Ohio State University Kyushu Institute of Technology National Chiao Tung University University of Tennessee Auburn University University of Texas Yamaguchi University Universitat Kassel National Tsinghua University Mid Sweden University New Mexico State University University of Johannesburg University of Toronto Universita di Padova Delft University of Technology Missouri University of Science and Technology University of Maryland Insitituto Italiano di Technologia 160

161 Efficiency (%) Simplifying GaN- DrGaN PLUS DrGaN PLUS 300kHz DrGaN PLUS 500kHz 80V MOSFET 300kHz Output Current (A) V IN =48 V V OUT =12 V f sw =300 khz L=10 µh egan FET T/SR: 100 V EPC2001 MOSFET T/SR: 80 V BSZ123N08NS3G 161

162 Breaking Down the Barriers Does it enable significant new capabilities? Is it easy to use? Is it VERY cost effective to the user? Is it reliable? 162

163 Silicon vs. egan Product Costs Starting Material Epi Growth Wafer Fab Test Assembly lower higher same same lower lower ~same? lower same lower OVERALL higher lower! 163

164 Breaking Down the Barriers Does it enable significant new capabilities? Is it easy to use? Is it VERY cost effective to the user? Is it reliable? 164

165 High Temp Reverse Bias (HTRB) Part Number Stress V DS (V) Temperature ( o C) Sample Size Results (# of fails) Duration (Hrs) EPC EPC EPC EPC EPC EPC EPC Over 0.5 million accumulated device hours of reliability testing without failure across 891 devices

166 Time to Fail 100 V HTRB Acceleration FIT Rate vs V DS and Temperature 0.01% 1% % 35 C 20 yrs 10 yrs 150 C 90 C 166

167 HTGB Acceleration MTTF vs V GS FIT Rate vs V GS 1 FIT 10 yrs 167

168 High Temp Gate Bias (HTGB) Part Number Stress V GS (V) Temperature ( o C) Sample Size Results (# of fails) Duration (Hrs) EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC fail in over 0.97 million accumulated device hours of HTGB reliability testing greater than 5V. 0 fail in over 0.6 million accumulated device hours of HTGB reliability testing greater than 5.5V

169 A Look Into the Future 169

170 Moore s Law Revival Gen V V Generation 3 Higher Frequency Launched September 2013 Generation 4 2 X Performance Improvement Launched June 2014 Half Bridge ICs September 2014 Generation 5 ~December 2014 High Voltage September

171 GaN Integration Generation 2/4 Discrete HB Generation 4 Monolithic 4:1 HB + Top Switch (T) Synchronous Rectifier (SR) SR T 33 % die size reduction 171

172 Efficiency (%) Monolithic Half Bridge GaN POL w/ Gen 4 Monolithic HB 33 % die size reduction GaN POL w/ Gen 4 Discrete Transistors f sw =2 MHz f sw =3 MHz f sw =4 MHz Output Current (A) V IN =12 V V OUT =1.2 V L=100 nh 172

173 Summary GaN transistors enable exciting new applications such as LiDAR, RF Envelope Tracking and Wireless Power Transmission GaN transistors have the potential to replace silicon power MOSFETs and LDMOS in power conversion applications with a low-cost and higher efficiency solution GaN technology is keeping Moore s Law alive! 173