Development Board EPC9066 Quick Start Guide. EPC V Half Bridge with Sync FET Bootstrap Gate Drive

Transcription

1 Development Board Quick Start Guide EPC800 0 Half Bridge with Sync FET Bootstrap Gate Drive

2 DESCRIPTION The development board is a 0 maximum device voltage,.7 A maximum output current, half bridge with onboard gate drives, featuring the EPC800 enhancement mode (egan ) field effect transistor (FET). The gate driver has been configured with a synchronous FET bootstrap circuit featuring the EPC08 egan FET that eliminates high side device losses induced by the reverse recovery losses of the internal bootstrap diode of the gate driver. The purpose of this development board is to simplify the evaluation process of the EPC800 egan FET by including all the critical components on a single board that can be easily connected into any existing converter. The inclusion of the synchronous FET bootstrap circuit enables significant increase in operating frequency capability of the half bridge circuit. The development board is x.5 and has two EPC800 egan FETs in a half bridge configuration using Texas Instruments LM5 gate driver with supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. The board includes pads for the inclusion of customer components to facilitate testing in a Buck converter or ZS class-d amplifier configurations. A complete block diagram of the circuit is given in figure. Table : Performance Summary (T A = 5 C) Symbol Parameter Conditions Min Max Units DD Gate Drive Input Supply Range 7.5 IN Bus Input oltage Range * OUT Switch Node Output oltage 0 I OUT Switch Node Output Current.7* A PWM PWM Logic Input oltage Threshold Minimum High State Input Pulse Width Minimum Low State Input Pulse Width Input High Input Low PWM rise and fall time < 0ns PWM rise and fall time < 0ns ns 60# ns *Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to refresh high side bootstrap supply voltage. For more information on the EPC800 and EPC08 egan FETs please refer to the datasheet available from EPC at The datasheet should be read in conjunction with this quick start guide. QUICK START PROCEDURE Development board is easy to set up to evaluate the performance of the EPC800 egan FET. Refer to figure for proper connect and measurement setup and follow the procedure below:. Configure the board for either ZS class-d operation OR Buck converter operation.. With power off, connect the input power supply bus to +IN (J) and ground / return to IN (J).. For ZS class-d operation, with power off, connect a HF load to the HF output (RF-J OR sw-j and GND-J). For Buck converter operation, with power off, connect a DC load to the DC output (+out-j5 and GND-J).. With power off, connect the gate drive input to +DD (J90, Pin-) and ground return to DD (J90, Pin-). 5. With power off, connect the input PWM control signal to PWM (J70, Pin-) and ground return to either Pin- or Pin- of J Turn on the gate drive supply make sure the supply is within the 7.5 and range. 7. Turn on the controller / PWM input source and probe switching node to observe switching operation. amplifier board photo 8. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 5 on OUT ). Increase voltage slowly while monitoring operation to ensure the FETs are operating within their datasheet parameters. 9. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 0. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node, care must be taken to avoid long ground leads. Measure the switch node by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminal provided. See figure for proper scope probe technique. PAGE EPC EFFICIENT POWER CONERSION CORPORATION COPYRIGHT 06

3 IN DD Gate drive regulator Q L ZS HF output PWM Logic and dead-time adjust Level shift C Bypass L Buck C OUT C ZS DC output Q GND Figure : Block diagram of development board 7.5 DC Main voltage measurement + IN supply (note polarity) Dead-time setting (if installed) Switch-node oscilloscope probe Ground post High frequency connection SMA (optional) + DCmax Main supply (note polarity) Control signal inputs DC output DC output measurement Figure : Proper connection and measurement setup Do not use probe ground lead Place probe tip in large via Ground probe against post Minimize loop Figure : Proper measurement of the switch node EPC EFFICIENT POWER CONERSION CORPORATION COPYRIGHT 06 PAGE

4 THERMAL CONSIDERATIONS The development board showcases the EPC800 egan FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 5 C. NOTE. The development board does not have any current or thermal protection on board. Table : Bill of Materials - Amplifier Board Item Qty Reference Part Description Manufacturer/Part Number C0 Capacitors, Ceramic,.7 µf, 0, ±0%, X5R Samsung, CL05A75MP5NRNC C, C5, C6 Capacitors, Ceramic,.0 µf, 00, ±0%, X7S TDK, C0X7SA05K5AB C95, C96, C97 Capacitors, Ceramic,.0 µf, 5, ±0%, X5R Murata, GRM88R6E05KAD C7, C7 Capacitors, Ceramic, 00 nf, 5, ±0%, X7R TDK, C005X7RE0K050BB 5 C, C Capacitors, Ceramic, 00 nf, 6, ±0%, X7R Murata, GRM55R7C0KA88D 6 C5 Capacitors, Ceramic, nf, 5, ±0%, X7R TDK, C005X7REK050BB 7 C, C, C Capacitors, Ceramic, 0 nf, 00, ±0%, X7S TDK, C005X7SA0M050BB 8 C, C Capacitors, Ceramic, pf, 50, ±5%, NPO TDK, C005C0GH0J050BA 9 R6 Resistors, 7 KΩ, ±%, /0 W Panasonic, ERJ-RKF70X 0 R70 Resistors, 0.0 KΩ, ±%, /0 W Panasonic, ERJ-6ENF00 R7 Resistors, 8 Ω, ±%, /0 W Panasonic, ERJ-RKF8R0X R5, R75 Resistors, 0 Ω, ±%, /6 W Stackpole, RMCF00FT0R0 R Resistors,.7 Ω, ±%, ±/6 W Yageo, RC00FR-07R7L D5, D7, D75 Diodes, Schottky Diode, 0, F=70 ma, 0 ma Diodes Inc, SDM0U0-7 5 D0 Diodes, Schottky, 00, 0. A, 00 ma ST Microelectronics, BATKFILM 6 D Diodes, Zener, 5., 50 mw, ±5% Bourns Inc., CD060-Z5 7 Q egan FET, 00, 500 ma, R DS(on) =. 50 ma, 5 EPC, EPC08 8 Q, Q egan FET, 0,. A, R DS(on) =5 500 ma, 5 EPC, EPC800 9 U95 IC's, 5 LDO, 50 ma, up to 6 IN, dropout 50 ma Microchip, MCP70T-500E/MC 0 U0 IC's, Gate Driver, 5. DC,. A,.5 to 5.5 Texas Instruments, LM5TME/NOPB U7 IC's, Logic NAND Gate,.65 to 5.5, ± ma Fairchild, NC7SZ00L6X U7 IC's, Input AND Gate, Tiny Logic,.65 to 5.5, ± ma Fairchild, NC7SZ08L6X TP, TP, TP, TP Test Point, Test Point Subminiature Keystone, J70, J90, GP (See Note ) Headers, Male ertical, 6 Pin. 0" Contact Height,." Center Pitch FCI, HLF 5 J, J, J, J5 Headers, Rows by Pins." Male ertical,." Center Pitch TE Connectivity, Optional Components Item Qty Reference Part Description Manufacturer/Part Number C7 Capacitors, DNP, Ceramic,.0 µf, 00, ±0%, X7S TDK, C0X7SA05K5AB C6 Capacitor, DNP, Ceramic, 00 nf, 6, ±0%, X7R Murata, GRM55R7C0KA88D R7, R7, R7 Resistor, DNP, 0 Ω, /0 W, Jumper Panasonic, ERJ-GEY0R00 P7, P75 Potentiometer, DNP, Multi-turn Potentiometer, kω, ±0%, / W, Turn Top Adjustment Small Murata, P7W0C0B00 5 Lbuck Inductor, DNP, 0 μh, ±0%,.5A, mω, Resonance=0 MHz, Frequency Wϋrth, 70 Tested=00 KHz 6 Lzvs Inductor, DNP, 500 nh, Q=80, 50 MHz, DCR=6.5 mω, I RMS =. A Coilcraft, 99SQ-50JEB 7 D Diodes, DNP, Schottky Diode, 0, F=70 ma, 0 ma Diodes Inc, SDM0U0-7 8 J Connector, DNP, RP-SMA Plug, 50 Ω Linx, CONRESMA HS Hardware, DNP, W= (0.590") 5 mm, by L= (0.590") 5 mm, H=(0.7") 9.5 mm, LFM Advanced Thermal Solutions, ATS-550D-C-R0 Note (6 pin Header to be cut as follows) J70 cut pins used, J90 cut pins used, GP cut pin used EPC EFFICIENT POWER CONERSION CORPORATION COPYRIGHT 06 PAGE

5 J90 7 in. Male ert. R70 0 K A 5 B C7 00 nf, 5 A 5 B C7 00 nf, U7 NC 7SZ08L 6X R7 DNP 00 Ω Deadtime Right P7 Y D7 SDM0U0 U7 NC 7SZ00L 6X DNP 0 Ω Deadtime Left P75 D75 SDM0 U0 5 5 HS U0 L M5T M 5 HS GRH GRH GL H GL H 5 GRH GL H C μf, 00 Figure : - Schematic J70. Male ert. U95 MCP70T-500E/MC 5.0, 50 ma DFN IN C95 μf, 5 OUT Logic Supply Regulator C96 μf, 5 C97 μf, 5 x. Male ert. Main Supply Input x. Male ert. Buck Output x. Male ert. SW Output. Male ert. Ground Post x. Male ert. GND GND Logic Supply 7.5 DC - DC PWM H_Sig L _Sig H_Sig C pf, 50 L _Sig C pf, 50 GRret main main main C C C 0 nf, 00 0 nf, 00 0 nf, 00 GRret GP T P PH ProbeHole PWM PWM PWM R7 DNP PWM PWM PWM PWM R7 DNP 0 Ω R7 DNP 0 Ω Q EPC08 00,.8 Ω 5 C 00 nf, 6 Gbtst R E 7 C 00 nf, 6 D CD 060-Z5.7 C6 E MP T Y D E MP T Y SDM0 U0 C5 nf, 5 R6 7 K main.7 HS DNP D0 BAT5 K FIL M C0.7 μf, 0 GL H GRret T P main main Q EPC800 Q EPC800 L zvs DNP 500 nh L buck DNP Output C6 μf, 00 HF main C7 μf, 00 main C5 μf, 00 J SMA Board Edge HF Output 7 in DNP K R75 DNP K 00 nf, 6 Synchronous Bootstrap Power Supply J Gate Driver R5 0 Ω D5 SDM0 U0 T P T P ZS Tank Circuit Output J5 J J EPC EFFICIENT POWER CONERSION CORPORATION COPYRIGHT 06 PAGE 5

6 For More Information: Please contact or your local sales representative isit our website: Sign-up to receive EPC updates at bit.ly/epcupdates or text EPC to 88 EPC Products are distributed through Digi-Key. Demonstration Board Notification The board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 00% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications.