Introducing egan IC targeting Highly Resonant Wireless Power

Transcription

1 Dr. M. A. de Rooij The egan FET Journey Continues Introducing egan IC targeting Highly Resonant Wireless Power Efficient Power Conversion Corporation EPC - The Leader in egan FETs 1

2 Agenda Introducing the Synchronous Bootstrap FET egan ICs targeting Wireless Power Experimental results in a ZVS class D amplifier Summary egan is a registered trademark of Efficient Power Conversion Corporation EPC - The Leader in egan FETs 2

3 Impact of Gate Driver Bootstrap Diode Q RR Gate drivers with internal bootstrap diodes have Q RR Schottky diode cannot be integrated This Q RR induces losses in the high side device: Proportional to frequency Present even with ZVS Level Shift V DD Q 2 Q mw at 50 V, 6.78 MHz ~ 40% of total FET losses + EPC - The Leader in egan FETs 3

4 Implementing a Synchronous FET Bootstrap Supply V Drvr + Q BTST C BTST D ENH Gate Driver + level shift Q 2 V Main + C ENH Gate Driver Q 1 EPC - The Leader in egan FETs 4

5 Synchronous Bootstrap FET Design Considerations Timing: Turn on - Delay Turn off Immediate Off state margin if lower FET reverse conducts Drain inductance to prevent over-voltage V V Sw-node V DD V GS_Qlow V GS_Btst Off-state margin Turn-on delay Turn-off immediate time EPC - The Leader in egan FETs 5

6 Synchronous FET Bootstrap Supply Implementation 5 V Q BTST R damp V DD + C DECP C ENH D ENH* R bleed Level Shift Q 2 ZVS tank L ZVS D off R on D 4V7 Q 1 C ZVS LM5113 Turn-off immediate Turn-on delay Reference: M. A. de Rooij, Wireless Power Handbook, 2 nd Edition, El Segundo, October 2015, ISBN EPC - The Leader in egan FETs 6

7 Waveform Improvements at MHz Operation V supply = 45 V, No load Q RR effect Δt = 4.2 ns No Q RR effect Δt = 4.2 ns Lower dv/dt Δt = 6.6 ns Equal dv/dt Δt = 4.2 ns 5 V/Div. 20 ns/div. 5 V/Div. 20 ns/div. Original Configuration SW Node Gate Driver Input Sync-Bootstrap Configuration EPC - The Leader in egan FETs 7

8 Synchronous Bootstrap Power Dissipation Results FET Power losses [mw] Total FET power, excludes gate driver Thermal Limit reached mw mw Increased 800 operating range 600 Original MHz Original MHz 400 SyncBoot MHz Original 6.78 MHz 200 SyncBoot MHz SyncBoot 6.78 MHz Supply Voltage [V] EPC - The Leader in egan FETs 8

9 egan ICs targeting Wireless Power Applications Source Upper D BTST G upper Positive Drain Upper Gate Upper Source Lower Drain Btst Source Btst EPC Part Number EPC2107 EPC x 1.35 mm Solder Side View Package (mm) V DS (V) V GS (V) Gate Lower Drain Lower Gate Btst R (mω) Q V Typ. (pc) 9 S BTST Q GS Typ. (pc) D Grev Q GD Typ. (pc) 3 G BTST Q BTST R G Typ. (Ω) V th Typ. (V) Q upper Q lower 2 8 G lower EPC - The Leader in egan FETs 9 Q RR (nc) I D (A) T J Max. ( C) BGA1.35x BGA1.35x BGA1.35x BGA1.35x BGA1.35x BGA1.35x Ground Out 1 Out 2

10 FoM WPT [nc mω] WPT Device Comparison DS(on) ( Q Q Q ) FOM = R + GD Zero Voltage Switching Class D 700 Q OSS 5.2x EPC2107 EPC2108 MOSFET 2 G 2.2x 4.3x Q OSS Q OSS OSS FOM WPT = R DS(on) ( Q ) OSS 4.7x FOM WPT = RDS(on) ( QG QGD ) EPC - The Leader in egan FETs 10

11 ZVS Class D Experimental Power Schematic Bypass Mode connection JP1 Pre-Regulator Jumper V AMP EPC9509 only Coil Connection Pre- Regulator Q 1_a L ZVS12 Q 1_b V IN + J1 EPC9509 and EPC9510 Q 2_a L ZVS1 C ZVS1 EPC9510 only C ZVS2 L ZVS2 Single Ended Operation Jumper Q 2_b EPC - The Leader in egan FETs 11

12 Gate Driver LM5113 (5 V) Experimental Single-Ended ZVS Class D Amplifier Configured for 6.78 MHz Operation ZVS Inductor L ZVS Coil Connection egan IC Oscilloscope Probe Post EPC9510 EPC V, 220 mω, V GS = 5 V ZVS Capacitor C ZVS (Bottom Side) EPC - The Leader in egan FETs 12

13 Experimental Differential-Mode ZVS Class D Amplifier Gate Driver LM5113 (5 V) Configured for 6.78 MHz Operation Coil Connection ZVS Inductor L ZVS egan IC Oscilloscope Probe Post EPC9509 EPC V, 150 mω, V GS = 5 V ZVS Capacitor C ZVS (Bottom Side) EPC - The Leader in egan FETs 13

14 Load Calibration Results for Class 2 Measured at 6.78 MHz High Q coil used as an inductor ONLY Tuning Capacitors Current Probe Low Inductance Resistance Network EPC - The Leader in egan FETs 50 Ω Smith +35j Ω +30j Ω +20j Ω +10j Ω 0j Ω -5j Ω -10j Ω -20j Ω -30j Ω -35j Ω 14

15 Load Calibration Results for Class 3 Measured at 6.78 MHz High Q coil used as an inductor ONLY Tuning Capacitors Current Probe Low Inductance Resistance Network EPC - The Leader in egan FETs 50 Ω Smith +40j Ω +30j Ω +20j Ω +10j Ω 0j Ω -5j Ω -10j Ω -20j Ω -35j Ω -50j Ω -55j Ω -60j Ω 15

16 Single-Ended ZVS Class D Class 2 Experimental Results Measured at 6.78 MHz 95 EPC9510 Total Amplifier Efficiency j Ω Efficiency [%] Includes Gate Driver Power Reflected Resistance [Ω] Output Power [W] +20j Ω 0j Ω -5j Ω -10j Ω -35j Ω Pout EPC - The Leader in egan FETs 16

17 Differential-Mode ZVS Class D Class 3 Results Measured at 6.78 MHz 94 EPC9509 Total Amplifier Efficiency j Ω Efficiency [%] Includes Gate Driver Power Reflected Resistance [Ω] Output Power [W] +20j Ω -5j Ω -35j Ω -60j Ω Pout EPC - The Leader in egan FETs 17

18 Summary Introduced the egan IC Lateral egan FET structure enables high voltage integration Three (3) FETs in one 1.35 mm x 1.35 mm chip-scale package Integration improves efficiency and power density Experimentally verified in a ZVS Class D amplifier egan ICs enable lower cost, higher performance wireless power EPC - The Leader in egan FETs 18

19 Wireless Power Handbook Visit EPC s Booth #2244 to see several demonstrations in operation 2 nd Edition Handbook on wireless power that covers this work and much more available at Digikey ( ND) or Amazon EPC - The Leader in egan FETs 19

20 EPC - The Leader in egan FETs 20