Development Board EPC9047 Quick Start Guide

Transcription

1 Development Board Quick Start Guide Half Bridge with Gate Drive for EPC0 DESCRIPTION The development boards are in a half bridge topology with onboard gate drives, featuring the EPC0 egan field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of these egan FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is x. and contains two egan FETs in a half bridge configuration using the Texas Instruments UCC gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. complete block diagram of the circuit is given in Figure. For more information on the EPC0 egan FET please refer to the data sheet available from EPC at The data sheet should be read in conjunction with this quick start guide. For More Information: Table : Performance Summary (T = C) SYMBOL PRMETER CONDITIONS MIN MX UNITS V DD Gate Drive Input Supply Range V Bus Input Voltage Range 0 V V OUT Switch Node Output Voltage 0 V I OUT Switch Node Output Current * V PWM PWM Logic Input Voltage Threshold Minimum High State Input Pulse Width Minimum Low State Input Pulse Width Input High Input Low. 0. V PWM rise and fall time < 0ns 00 ns V PWM rise and fall time < 0ns 00# ns *ssumes inductive load, maximum current depends on die temperature actual maximum current will be subject to switching frequency, bus voltage and thermal management. # Dependent on time needed to refresh high side bootstrap supply voltage. V V Please contact info@epc-co.com or your local sales representative Visit our website: Sign-up to receive EPC updates at bit.ly/epcupdates or text EPC to 88 EPC Products are distributed through Digi-Key. Demonstration Board Notification boards are intended for product evaluation purposes only and are not intended for commercial use. s evaluation tools, they are not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. s board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 00% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 0

2 QUICK STRT PROCEDURE The development boards are easy to set up to evaluate the performance of the egan FET. Refer to Figure for proper connect and measurement setup and follow the procedure below:. With power off, connect the input power supply bus to (J, J) and ground / return to (J, J8).. With power off, connect the switch node of the half bridge OUT (J, J) to your circuit as required.. With power off, connect the gate drive input to V DD (J, Pin-) and ground return to V DD (J, Pin-).. With power off, connect the input PWM control signal to PWM (J, Pin-) and ground return to any of the remaining J pins.. Turn on the gate drive supply make sure the supply is between V and V range.. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 0 V on V OUT.. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the terminals provided. See Figure for proper scope probe technique. V DD Gate Drive Regulator Gate Drive Supply Half Bridge with Bypass PWM Input Enable Level shift, Dead-time djust and Gate Drive OUT Figure : Block Diagram of Development Board EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 0 PGE

3 QUICK STRT PROCEDURE Supply Gate Drive Supply (Note Polarity) V V _ V DD _ V (For Efficiency Measurement), 0 dditional bus capacitance can be added on back I IN Switch Node External Circuit <0 V Supply _ PWM Input Figure : Proper Connection and Measurement Setup, 0 Do not use probe ground lead Ground probe against TP Minimize loop Place probe tip in large via at OUT Figure : Proper Measurement of Switch Node OUT EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 0 PGE

4 0 V 00 MHz ringing.9 ns rise time 8. ns fall time Figure (a) Rising Edge Figure (b) Falling Edge Figure : Typical Waveforms for. = 0 V to V/ (00 khz) Buck converter showing rising and falling edges, CH: (V PWM ) Input logic signal CH: (I OUT ) Output inductor current CH: (V OUT ) Switch node voltage THERML PERFORMNCE The development boards showcase the EPC0 egan FETs. These development boards are intended for bench evaluation with low ambient temperature and convection cooling. The addition of heatsinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 0 C. NOTE. The development boards do not have any current or thermal protection on board. Table : Bill of Materials Item Qty Reference Part Description Manufacturer / Part # C, C, C, C0, C Capacitor, µf, 0%, V, XR Murata, GRM88RE0KD C, C Capacitor, 00 pf, %, 0V, NP0 TDK, C00XREK00BC C8, C9, C, C Capacitor, 0. µf, 0%, V, XR TDK, C0XTE0K C, C, C8 Capacitor, 0. µf, 0%, 0 V, XS C0XTE0K D, D Schottky Diode, 0 V Diodes Inc., SDM0U0- D Diode, 00 V Diodes Inc.,BVWS--F D, D Diode, 0 V Diodes Inc.,BS0LP- 8 J Connector pins of Tyco, J Connector pins of Tyco, J, J, J, J, J, J8 Connector FCI, 80-HLF Q, Q egan FET EPC0 R Resistor, 0.0 K, %, /8 W Stackpole, RMCF00FT0K0 R, R Resistor, Ohm, %, / W Stackpole, RMCF00FTR00 R, R, R, R Resistor, 0 Ohm, /8 W Stackpole, RMCF00ZT00R0 R Resistor, 0 Ohm, %, /8 W Stackpole, RMCF00FT0R R Resistor, 0 Ohm, %, /8 W Stackpole, RMCF00FT0R TP, TP Test Point Keystone Elect, 0 8 TP Connector /0th of Tyco, U I.C., Logic Fairchild, NCSZ00LX 0 U I.C., Opto-coupler 00 LFM Silicon Labs, Si80BC U I.C., Logic Fairchild, NCSZ08LX U, U I.C., Gate driver Texas Instruments, UCC 0 P, P potentiometer 0 R resistor 0 U I.C. EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 0 PGE

5 - Vdc J CON J9 CON PWM PWM R PWM PWM R 0k R U B Y NCSZ00LX PWM DZH R U DL B NCSZ08LX P C μf, V Y D SDM0U0 R 0 C 00p J CON DH C μf, V P D DRL SDM0U0 R 0 DRH C C0 μf, V μf, V U C 00p U SS80BC R D BV 8 8 R C μf, V DRHT C9 0.μF, V DRLT U C8 0.μF, V LDO VREF VSS UCC U BC LDO VREF VSS UCC D BS0LP GDH GDH R ohm SW OUT D BS0LP GDL GDL R ohm C 0.μF, V GDH EPC0 C 0.μF, V GDL TP Keystone 0 Q J J Q SW OUT C C C8 J J 0.μF, 0V TP CON J 0V Max TP Keystone 0 J8 Figure : Development Board Schematic EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 0 PGE