Development Board EPC9040 Quick Start Guide

Transcription

1 Development Board EPC900 Quick Start Guide EPC0 Monolithic Half-Bridge with Gate Drive Revision.0

2 QUICK STRT GUIDE DESCRIPTION These development boards are in a monolithic half bridge topology with onboard gate drives, featuring the EPC0 eganic (Enhancementmode Gallium Nitride Integrated Circuits). The purpose of these development boards is to simplify the evaluation process of these monolithically integrated egan FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is x and contains one eganic in half bridge configuration using the Texas Instruments LM5 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance and has additional area to add buck output filter components on board. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. complete block diagram of the circuit is given in Figure. For more information on the EPC0 eganic, please refer to the datasheets available from EPC at The datasheet should be read in conjunction with this quick start guide. Table : Performance Summary (T = 5 C) EPC900 Demonstration System EPC900 Symbol Parameter Conditions Min Max Units VDD Gate Drive Input Supply Range 7 V Bus Input Voltage Range 60* V V OUT Switch Node Output Voltage 60* V I OUT Switch Node Output Current 5** V PWM PWM Logic Input Voltage Threshold Minimum High State Input Pulse Width Minimum Low State Input Pulse Width Input High.5 6 V Input Low 0.5 V V PWM rise and fall time < 0ns V PWM rise and fall time < 0ns 50 ns 00# ns *Maximum input voltage depends on inductive loading. ** Maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermal cooling. Symmetrical egan intended for 50% duty cycle or low step-down ratio applications. # Limited by time needed to refresh high side bootstrap supply voltage. SETUP ND OPERTION The development boards are easy to set up to evaluate the performance of the eganic. The board allows the on-board placement of buck output filter components. Refer to Figure for proper connect and measurement setup and follow the procedure below:. With power off, connect the input power supply bus to (J5, J6) and ground / return to (J7, J8).. With power off, connect the switch node of the half bridge OUT (J, J) to your circuit as required.. With power off, connect the gate drive input to V DD (J, Pin-) and ground return to V DD (J, Pin-).. With power off, connect the input PWM control signal to PWM (J, Pin-) and ground return to any of the remaining J pins. 5. Turn on the gate drive supply make sure the supply is between 7 V and V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltages). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the terminals provided. See Figure for proper scope probe technique. V DD PWM Input 7 V V V DD Supply Gate Drive Supply (Note Polarity) V (For Efficiency Measurement) PWM Input Gate Drive Regulator Logic and Dead-time djust VERSION Gate Drive Supply LM5 Gate Driver Monolithic Half Bridge Figure : Block Diagram of Development Board Pads for Buck Output Filter EPC900 DEVELOPMENTBORD P Pads for Buck Output Filter VSW OUT Supply * (For Efficiency Measurement) V SW V OUT Figure : Proper Connection and Measurement Setup I IN 60 V V V OUT EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 07

3 QUICK STRT GUIDE Demonstration System EPC900 EPC900 DEVELOPMENTBORD Do not use probe ground lead Ground probe against TP Minimize loop Place probe tip in large via at OUT Figure : Proper Measurement of Switch Node OUT THERML CONSIDERTIONS The EPC900 development boards showcase the EPC0 eganic. These development boards are intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 50 C. NOTE. These development boards do not have any current or thermal protection on board. Table : Bill of Material Item Qty Reference Part Description Manufacturer / Part# C, C0, C, Capacitor, µf, 0%, 5 V, X5R Murata, GRM88R6E05KD C6, C7 Capacitor, 00 pf, 5%, 50 V, NP0 Kemet, C00C0K5GCTU C9, C9 Capacitor, 0. µf, 0%, 5 V, X5R TDK, C005X5RE0K C, C, C, C Capacitor - µf, 0%, 00 V, X7S TDK, CGJX7S05K5E 5 D, D Schottky Diode, 0 V Diodes Inc., SDM0U0-7 6 J, J, J9 Connector pins of Tyco, J, J, J5, J6, J7, J8 Connector FCI, 6860-HLF 8 Q eganic EPC0 9 R Resistor, 0.0 k, 5%, /8 W Stackpole, RMCF060FT0K0 0 R, R5 Resistor, 0 Ω, /8 W Stackpole, RMCF060ZT0R00 R Resistor, 7 Ω, %, /8W Stackpole, RMCF060FT7R0 R5 Resistor, - 75 Ω, %, /8W Stackpole, RMCF060FT75R0 R9, R0, R, R Resistor, 0 Ω, /0 W Panasonic, ERJ-GE0R00C TP, TP Test Point Keystone Elect, TP Connector /0th of Tyco, U I.C., Logic Fairchild, 7SZ00L6X 7 U I.C., Gate driver Texas Instruments, LM5 8 U I.C., Regulator Microchip, MCP70T-500E/MC 9 U I.C., Logic Fairchild, 7SZ08L6X 0 0 R Resistor 0 D Diode 0 P, P Potentiometer EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 07

4 QUICK STRT GUIDE J5 See Table Demonstration System EPC Vdc J CON C0 µf, 5 V R 0 k Figure : EPC900 Development Board Schematic C µf, 5 V VCC PWM U VDD B 7SZ00L6X J6 Y SW OUT TP CON J7 J8 J C µf, 5 V TP Keystone 505 J PWM U MCP70 IN OUT R R5 R D SDM0U0 R5 D SDM0U0 R 7 VCC TP Keystone J CON J9 CON U B 7SZ08L6X P VDD Y 75 P C6 00pF C7 00 pf U 0. µf, 5 V C9 C C C C µf, 00 V LM5TM R9 R R0 R 0. µf, 5 V C9 : HB Q D EPC EFFICIENT POWER CONVERSION CORPORTION COPYRIGHT 07

5 For More Information: Please contact or your local sales representative Visit our website: Sign-up to receive EPC updates at bit.ly/epcupdates or text EPC to 88 EPC Products are distributed through Digi-Key. Demonstration Board Notification The EPC900 board is intended for product evaluation purposes only and is not intended for commercial use. Replace components on the Evaluation Board only with those parts shown on the parts list (or Bill of Materials) in the Quick Start Guide. Contact an authorized EPC representative with any questions. This board is intended to be used by certified professionals, in a lab environment, following proper safety procedures. Use at your own risk. s an evaluation tool, this board is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. s board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 00% RoHS compliant. The Evaluation board (or kit) is for demonstration purposes only and neither the Board nor this Quick Start Guide constitute a sales contract or create any kind of warranty, whether express or implied, as to the applications or products involved. Disclaimer: EPC reserves the right at any time, without notice, to make changes to any products described herein to improve reliability, function, or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, or other intellectual property whatsoever, nor the rights of others.