GaN Transistors for Efficient Power Conversion

Transcription

1 GaN Transistors for Efficient Power Conversion

2 Agenda How GaN works Electrical Characteristics Design Basics Design Examples Summary 2 2

3 How GaN Works 3 3

4 The Ideal Power Switch Block Infinite Voltage Carry Infinite Current Switch In Zero Time Zero Drive Power Normally Off 4 4

5 5 Power Switch Wish List Faster Lower Conduction Loss Less Capacitance Smaller Lower Cost

6 Material Comparison 6 6

7 GaN + AlGaN Spontaneous Polarization AlGaN GaN 7 7

8 GaN Magic V AlGaN GaN 2D Electron Gas 8 8

9 GaN Switch V Applying bias destroys the polarization E Field AlGaN GaN 9 9

10 GaN Now we Switch have a switch That has high voltage blocking V capability, low on resistance, and is very, very fast. AlGaN GaN Depletion Mode = Normally On 10 10

11 Device Construction Concept Source Gate AlGaN Protection Dielectric Drain GaN Substrate Early substrate materials: SiC and Sapphire Are expensive and hard to manufacture. Silicon substrates are much lower cost and allow fabrication in a standard CMOS Fab

12 What About Normally Off Devices? True enhancement mode GaN HFETs have been around for years There are various methods for dissipating the electron gas under the gate 12 12

13 Enhancement Mode A positive voltage from Gate-To-Source establishes an electron gas under the gate 13 13

14 State of the Art 14 14

15 Body Diode? A positive voltage from Gate-To-Drain also establishes an electron gas under the gate 15 15

16 egan FET Reverse Conduction MOSFET + Q RR egan FET + Zero Q RR 16 16

17 Threshold vs. Temperature Normalized Thershold Voltage egan FET MOSFET A Junction Temperature ( C) 17 17

18 MOSFET Transfer Characteristics Negative temperature coefficient region of silicon MOSFET Source:

19 egan FET Transfer Characteristics EPC

20 egan FET Safe Operating Area 1 ms 10 ms 100 ms DC 20

21 egan FET Safe Operating Area 1 ms 10 ms 100 ms DC 21

22 egan FET Capacitances C GS C DS GaN Silicon C GD 22 22

23 Total Gate Charge BSC057N08NS EPC2001 = 100 V, 5.6 mω typ BSC057N08 = 80 V, 4.7 mω typ 23 23

24 Figure of Merit FOM = Rdson x Qg (100V) EPC2001 BSC109N10NS3 IRFH5030 SiR870DP FDMS

25 egan FET Loss Mechanisms Like A MOSFET I²R Conduction Loss Capacitive Switching Losses Gate Drive Losses V I Switching Loss Not Like A MOSFET High Reverse Conduction Loss No Body Diode Reverse Recovery Loss 25 25

26 egan FET Loss Mechanisms Like A MOSFET I²R Conduction Loss Capacitive Switching Losses Gate Drive Losses V I Switching Loss Not Like A MOSFET High Reverse Conduction Loss No Body Diode Reverse Recovery Loss Can be much, much better than comparable silicon MOSFET 26 26

27 Package Wish List Low parasitic resistance Low parasitic inductance Low thermal resistance Small size Low cost 27 27

28 Flip-Chip LGA Construction egan FET Silicon Solder Bar Copper Trace Printed Circuit Board Absolute minimum lead resistance and inductance! 28

29 LGA Construction Drain Contacts Interleaving to reduce layout inductance Substrate Gate Source Contacts 29 29

30 Size Comparison 200 V egan FET D-PAK 5.76 mm² Drawn To Scale 65.3 mm² 30 30

31 Key Applications Wireless Power Transmission GaN Enabled RF DC-DC Envelope Tracking GaN Enabled RadHard Power Over Ethernet RF Transmission Network and Server Power Supplies Point of Load Modules Energy Efficient Lighting Class D Audio 31 31

32 Design Basics Agenda Gate Driver Requirements Layout Thermal Management 32 32

33 E-Mode Gate Drive - Low V GS(ON) Overhead V GS(Max) = 6 V 33 33

34 Gate Drive Solution No overshoot: R G 4 ( LG + L C GS S ) Minimize inductance Tight gate drive layout BGA and LGA minimizes package inductance Choose correct resistance Separate source and sink transistors allowing for separate drive paths

35 Bootstrap Supply +5V HB VIN LEVEL SHIFT HOH HOL Switch can be node negative during low side diode conduction Regulated high side supply Minimal dead time and slow bootstrap HS 35 35

36 High Side Regulation LM5113 Bootstrap clamp limits floating (HS) power supply Separate control inputs allow accurate, flexible tuning to minimize dead-time Well matched channel-to-channel propagation delays are critical Optional Schottky in parallel Texas Instruments, Gate Drivers for Enhancement Mode GaN Power FETs 100 V Half-Bridge and Low- Side Drivers Enable Greater Efficiency, Power Density, and Simplicity, SNVB

37 Layout 37 37

38 Packaging Evolution So-8 LFPAK DirectFET LGA egan Power Loss (W) Device Loss Breakdown 82% 18% Package Die 73% 27% 47% 53% So-8 LFPAK DirectFET LGA V IN =12V V OUT =1.2V I OUT =20A F S =1MHz 18% 82% Efficiency (%) So-8 LFPAK DirectFET egan Switching Frequency (MHz) 38 38

39 Generating Kelvin Source Connection Source Return Source R Source C GD Substrate Gate R Series R G C GS R Sink Drain L S Minimize Common Source Inductance 39 39

40 Buck Converter Parasitics C in T SR L S : Common Source Inductance L Loop : High Frequency Power Loop Inductance Power Loss(W) Power Loss vs Parasitic Inductance Ls L Loop Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, F S =1 MHz, I OUT = 20 A 40 40

41 Layout Impact on Efficiency Efficiency (%) Measured Efficiency 40V MOSFET 3x3mm LFPAK L Loop 3nH L Loop 0.4nH L Loop 1.0nH L Loop 1.6nH L Loop 2.9nH Output Current (I OUT ) V IN =12 V, V OUT =1.2 V, F S =1 MHz, L=150 nh Experimental Prototype L LOOP 0.4 nh 41 41

42 Layout Impact on Peak Voltage L Loop 1.0 nh L Loop 0.4 nh 70% Overshoot 30% Overshoot Switching Node Voltage V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=150 nh 42 42

43 Conventional Lateral Layout Top View Side View 43 43

44 Conventional Vertical Layout Top View Side View Bottom View 44 44

45 Optimal Layout Top View Side View Top View Inner Layer

46 Power Loss Comparison Power Loss (W) Lateral Power Loop Optimal Power Loop Vertical Power Loop High Frequency Loop Inductance (L LOOP ) V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM

47 Efficiency Comparison Efficiency (%) V MOSFET Design 1 Optimal Design 1 Vertical Design 1 Lateral Design Output Current (I OUT ) V IN =12 V V OUT =1.2 V F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM

48 egan FET vs. MOSFET Si MOSFET egan FET V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh egan FET T/SR: EPC2015 MOSFET T:BSZ097N04LS SR:BSZ040N04LS 48

49 Layout Summary egan FETs improve performance in high switching frequency converters CSI is a critical component for maximizing switching performance Gate drive loop inductance limits switching speed Optimizing power loop inductance improves efficiency and minimizes voltage overshoot Current measurements affect performance Voltage measurements are bandwidth limited Reduced ringing reduces EMI 49 49

50 Thermal Management 50 50

51 Thermal Management Heat Is Generated In GaN Material Essentially On The Surface Of The Die Silicon Substrate Active GaN Device Region Solder Bars Copper Traces Printed Circuit Board 51 51

52 Thermal Management Silicon Substrate R ƟJC Active GaN Device Region Solder Bars R ƟJB Copper Traces Printed Circuit Board Two Paths For Heat: Through The Back Of The Die Or Through The Solder Contacts Into The PCB 52 52

53 Thermal Resistance with Heat Sink Silicon Substrate Active GaN Device Region R ƟJC Solder Bars R ƟJB Copper Traces Printed Circuit Board 53 53

54 Thermal Resistance with Heat Sink 2 22 Printed Circuit Board 1 Thermal Interface Material on sides of die too 54 54

55 Thermal Model with Heat Sink Back of Die temperature Heatsink R θtim R θha R θtim Ambient Temperature Junction temperature R θjc R θjc R θjb R θjb Other PCB losses Device 1 Power dissipation R θspread R θpcba Ambient Temperature Device 2 Power dissipation 55 55

56 Thermal Results Possible to remove up to 5 W from small EPC die with double sided cooling 56

57 Design Example Agenda Hard Switched Circuits Buck Converter Isolated Full Bridge Envelope Tracking Resonant Circuits Intermediate Bus Converter 57 57

58 Buck Converters 58

59 High Frequency Buck Converters D. Reusch, D. Gilham, Y. Su, and F.C. Lee, C, Gallium Nitride Based 3D Integrated Non-Isolated Point of Load Module, APEC

60 EPC9107 Optimal Layout Buck Module Switching Node Voltage V IN =28 V I OUT =15 A EPC9107 Demonstration Board V IN =12-28 V V OUT =3.3 V I OUT =15 A F S =1 MHz 2 x EPC V/ div 60

61 EPC9107 Demonstration Board Efficiency (%) V IN 19 V IN 24 V IN 28 V IN Output Current (Io) V OUT =3.3 V F S =1 MHz GaN T/SR: EPC2015 Driver LM

62 Isolated Full Bridge 62

63 100 V Hard Switching FOM 160 FOM=(Q GD +Q GS2 )*R DSON (nc*ω) Q GS2 Q GS2 Q GS2 Q Q GS2 GD Q GD Q GS2 Q GD Q GD Q GD 100V egan FET 80V MOSFET 1 80V MOSFET 2 80V MOSFET 3 80V MOSFET 4 V DS =0.5*V DS, I DS = 15 A 63 63

64 Regulated Full Bridge Converter EPC9102 Demo board Full Bridge, Vin, 12 V, 200 W, 375 khz 64 64

65 Efficiency Comparison 375 khz egan FET 250 khz MOSFET Regulated 12 V Output 65 65

66 Brick Converter Summary Topologies varied Optimization as important as device selection Efficiency is key to power density Maximum power loss is fixed. Good comparison requires identical designs Given topology, egan FETs will outperform MOSFETs based on superior FOM 66 66

67 Overview of Envelope Tracking World of Radio Frequency Power Amplifiers (RFPA) is changing. Increased efficiency driven by: Improved battery life Reduced cooling Reduced size Lower cost of operation 67

68 Peak to Average Power Ratio Same average Normalized to same peak Ref: Nujira.com website 68

69 Effect of PAPR Average Power Peak Power Fixed supply PAPR = 0dB Peak efficiency up to 65% Average efficiency only 25 % Increasing PAPR Output Probability Output Power (dbm) 69

70 Effect of Envelope Tracking Average efficiency > 50 % (incl. ET) Only 1/3 the losses Envelope Tracking Output Probability Average Power Output Power (dbm) 70

71 RFPA Standards* Up to 20 MHz Carrier bandwidth required Required ET supply BW up to 5x higher if linear control *Ref: website 71

72 Envelope Tracking Supply ET power supply topologies vary Open loop boost full BW required Closed loop linear-assisted Buck* Buck ~ 10% Bandwidth ~ 90% Power Linear AMP ~ 10% Power Highest 90% of Bandwidth *V. Yousefzadeh, et. Al, Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers, ISCAS

73 egan FET based Buck(s) for ET 1300 W DVB* 8 MHz BW and 8 db PAPR Linear-assisted Buck for ET 4 phase x 1 MHz Buck with up to 800 khz band width 45 V IN, 22 V OUT / 15 A OUT (Avg) Pure Buck option for ET (Push frequency) 10 phase x 4 MHz Buck with up to 8 MHz band width 45 V IN, 22 V OUT / 6 A OUT (Avg) *Representative of a high power ET buck in HV LDMOS, such as that implemented by ET specialist Nujira. 73

74 6 A OUT / 4 MHz Single φ Buck Modified an EPC9006 development board 45 V IN Before After Gappad GP mil 22 V OUT Common LM5113TE EPC

75 Efficiency Results 98% 10x potential bandwidth require 2.5x more phases and 2x losses 16 97% 14 96% 12 Efficiency (%) 95% 94% 93% 4 MHz Efficiency Power loss (W) 92% 1 MHz Efficiency 4 91% 90% 2 1 MHz Losses Output Power (W) 4 MHz Losses 75

76 Loss Breakdown EPC2001 EPC2007 EPC2001 EPC MHz EPC MHz EPC9006 Future die size optimization possible 76 76

77 Higher Frequency ET Results* EPC1014 BSC016N04LSG 24 V IN to 12 V OUT Buck 20 to 30 pp improvement! 4 MHz 7 MHz 10 MHz *D. Čučak, et. al, Application of egan FETs for highly efficient Radio Frequency Power Amplifier, CIPS

78 Envelope Tracking Summary egan FETs are an enabling technology for ET Low charge reduces delay and switching times Thermally possible - with double sided cooling Results are representative, but not optimized Improve inductor selection Improve thermal design Reduce high side peak device temp by reducing low side device size to reduce Q OSS losses Power and # of phases application specific 78 78

79 Resonant Converters 79

80 100 V Soft Switching FOM 350 FOM=(Q OSS or Q G )*R DSON (nc*ω) Q OSS Q OSS Q OSS Q G Q G Q G 100 V EPC V BSC057N08NS3G 80 V BSZ123N08NS3G V DS =48 V 80

81 egan FET vs. MOSFET 81

82 ZVS Switching Comparison T ZVS = 42 ns egan FET V DS MOSFET V DS T ZVS = 87 ns MOSFET V GS egan FET V GS F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 82

83 Duty Cycle Comparison D egan FET = 42% D MOSFET = 34% MOSFET V GS egan FET V DS egan FET V GS MOSFET V DS F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 83

84 Efficiency Comparison Efficiency (%) MHz egan FET 1.2 MHz MOSFET 10 W 12 W 14 W Power Loss (W) MHz MOSFET 1.2 MHz egan FET Output Current (I OUT ) Output Current (I OUT ) F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 84

85 Loss Breakdown Power Loss (W) Gate Drive Transfomrer Core Conduction + Turn Off 2 0 egan FET I OUT = 2.5 A MOSFET I OUT = 2.5 A egan FET I OUT = 20 A MOSFET I OUT = 20 A F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 85

86 EPC9105 Bus Converter EPC9105 Demonstration Board V IN, 12 V OUT, 350 W, 1.2 MHz L IN L K1 2 SR V IN+ C IN Q 1 Q 3 4:1 * * * Q 6, Q 7 V OUT+ L OUT C RES C OUT V IN- Q 2 Q 4 L K2 2 SR Q 5, Q 8 V OUT- 86

87 Resonant Converter Summary egan FETs improve high frequency resonant converter performance Lower output charge Lower gate charge More power delivery per cycle 87 87

88 Summary GaN transistors have the potential to replace silicon power MOSFETs in power conversion applications with a low-cost and higher efficiency solution egan FETs are straightforward to use, but care must be taken due to the higher switching speeds compared with power MOSFETs GaN transistors enable exciting new applications such as RF Envelope Tracking 88 88