Microsemi SiC MOSFETs

Transcription

1 Microsemi SiC MOSFETs Francis K Chai April 15 th -16 th, 2015

2 Outline 1700V wafer- level data Starting epitaxial wafers Technology development Benchmark of SiC MOSFET by Microsemi against competitors DC characteristics key to switching performance Dynamic performance Ruggedness Reliable technology platform Die size and switching Silicon superjunction MOSFET benchmark

3 New Voltage Node 1700V

4 First 1700V MOSFET Wafer- Level Data 4 I D [V] C Competitor V/4.9A/1Ω V D [V]

5 Quality Of Epitaxial Wafers

6 Epitaxial Layer Thickness Thickness [μm] 1μm target

7 Epitaxial Layer Doping Doping concentration [cm - 3 ] target

8 Epitaxial Layer Surface Roughness RMS Surface Roughness[Å] 5Å Denko Gen 2

9 Epitaxial Layer Defect Count Defect count [per 100mm wafer] 200

10 SiC Epitaxial Wafer Cross-Polarization History doping stain Birefringence induced by lattice strain. A perfect crystal will produce a uniform appearance when viewed between crossed polarizers, as the polarized light rotation will be the same everywhere. Lattice strain induced by lattice defects, polytype inclusions, compositional in- homogeneities, etc. can all result in regions that induce locally different rotations of the polarized light. The local variations in light rotation are easily imaged with this technique, providing a picture of crystal quality.

11 Technology Development

12 Special Processing Contrast to Silicon Technology Dopant introduction by implant at elevated temperatures Dopant activation, implant damage anneal at high temperatures No diffusion High temperature gate oxidation Above translates into all layer removal post dopant introduction for electrical activation Alignment is critical E220 Production Implanter CentroTherm CHV- 100 Post Implant Annealing to 1700 C Hi Temp Oxidation SiC MOSFET Gate Oxidation

13 Process Integration P- well implants for reduced R DS(ON) contribution from JFET region o V th adjustment implant o Voltage blocking implant Balance between guard- ring, p- well voltage blocking enables UIS capability Topology conforming backend metallization for high yield n + source pw 1 gate poly n + source pw 1 p + p + gr p-well 2 p-well 2 n-epitaxy n-substrate

14 SiC MOSFET Transistor X- Section Source (N14) # Athena simulation source p- well poly gate N - drain epitaxyt Doping Concentration [cm - 3 ] Voltage blocking p- well (Al27) V th adjust p- well (Al27) Depth [µm] Simulation- based technology development to cut cycles of learning Flexibility of design variations for special applications Thick Al- Cu metallization for interconnect and bond pads Dual layer metal process integration for maximized packing density Thick final passivation for maximum reliability

15 Simulated vs. Measured Athena P- well implant for V th adjust Deep p- well for voltage blocking Source implant for optimized ohmic formation P- well contact implant Guard- ring implant V 1mA [V] Atlas y = x R² = simulation (offset) B6523 w1 B6523 w2 B6523 w3, w4 B keV B keV Linear (simulation (offset)) V th adjust implant dose

16 What Makes A High Speed Switch Typical Transistor Gain Characteristics f t Transistor switching speed f max Transistor power gain f t C gs g + m C gd f max r g ft C gd f t

17 g m Optimization g 10A, 10V g m g m g gm' = 1+ g m m R s R s R 10A, 20V Packing density (without increasing parasitic capacitance) Source resistance minimized (g m vs. R DS(ON) plot) o Perfection of source contact formation o Push the limit on gate/source overlap without trading manufacturability

18 Future Optimization Parasitic capacitance reduction Potential tradeoff with breakdown examined field plating by pad metal

19 C gd Reduction For Interdigitated SiC MOSFET current low parasitic No change in integration (drawn poly layer change) 50% C gd reduction No impact on JFET resistance (p- well spacing) Most importantly, no implication on gate oxide

20 Field Plating Of Pad Metal vs. Poly/TEROX (drain=980v, gate=pwell=0v) 2D contours of electric field source metal pad baseline BPSG=6kÅ BPSG=10kÅ BPSG=20kÅ Terox=6kÅ No pad metal above gate poly source metal pad source metal pad BPSG BPSG BPSG gate poly gate poly gate poly gate poly gate poly gate poly terox gate poly 1D cutline 1D electric field cutline through highest field region 1D electric field cutline through highest field region poly oxide SiC (drain epitaxy) poly oxide SiC (drain epitaxy)! E [V/cm] zoom! E [V/cm] No pad metal above gate poly BPSG=20kÅ BPSG=10kÅ BPSG=6kÅ No pad metal above gate poly Terox=6kÅ baseline baseline Distance [µm] Distance [µm]

21 Breakdown Voltage Of Various FP Schemes baseline 100% 90% Terox=6kÅ 80% log(i D ) [A/µm] BPSG=20kÅ BPSG=10kÅ BPSG=6kÅ Normalized BV [V] 70% 60% 50% 40% 30% 20% 10% 0% V D [V] baseline Terox=6kÅ BPSG=6kÅ BPSG=10kÅ BPSG=20kÅ

22 DC Characteristics Key to Switching Performance

23 Best in Class R DS(ON) vs. Temperature Normalized R DS(ON) Competitor V, 30A, 80mΩ T j [ C] Competitor V, 36A, 80mΩ Microsemi APT40SM120B 1200V, 40A, 80mΩ Lower R DS(ON) at temperature provides higher ceiling for continuous current rating

24 R G & Dynamic Performance Turn- On Turn- Off +20V +20V Gate driver Gate driver ON i g OFF MOSFET R G(MOSFET) R G(MOSFET) OFF ON C iss C iss MOSFET i g i g ( t = 0) = R G 20V + R ( driver) G( MOSFET ) i g ( t = 0) = R G 20V + R ( driver) G( MOSFET ) High gate resistance limits available charging current, consequently, retards transistor switching performance

25 Ultra Low Gate Resistance Minimized Switching Energy Loss & Higher Switching Frequency Competition High R G Microsemi Low R G Oscillation- free with minimal external R G APT50SM120B 50mΩ APT40SM120B 80mΩ Competitor 2 Competitor 1 Microsemi

26 High Transconductance (g m ) Cuts t on Microsemi competitor 1 I D [A] g m [S] VD=0.1V V G [V] 2 g m at the start of the turn- on process

27 High Transconductance (g m ) Cuts t on V G V D ,000 10,000 8,000 6,000 4,000 I D P on Microsemi (R G =7Ω) Competitor 1 (R G =0Ω) competitor 1 2,000 Microsemi Time [ns] Intentionally added external R g to show case high g m I d [A] 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 Microsemi 50mΩ (7Ω) Microsemi 50mΩ (0) Comp 1 (0) Microsemi solid=7ω dashed=0 Ω competitor 1 Sub- threshold slope: Shallow junction and good interface quality V g [V] Superior sub- 1A g m jumps start the turn- on process

28 Superior Dynamic Performance

29 Switching Energy Benchmark Total Switching Energy [mj] Microsemi 80mΩ Microsemi 50mΩ Competitor 2 80mΩ Current [A] T c =25 C; V DD =900V >30% less switching loss translates to cooler dynamic operations and capability for higher switching frequencies

30 Maximum Switching Frequency, f max 1.E+06 Total switching time 5% switching period 1.E+05 Microsemi APT50SM120B 1200V, 50A, 50mΩ Limitation 1 f fmax [Hz] 1.E+04 Competitor V, 30A, 80mΩ Thermally limited switching frequency 1.E+03 T j =150 C; T c =75 C I D ID [A] Microsemi APT40SM120B 1200V, 40A, 80mΩ Limitation 2 Dynamic performance breakaway enablers: Superior E on (t on ) due to high g m, ultra low R G Superior E off due to extremely low R G (yet oscillation free with very low external R G ) Low R DS(ON) at high temperatures extends switching frequency and current capability

31 Outstanding Ruggedness

32 Superior Short Circuit Withstand Microsemi Competitor 1 Microsemi s 80mΩ SiC MOSFET demonstrates 25% longer short circuit capability

33 Superb Avalanche Ruggedness Unclamped inductive load v = L di dt DUT VDD I d =20A V g =20V Max V d =2225V APT40SM120B (1200V/80mΩ/40A) n + source pw 1 gate poly n + source pw 1 p + p + gr 2.3J (20A) p-well 2 p-well 2 n-epitaxy n-substrate Competitor1 not UIS rated, competitor2 GEN2 1200V/80mΩ/36A E a =1J (20A)

34 Body Diode Forward Current Surge 500A peak forward current surge through body diode Ch1 Vds 5V/div. Ch2 voltage surge generator 1kV/div. Ch3 current surge generator 1kA/div. Ch4 current body diode State of New York test ANSI/IEEE C62.41: Surge in body diode goes up to 500A for 100µs Typical operation test: 25 surges To push the envelope: 2000 pulses of body diode forward surge 700V SiC MOSFET survived this extreme body diode surge torture with no change in device

35 Reliable Technology Platform

36 SiC MOSFET Technology Reliability Assessment Field- driven intrinsic weakness in bulk SiC materials SiC gate oxide, interface quality Gate oxide lifetime Stacking faults growth in epitaxial wafers High temperature reverse bias (HTRB) 2000hrs V DD 175 C Positive bias temperature instability (PBTI) 2000 hrs V G 175 C Negative bias temperature instability (NBTI) 2000 hrs V G =- 175 C Time- dependent dielectric breakdown (TDDB) Constant current stress to breakdown Body diode forward bias stress 100A/cm 2 forward current through body diode Post 2000 hrs no key parameter drift Post 2000 hrs Vth less than 15% Post 2000 hrs devices remain normally- off Q BD equivalent to silicon MOSFET R DS(ON) remains unchanged post 160hrs of continuous stress

37 175 C, 960V (post 2000 hrs) Field- driven intrinsic weakness in bulk SiC materials High temperature reverse bias (HTRB) 2000hrs 175 C Δ(V th, V D(ON), R DS(ON), BVDSS) [%] Microsemi APT50SM120B (50mΩ) >2000hrs Post 2000 hrs no key parameter drift No degrading drift of key electrical parameters post 2000 hrs

38 SiC gate oxide, interface quality Gate Oxide 175 C, V G =+20V (PBTI post 2000hrs) Microsemi APT50SM120B (1200V, 50A, 50mΩ) Positive bias temperature instability (PBTI) 2000 hrs 175 C Δ(V th ) [V] Competitor 1 Competitor hrs -0.6 Post 2000 hrs Vth less than 15% E+00 1.E+01 1.E+02 1.E+03 1.E+04 Accumulated stress [hrs] Device V th drift less than 15% post 2000 V G =+20V, 175 C (pre- stress V th =2.7 ± 0.050V)

39 SiC gate oxide, interface quality Gate Oxide 175 C, V G =- 20V (NBTI post 2000hrs) >2000hrs Microsemi APT50SM120B (1200V, 50A, 50mΩ) Negative bias temperature instability (NBTI) 2000 hrs VG=- 175 C Δ(V th ) [V] Competitor Post 2000 hrs devices remain normally- off -9 Gate driver negative V G typically 0 ~ - 5V E+00 1.E+01 1.E+02 1.E+03 1.E+04 Accumulated stress [hrs] Device remains normally- off post 2000 V G =- 20V, 175 C (pre- stress V th =2.78 ± 0.070V)

40 Time- Dependent Dielectric Breakdown (TDDB) Gate oxide lifetime Microsemi VG Competitor 1 VG Time- dependent dielectric breakdown (TDDB) Constant current stress to breakdown Q BD [C/cm 2 ] Competitor 1 QBD QBD QBD equivalent to silicon MOSFET Microsemi Constant current stress for all DUTs Si MOSFET Q BD ~ 15-20C/cm 2 (green dashed line)

41 Gate Oxide Reliability Intrinsic Aging Lifetime Equivalent to Silicon ~300+ Years of Lifetime Competitor 1 SiC MOSFET Competitor 1 Silicon MOSFET Microsemi SiC MOSFET Competitor 1 process evolution

42 Body Diode Forward Stress Stacking faults growth in epitaxial wafers Expansion of Shockley stacking faults (SSFs) during forward- bias device operation (stressing) min periods of 14 A/cm 2 Body diode forward bias stress I F [A] Stressed at room temperature 100A/cm 2 forward current through body diode Subsequent periods of annealing at 505 C RDSON remains unchanged post 160hrs of continuous stress 100µm 100µm SiC MOSFET V F [V] J.D. Caldwell et. al., 2008 NRL Review ELECTRONICS AND ELECTROMAGNETICS High forward current density through body diode Body diode on- voltage, series resistance unchanged with stress time

43 Medium- Current Body Diode Forward Stress 8A G/S tied; 8A continuous forward current through body diode Style of curves=different part # IDSS at 1200V V th V DS(ON) R DS(ON) BVDSS Microsemi APT40SM120B (1200V, 40A, 80mΩ) I G at 20V Accumulated stress [hr] Accumulated stress [hr] No evidence of Shockley stacking faults high quality epitaxial wafers

44 High- Current Body Diode Forward Stress 20A 20A continuous forward current through body diode Δ(V th, V D(ON), R DS(ON), BVDSS) [%] 10% 8% 6% 4% 2% 0% -2% -4% -6% -8% G/S tied (solid) G/D tied (dashed) IF=20A, VGS=- 5V Microsemi APT40SM120B (1200V, 40A, 80mΩ) -10% 1E+01 1E+02 1E+03 Accumulated stress [hr] No evidence of Shockley stacking faults high quality epitaxial wafers

45 Summary Microsemi SiC MOSFETs Microsemi s Best-in-Class SiC MOSFETs enable customers to design ultra efficient high power electronics Microsemi Advantages Best-in-class R DS(ON) vs. temperature Ultra low gate resistance Low conduction losses Low switching losses Short Circuit Withstand Rating Single Pulse Avalanche Rating Reliable technology platform 2015 Microsemi Corporation

46 Die Size Scaling Larger=More capacitance=more Switching Loss?

47 Larger=More Switching Loss? Die Size vs. Switching 25 C 1200V/40A (dashed) 1200V/80A (solid) Small transistor shows 112% more switching loss at 150A <85A, switching loss is independent of transistor size 40A 80A equal E total 40A E on 80A 80A E Ooff 40A

48 Difference Between On/OFF (not described by Q g characteristic) Inductive switching IV turn- on I d [A] turn- off V d [V] Turn- on: An energizing process with transistor g m generator hard at work Turn- off: Capacitive Area under the dynamic load- line: E on >E off

49 Gate Charge (Q g ) Characteristic linear saturation s C C A < C C! S A > S c ON s A 450 OFF 700 Plateau voltage: g m (but note: Q g characteristic has no g m action, i.e., high g m does not speed things up due to the very choked gate current contrast to real switching. Further, more gate charge does not mean higher switching loss necessarily) Slope of V g in region A: Capacitance at weak turn- on (C A ) Flatness of V g in region B: Degree of saturation Slope of V g in region C: Capacitance at strong turn- on (C C )! No contribution to switching power loss (V d =0) C gg C C V th C A V gs=d C gd 0 10V V ds=g 1kV

50 Low Current Q 10A V d APT40 (dashed) APT80 (solid) Transistor size APT80=2 APT40 V g [V] δ=3v 9V 6V V d [V] No E off APT80 Apparent: Bigger transistor=more capacitance (V g slope, duration) Not so obvious: Bigger transistor=lower V plateau =Higher g m Turn- on: g m - dictated process! bigger transistor wins Turn- off: E off worse for the bigger transistor (E off is purely capacitance) E total remains constant (current/capacitance scaling)! equal for big and low/ moderate currents

51 High Switching Current APT80(1200V/80A) APT40(1200V/40A) +20V +18V +16V V +20V +18V +16V I D [A] V +12V +14V +12V V DS [V] +10V +8V +8V +6V +6V ON OFF V G required for a larger transistor to support a given current is a given high switching current, V G of a smaller transistor is required to climb to a higher value to support I D in the turn- on process! Lag in V D fall time to complete turn- on! E on

52 I D - V G Characteristic I D [A] APT80 APT V G [V] A smaller transistor is required to reach for higher voltage (V G, V D ) to support a given current The disparity between the transistor sizes grows as current increases

53 High vs. Low Switching Current Q g (for APT40SM) V d 60A V g [V] 10A V d [V] 60A 10A In contrast to 10A o 60A pushes the transistor to higher V g (more saturated) to support current o Transistor struggles to support the current o Higher V d is required o Lag in V d fall results o Note the worse gate voltage slope indicative of higher gate capacitance at higher V g (no contriution to loss)

54 High Current Q 60A V d (APT40 vs. APT80) APT40 (dashed) V g [V] δ=4.25v 12.4V 8.15V APT80 (solid) V d [V] No E off APT80 Smaller transistor screaming for g m (requires higher V g to support high current) The falling of V d slows toward the end of Miller plateau! onset of saturation for smaller transistor to support current at a higher V d Lag in V d dissipates more power during turn- on

55 High Current Turn- On Lag 1200V/40A (dashed) 1200V/80A (solid) I a given high switching currents o Smaller transistor lags in g m! required to sweep to a higher voltage (V g, V d ) o Smaller transistor turn- on lag leads to higher turn- on switching loss V g, V d /10 [V] V d /10 V g 80A 40A I d [A] A smaller transistor can only support a high switching current at a higher V ds due to saturation, i.e., drain voltage never falls sufficiently leading to the increase of switching/conduction loss! conduction loss! a bigger transistor is needed P on [V] 80A 40A conduction loss due to saturation Time [s]

56 Transistor Size Scaling Summary Larger transistor! Lower conduction loss (R DS(ON) ) For a given low/moderate switching current! Equal E total high switching current! Larger transistor has lower switching loss At a switching current where drain voltage fails to complete its fall! Transistor size cannot support the current and a bigger transistor is required

57 A Word On V G APT80(1200V/80A) APT40(1200V/40A) +20V +18V +16V V +20V +18V +16V I D [A] V +12V +14V +12V V DS [V] +10V +8V +8V +6V +6V Similar to the sizing limitation to g m, increase V G expands range of switching current capability. Due to wide bandgap, SiC MOSFET is less than prime when V G starts to deviate too far less than 20V.

58 Microsemi 700V SiC MOSFET Benchmarked Against 700V Silicon Superjunction MOSFET Microsemi SiC MOSFET APT70SM070B: 700V, 53mΩ Silicon Superjunction MOSFET IPW65R045C7: 700V, 45mΩ

59 Thermal Friendly SiC MOSFET Normalized R DS(ON) (to 25 C) Silicon Superjunction MOSFET 700V/45mΩ T j [ C] SiC MOSFET 700V/53mΩ For silicon superjunction MOSFET, conduction loss deteriorates rapidly with temperature while SiC MOSFET remains temperature insensitive. Switching/conduction loss deteriorates at high current/temperature due to saturation

60 R DS(ON) vs. Temperature Normalized R DS(ON) (to 25 C) T j [ C] Channel mobility improves with temperature due to reduced scattering from interface states! Improves R DS(ON) with temperature Epitaxial layer resistance increases with temperature due to scattering! Deteriorates R DS(ON) with temperature The above two mechanisms compete as temperature increases Transistors with higher voltage rating (such as 1200V) would have worse R DS(ON) deterioration with increasing temperature! The deteriorating mechanism is more dominant for a thicker epi layer For 700V, the two mechanisms even out to produce a flat R DS(ON) vs. temperature! So much better than silicon superjunction MOSFET

61 Inductive Room Temperature (25 C) E total [μj] E on [μj] E off [μj] Silicon superjunction MOSFET 700V/45mΩ V G =+13V +20V % I d [A] I d [A] I d [A] Switching loss of silicon superjunction MOSFET matches that of SiC at room temperature when V g is allowed up to 20V E on is a strong function of V g due to g m Superior electron mobility of silicon together with larger die size allows high g m to carry the higher capacitance associated with die size g m superiority of silicon superjunction MOSFET is enhanced by gate bias up to 20V E off is not a function of gate bias (Q g post Miller plateau where V d =0) Lower capacitance translates into less switching loss for SiC MOSFET! Reason SiC MOSFET wins in total switching loss

62 Superjunction E total vs. Gate Bias (25 C) 1.5 Silicon superjunction MOSFET E 145A (normalized to SiC V G =20V) Silicon superjunction MOSFET V G [V] Silicon superjunction MOSFET switching loss is competitive (with that of SiC) when gate bias is allowed to 20V due to the increased advantage of g m to carry the extra capacitance associated with its die size

63 Gate Charge (Q g ) Characteristic linear saturation s C C A < C C! S A > S c ON s A 450 OFF 700 Plateau voltage: g m (but note: Q g characteristic has no g m action, i.e., high g m does not speed things up due to the very choked gate current contrast to real switching. Further, more gate charge does not mean higher switching loss necessarily) Slope of V g in region A: Capacitance at weak turn- on (C A ) Flatness of V g in region B: Degree of saturation Slope of V g in region C: Capacitance at strong turn- on (C C )! No contribution to switching power loss (V d =0) C gg C C V th C A V gs=d C gd 0 10V V ds=g 1kV

64 Silicon Superjunction MOSFET Q g ~ 1.5 V d 700V/53mΩ SiC MOSFET (dotted) 700V/45mΩ superjunction MOSFET (solid) 3E V/40A 2E-9 V g [V] V g V d [V] C rss [F] 1E-9 turn- on C A B Time [s] Plateau V g! silicon superjunction MOSFET lower! stronger g m (μ n, die size) Slope of V g in region A o SiC MOSFET steeper! lower input capacitance C iss in region A (V th ) o SiC breakdown field 7.3! Allows heavier doping for a given breakdown voltage o For a given breakdown voltage and R DS(ON)! SiC MOSFET has a smaller die size o Silicon superjunction MOSFET die size 1.67 Flatness of Miller plateau (region B) o Flat for silicon superjunction MOSFET! More saturation o Never flat for SiC MOSFET! Much less saturation! More current capability Region C slope of V g post Miller plateau (C gg of V g >V th )! No contribution to loss 0E+0 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 V ds=g [V]

65 Q g Characteristic Summary Features in gate charge characteristic Switching performance implication SiC MOSFET Silicon superjunction MOSFET g m plateau voltage turn- on loss - Input capacitance Miller capacitance Saturation slope(v g ) duration of Miller plateau (till V d falls sufficiently) flatness of plateau switching loss switching loss switching current, temperature capability + (die size, integration, layout) (+) (die size, integration, layout) + (die size, mobility) linear saturation s C C A < C C! S A > S c ON s A 450 OFF 700

66 Inductive Room Temperature (25 C) E total [μj] E on [μj] E off [μj] Silicon superjunction MOSFET 700V/45mΩ V G =+13V +20V % I d [A] I d [A] I d [A] Switching loss of silicon superjunction MOSFET matches that of SiC at room temperature when V g is allowed up to 20V E on is a strong function of bias due to g m Superior electron mobility of silicon together with larger die size allows high g m to carry the higher capacitance associated with die size g m superiority of silicon superjunction MOSFET is enhanced by gate bias E off is not a function of gate bias (Q g post Miller plateau) Lower capacitance translates into less switching loss for SiC MOSFET! Reason SiC MOSFET wins in total switching loss

67 Inductive Elevated Temperature (125 C) E total [μj] E on [μj] E off [μj] VG=+13V Silicon superjunction MOSFET 700V/45mΩ +20V +20V 110% % I d [A] I d [A] I d 125 C, E on advantage erodes for silicon superjunction MOSFET (contrast to room temperature) o g m degrades with temperature o Saturation worsens rapidly with temperature o Severe increase of R DS(ON) with temperature Normalized g m (to 25 C) CoolMOS 125 C CoolMOS 150 C SiC MOSFET 125 C SiC MOSFET 150 C VDD=0.5V V D =0.5V I D [A]

68 Intrinsic Series Input Resistance 1.3 Normalized R G Silicon superjunction MOSFET 700V/45mΩ SiC MOSFET 700V/53mΩ Temperature [ C] Silicon superjunction MOSFET die size 1.67 At room temperature, SiC MOSFET 1.4 mostly due to smaller die size Gate poly resistivity increases with temperature E off degrades with temperature similarly between the two in comparison

69 Inductive Switching Performance Over Temperature E total [μj] Solid: 25 C Symbol (dashed): 125 C red=sic MOSFET Silicon superjunction MOSFET 700V/45mΩ 125 C 25 C 125 C 25 C V g =13V V g 150A, 125 C Silicon superjunction MOSFET o V g =13V, 13% worse than 25 C o V g =20V, 15% worse than 25 C SiC MOSFET unchanged from 25 C I D [A] Silicon superjunction MOSFET switching loss deteriorates with temperature while SiC MOSFET remains unchanged Silicon superjunction MOSFET switching loss degrades over current more rapidly than SiC MOSFET at elevated temperature

70 Saturation Necessitates A Bigger SJ MOSFET C 150 C Silicon superjunction MOSFET 700V/45mΩ I D [A] C 25 C 125 C 150 C 50 0 APT 25 APT 125 APT 150 Cool 125 Cool 150C +20V V D [V] Silicon superjunction MOSFET switching current capability is limited at elevated temperature o Transistor saturation worsens with temperature! limits high current switching o Rapid increase of R DS(ON) with temperature

71 Inductive 125 C Silicon superjunction MOSFET 700V/45mΩ SiC MOSFET 700V/58mΩ V d /10 466V V d /10 466V V g, V d /10 [V] 700V 45mΩ 150 C DC 46A, pulsed 212A I d V g 20V I d [A] V g, V d /10 [V] 700V 53mΩ 175 C DC 70A, pulsed 165A I d V g 20V I d [A] Drain voltage of silicon sj MOSFET fails to settle to 0 rapidly during turn- on causing excessive switching energy loss (figured into E ON and E OFF ) Conduction loss of deteriorates rapidly with temperature

72 Saturation 150 C Silicon superjunction MOSFET 700V/45mΩ SiC MOSFET 700V/53mΩ 466V V d /10 I d 466V V d /10 I d V g, V d /10 [V] 700V 45mΩ 150 C DC 46A, pulsed 212A 20V I d [A] V g, V d /10 [V] 700V 53mΩ 175 C DC 70A, pulsed 165A 20V I d [A] V g V g

73 MOSFET Temperature, Current All 700V rated I D [A] SiC MOSFET exhibits minimal current saturation in contrast to silicon superjunction MOSFET. 25 C (solid) 150 C (dashed) All data taken at V g =20V Superjunction 19mΩ 25 C 150 C Superjunction 45mΩ SiC MOSFET 53mΩ 25V SiC MOSFET 53mΩ Superjunction MOSFET suffers severe saturation at high current and temperature, necessitates the adoption of a bigger device. For SiC MOSFET Superjunction 19mΩ Superjunction 45mΩ o No obvious degradation of saturation with temperature o Both conduction loss as well as switching loss are rather insensitive to temperature o Cost advantage in high current regime at elevated temperatures V DS [V]

74 Performance vs. Economics Apparently similar in R DS(ON) at room temperature o SiC MOSFET 700V/53mΩ o Silicon superjunction MOSFET 700V/45mΩ At elevated temperature and high switching current o Silicon superjunction MOSFET appears shrunk o 19mΩ silicon superjunction MOSFET 53mΩ SiC MOSFET Silicon superjunction MOSFET 700V/19mΩ=$1.2 Silicon superjunction MOSFET 700V/45mΩ=$0.85 SiC MOSFET 700V/53mΩ=$1

75 Body Diode Reverse Recovery V R =400V,I F =46A,di F /dt=60a/µs Current [A] SiC MOSFET Silicon superjunction MOSFET 700V/45mΩ Time [ns] SiC MOSFET exhibits insignificant body diode reverse recovery loss in comparison with silicon super junction transistor. Silicon superjunction MOSFET body diode reverse recovery characteristic presents EMI concerns.

76 Body Diode Forward Current Surge 500A peak body diode forward surge Ch1 V ds 5V/div. Ch2 voltage surge generator 1kV/div. Ch3 current surge generator 1kA/div. Ch4 current body diode State of New York test ANSI/IEEE C62.41: Surge in body diode goes up to 500A for 100µs Typical operation test: 25 surges To push the envelope: 2000 pulses of body diode forward surge 700V SiC MOSFET survived this extreme body diode surge torture with no change in device

77 Untouchable Avalanche Ruggedness Superjunction MOSFET max. 249mJ SiC MOSFET 1450mJ mJ V g =20V APT70SM070B I d =12A pass at 3500mJ Max V d =1150V 3.5J (12A) BVDSS increases with temperature Flat V d suggests SiC MOSFET remains cool at severe avalanche conditions fail at 4000mJ Note: Rohm 650V/120mΩ/29A SiC MOSFET not avalanche rated

78 Technology Benchmark Summary Silicon superjunction MOSFET R DS(ON) more than doubles (2.4 ) at 125 C while R DS(ON) of Microsemi s 700V SiC MOSFET remains constant At room temperature, silicon superjunction MOSFET exhibits o over 1.25 switching loss at V G =13V o 1.1 switching loss at V G =15V o equivalent switching performance to SiC MOSFET when V G is allowed up to 20V At elevated temperature of 125 C, silicon superjunction MOSFET o over 1.5 switching loss at V G =13V o 1.1 switching loss at V G =20V Switching current capability o becomes severely limited for silicon superjunction MOSFET at high current and elevated temperature due to transistor saturation o remains unchanged going from 25 C to 125 C for Microsemi s 700V SiC MOFSET At 25 C, 45mΩ silicon superjunction is equivalent to Microsemi s 53mΩ SiC MOSFET At 125 C, 19mΩ silicon superjunction is equivalent to Microsemi s 45mΩ SiC MOSFET SiC MOSFET demonstrates superb ruggedness o high current body diode forward surge of 300A for a DC 70A rated transistor o single pulse avalanche survival from 1450mJ to 3500mJ (249mJ max for silicon sj MOSFET)