SiC MOSFET & Diode Roadmap September 12, 2016 DPG-PDM

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1 Power Matters. TM SiC MOSFET & Diode Roadmap September 12, 2016 DPG-PDM 1

2 SiC Capabilities Vs. Silicon Power Matters. TM 2

3 SiC Epitaxial Wafer Cross-Polarization History doping stain Birefringence induced by lattice strain. A perfect crystal will produce a uniform appearance when viewed between crossed polarizers, as the polarized light rotation will be the same everywhere. Lattice strain induced by lattice defects, polytype inclusions, compositional in-homogeneities, etc. can all result in regions that induce locally different rotations of the polarized light. The local variations in light rotation are easily imaged with this technique, providing a picture of crystal quality. Power Matters. TM 3

4 Epitaxial Layer Thickness Thickness Target = 12.5um Gen2 Thickness Target = 10.5 Dow Gen 2 Dow Gen 2 Denko Gen 2 target Th ickness [μm] 1μm 18 Sep Jan Feb Mar 10 1 Apr Apr Jun 10 5 Aug 10 3 Feb Apr May Aug Nov Dec 11 5 Jan Feb Apr Jun Nov Feb Feb Mar Mar Mar 13 1 Apr Apr Apr May May Jun Jul 13 2 Aug Aug Sep Sep Sep Oct Oct Nov 13 3 Jan Jan Jan 14 7 Feb Mar Apr 14 9 May May Jun 14 Power Matters. TM 4

5 Epitaxial Layer Doping centration [cm -3 ] Dow Gen 2 Denko Gen 2 Dow Early Gen 2 Gen 2 Doping Target = 6E Doping Target = 5.3E15 Doping con target Dow Gen 2 29 Oct 22 Nov 3 Jan 24 Jan 25 Jan 7 Feb 31 Mar 17 Apr 9 May 22 May 30 Jun 18 Sep 29 Jan 22 Feb 12 Mar 1 Apr 16 Apr 16 Jun 5 Aug 3 Feb 29 Apr 26 May 1 Aug 2 Nov 19 Dec 5 Jan 22 Feb 9 Apr 26 Jun 5 Nov 20 Feb 26 Feb 13 Mar 15 Mar 20 Mar 1 Apr 19 Apr 23 Apr 10 May 30 May 28 Jun 19 Jul 2 Aug 30 Aug 3 Sep 13 Sep 27 Sep 17 Oct Power Matters. TM 5

6 Epitaxial Layer Surface Roughness Denko Gen 2 RMS Surface Roughn ness[å] 5Å 19 Dec 11 5 Jan Feb 12 9 Apr Jun 12 5 Nov Feb Feb Mar 15 Mar 20 Mar 1 Apr Apr Apr May 30 May 28 Jun Jul 13 2 Aug Aug 13 3 Sep Sep Sep Oct Oct Nov 13 3 Jan Jan Jan 14 7 Feb Mar 17 Apr 14 9 May May 30 Jun 14 Power Matters. TM 6 2 Nov 11

7 Epitaxial Layer Defect Count D [per Defect 100m 200 count m waf er] Power Matters. TM 7

8 Special Processing Contrast to Silicon Technology Dopant introduction by implant at elevated temperatures Dopant activation, implant damage anneal at high temperatures No diffusion High temperature gate oxidation Above translates into all layer removal post dopant introduction for electrical activation Alignment is critical E220 Production Implanter CentroTherm CHV-100 Post Implant Annealing to 1700 C Hi Temp Oxidation SiC MOSFET Gate Oxidation Power Matters. TM 8

9 SiC MOSFET Transistor X-Section p-well source poly gate N - drain epitaxyt Doping Concentra ation [cm -3 ] Source (N14) # Athena simulation Voltage blocking p-well (Al27) V th adjust p-well (Al27) Depth [µm] Simulation-based technology development to cut cycles of learning Flexibility of design variations for special applications Thick Al-Cu metallization ti for interconnect t and bond pads Dual layer metal process integration for maximized packing density Thick final passivation for maximum reliability Power Matters. TM 9

10 Process Integration P-well implants for reduced R DS(ON) contribution from JFET region o V th adjustment implant o Voltage blocking implant Balance between guard-ring, p-well voltage blocking enables UIS capability Topology conforming backend metallization for high yield Mask 1 M2 M1 p-well 1 p-well pw 1 1 pw 1 M2 p-well 2 p-well 2 n-epitaxy n-epitaxy n-substrate n-substrate M2 (A) (B) M1 n + source pw n + source 1 pw n + source 1 pw 1 M2 Mask 3 n + source pw 1 p + p + n + source pw 1 gate poly n + source pw 1 p + p + p-well 2 p-well 2 gr p-well 2 n-epitaxy p-well 2 p-well 2 n-epitaxy p-well 2 n-epitaxy n-substrate n-substrate n-substrate (C) (D) Power Matters. TM 10

11 Microsemi SiC MOSFETs Voltage Current R DS(ON) Part Number Package Samples Availability 700V 35A ~100mΩ APT35SM70B APT35SM70S New APT70SM70B 700V 70A 53mΩ Ω APT70SM70S APT70SM70J TO-247 D3 Mid-August TO-247 D3 Mid-August SOT-227 APT130SM70B TO V 130A 33mΩ New APT130SM70J SOT-227 End-July 1200V 25A 140mΩ APT25SM120B APT25SM120S TO-247 D3 Early-August 1200V 40A 80mΩ 1200V 80A 40mΩ APT40SM120B APT40SM120S APT40SM120J TO 247 D3 SOT 227 Mid-June then Early-July APT80SM120B TO-247 Mid-June APT80SM120S D3 then APT80SM120J SOT-227 Mid-July 1700V 5A 800mΩΩ APT5SM170B APT5SM170S TO-247 D3 Early-October 2016 Microsemi Corporation Power Matters. TM 12

12 What Makes A High Speed Switch Typical Transistor Gain Characteristics f t f Transistor power gain f max Transistor switching speed f t C gs g m C gd f max ft r C g C gd f t Power Matters. TM 13

13 g m Optimization 10V g 10A, 1 g m g m g m' 1 g 1 g m m R s R s R 10A, 20V Packing density (without increasing parasitic capacitance) Source resistance minimized (g m vs. R DS(ON) plot) o Perfection of source contact formation o Push the limit on gate/source overlap without trading manufacturability Power Matters. TM 14

14 DC Characteristics Key to DC Characteristics Key to Switching Performance

15 Best in Class R DS(ON) vs. Temperature Normalize ed R DS(ON) Competitor V, 30A, 80mΩ T j [ C] Competitor V, 36A, 80mΩ Microsemi APT40SM120B 1200V, 40A, 80mΩ Lower R DS(ON) at temperature provides higher ceiling for continuous current rating Power Matters. TM 16

16 R G & Dynamic Performance Turn-On Turn-Off +20V +20V Gate driver Gate driver ON i g OFF MOSFET OFF R G(MOSFET) ON R G(MOSFET) MOSFET C iss i g C iss i g t 0 R G 20 V 20 V ig t 0 R R R driver G MOSFET G driver G MOSFET High gate resistance limits available charging current, consequently, retards transistor switching performance Power Matters. TM 17

17 Ultra Low Gate Resistance Minimized Switching Energy Loss & Higher Switching Frequency R G (Ω) Competition High R G Microsemi Low R G Oscillation-free with minimal external R G APT50SM M120B 50m Ω APT40SM M120B 80m mω Compet titor 2 Compet titor 1 Microsemi Power Matters. TM 18

18 High Transconductance (g m ) Cuts t on Microsemi competitor 1 I D D [A] g m [S] VD=0.1V V G [V] 2 g m at the start of the turn-on process Power Matters. TM 19

19 High Transconductance (g m ) Cuts t on Intentionally added external Microsemi (R G =7Ω) R g to show case high g m Competitor 1 (R G =0Ω) 10 V G 5 0 I D ,000 10,000 P on 8,000 6,000 competitor 1 4,000 2,000 Microsemi Time [ns] 1.E+02 1.E+01 V D 1E+00 1.E+00 I d [A] 1.E-01 1.E-02 Microsemi 50mΩ (7Ω) Microsemi 50mΩ (0) Comp 1 (0) Microsemi solid=7ω dashed=0 Ω competitor 1 Sub-threshold slope: Shallow junction and good interface quality V g [V] Superior sub-1a g m jumps start the turn-on process Power Matters. TM 20

20 Maximum Switching Frequency, f max 1.E+06 Total switching time 5% switching period 1.E+05 Microsemi APT50SM120B 1200V, 50A, 50mΩ Limitation 1 f fmax [Hz] 1.E+04 Competitor V, 30A, 80mΩ Thermally limited switching frequency Microsemi APT40SM120B 1200V, 40A, 80mΩ Limitation 2 1.E+03 T j =150 C; T c =75 C I D ID [A] Dynamic performance breakaway enablers: Superior E on (t on ) due to high g m, ultra low R G Superior E off due to extremely low R G (yet oscillation free with very low external R G ) Low R DS(ON) at high temperatures extends switching frequency and current capability Power Matters. TM 21

21 Superior Short Circuit Withstand Microsemi Competitor 1 8.5µs Microsemi s s 80mΩ SiC MOSFET demonstrates 25% longer short circuit capability Power Matters. TM 22

22 Superb Avalanche Ruggedness Unclamped inductive load v L di dt DUT VDD V g =20V I d =20A Max V d =2225V APT40SM120B (1200V/80mΩ/40A) n + source pw 1 gate poly n + source pw 1 p + p + gr 2.3J (20A) p-well 2 p-well 2 n-epitaxy n-substrate Competitor1 not UIS rated, competitor2 GEN2 1200V/80mΩ/36A E a =1J (20A) Power Matters. TM 23

23 SiC MOSFET Technology Reliability Assessment Field-driven intrinsic weakness in bulk SiC materials SiC gate oxide, interface quality Gate oxide lifetime Stacking faults growth in epitaxial wafers High temperature reverse bias (HTRB) 2000hrs V DD 175 C Positive bias temperature instability (PBTI) 2000 hrs V G 175 C Negative bias temperature instability (NBTI) 2000 hrs V G 175 C Timedependent dielectric breakdown (TDDB) Constant current stress to breakdown Body diode forward bias stress 100A/cm 2 forward current through body diode Power Matters. TM 24

24 Die Size Scaling Larger=More capacitance=more Switching Loss?

25 Difference Between On/OFF (not described by Q g characteristic) Inductive switching IV turn-on I d [A] turn-off V d [V] Turn-on: An energizing process with transistor g m generator hard at work Turn-off: Capacitive Area under the dynamic load-line: E on >E off Power Matters. TM 26

26 Gate Charge (Q g ) Characteristic linear saturation s C C A < C C S A > S c ON s A 450OFF 700 Plateau voltage: g m (but note: Q g characteristic has no g m action, i.e., high g m does not speed things up due to the very choked gate current contrast to real switching. Further, more gate charge does not mean higher switching loss necessarily) Slope of V g in region A: Capacitance at weak turn-on (C A ) Flatness of V g in region B: Degree of saturation Slope of V g in region C: Capacitance at strong turn-on (C C ) No contribution to switching power loss (V d =0) C gg C C C gd C A 10V 1kV V th V gs=d V ds=g Power Matters. TM 27

27 Low Current Q 10A 25 V d 40A (10A) VG 80A (10A) VG 1E+03 40A (10A) VD 80A (10A) VD 20 APT40 (dashed) APT80 (solid) 1E+02 Transistor size APT80=2 APT40 V g [V] δ=3v V] Vg [V V 6V 5 1E+01 1E+00 V d [V] VD [V] 1E E-5 00E+0 0.0E+0 50E-5 5.0E 5 10E-4 1.0E 15E-4 1.5E 20E-4 2.0E 25E-4 2.5E -5 Time [s] No E off APT80 1E-02 Apparent: Bigger transistor=more capacitance (V g slope, duration) Not so obvious: Bigger transistor=lower V plateau =Higher g m Turn-on: g m -dictated process bigger transistor wins Turn-off: E off worse for the bigger transistor (E off is purely capacitance) E total remains constant (current/capacitance scaling) equal for big and low/moderate currents Power Matters. TM 28

28 High Switching Current APT80(1200V/80A) APT40(1200V/40A) +20V +18V +16V V +20V +18V V I D [A] V V V DS [V] +8V +8V +6V +6V ON 450 OFF 700 V G required for a larger transistor to support a given current is a given high switching current, V G of a smaller transistor is required to climb to a higher value to support I D in the turn-on process Lag in V D fall time to complete turnon E on Power Matters. TM 29

29 High vs. Low Switching Current Q g (for APT40SM) 25 APT40 (10A) VG APT40 (60A) VG V d APT40 (10A) VD APT40 (60A) VD 1E E+02 V g [V] V] Vg [V A 60A 1E+01 V d [V] VD [V] 60A 5 10A 1E E-5 00E+0 0.0E+0 50E-5 5.0E 5 10E-4 1.0E 15E-4 1.5E Time [s] -5 1E-01 In contrast to 10A o 60A pushes the transistor to higher V g (more saturated) to support current o Transistor struggles to support the current o Higher V d is required o Lag in V d fall results o Note the worse gate voltage slope indicative of higher gate capacitance at higher V g (no contriution to loss) Power Matters. TM 30

30 High Current Q 60A (APT40 vs. APT80) V d APT40 (dashed) APT40 (60A) VG APT80 (60A) VG APT40 (60A) VD APT80 (60A) VD 1E+03 1E+02 V g [V] ] Vg [V δ=4.25v V V APT80 (solid) 1E+01 1E+00 V d [V] 5 1E E-5 50E5 00E+0 0.0E+0 50E5 5.0E-5 10E4 1.0E-4 15E4 1.5E-4 20E4 2.0E-4 25E4 2.5E-4-5 Time [s] No E off APT80 1E-02 Smaller transistor screaming for g m (requires higher V g to support high current) The falling of V d slows toward the end of Miller plateau onset of saturation for smaller transistor to support current at a higher V d Lag in V d dissipates more power during turn-on Power Matters. TM 31

31 High Current Turn-On a given high switching currents o Smaller transistor lags in g m required to sweep to a higher voltage (V g, V d ) o Smaller transistor t turn-on lag leads to higher turn-on switching loss A smaller transistor can only support a high switching current at a higher V ds due to saturation, i.e., drain voltage never falls sufficiently leading to the increase of switching/conduction loss conduction loss a bigger transistor is needed V d /10 [V] VG G, VD/10 [V] P on [V] V g, PON [W] V/40A (dashed) 1200V/80A (solid) V d /10 d V g 80A 80A 40A 40A I d I d [A] ID[A] conduction loss due to saturation 0 1E 8 1E 7 1E 6 Time [s] [s] Power Matters. TM 32

32 Transistor Size Scaling Summary Larger transistor Lower conduction loss (R DS(ON) ) For a given low/moderate switching current Equal E total high switching current Larger transistor has lower switching loss At a switching current where drain voltage fails to complete its fall Transistor size cannot support the current and a bigger transistor is required Power Matters. TM 33

33 Microsemi 700V SiC MOSFET Benchmarked Against 700V Silicon Superjunction MOSFET Microsemi SiC MOSFET APT70SM070B: 700V, 53mΩ Silicon Superjunction MOSFET IPW65R045C7: 700V, 45mΩ

34 Thermal Friendly SiC MOSFET DS(ON) Norm malized R D (to 25 C) Silicon Superjunction 2.2 MOSFET V/45mΩ SiC MOSFET V/53mΩ T j [ C] For silicon superjunction MOSFET, conduction loss deteriorates rapidly with temperature while SiC MOSFET remains temperature insensitive. Switching/conduction loss deteriorates at high current/temperature due to saturation Power Matters. TM 35

35 Thermal Friendly SiC MOSFET DS(ON) Norm malized R D (to 25 C) Silicon Superjunction 2.2 MOSFET V/45mΩ SiC MOSFET V/53mΩ T j [ C] For silicon superjunction MOSFET, conduction loss deteriorates rapidly with temperature while SiC MOSFET remains temperature insensitive. Switching/conduction loss deteriorates at high current/temperature due to saturation Power Matters. TM 36

36 V g [V] Silicon Superjunction MOSFET Q g ~ V/53mΩ SiC MOSFET (dotted) 1E+3 700V/45mΩ superjunction MOSFET (solid) 3E V d V g C 1E+2 1E+1 V d [V] 1E+0 5 B 0 A 0.0E+0 5.0E 5 1.0E 4 1.5E 4 2.0E 4 2.5E 4 5 Time [s] 1E 1 C rss [F] 2E-9 1E V/40A turn-on 0E+0 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 V ds=g [V] Plateau V g silicon superjunction MOSFET lower stronger g m (μ n, die size) Slope of V g in region A o SiC MOSFET steeper lower input capacitance C iss in region A (V th ) o SiC breakdown field 7.3 Allows heavier doping for a given breakdown voltage o For a given breakdown voltage and R DS(ON) SiC MOSFET has a smaller die size o Silicon superjunction MOSFET die size 1.67 Flatness of Miller plateau (region B) o Flat for silicon superjunction MOSFET More saturation o Never flat for SiC MOSFET Much less saturation More current capability Region C slope of V g post Miller plateau (C gg of V g >V th ) No contribution to loss Power Matters. TM 37

37 Q g Characteristic Summary Features in gate charge characteristic Switching performance implication SiC MOSFET g m plateau voltage turn-on loss - Input capacitance Miller capacitance Saturation slope(v g ) duration of Miller plateau (till V d falls sufficiently) flatness of plateau switching loss switching loss switching current, temperature capability + (die size, integration, layout) (+) (die size, integration, layout) Silicon superjunction MOSFET + (die size, mobility) + - linear saturation - - s C C A < C C S A > S c ON s A 450OFF 700 Power Matters. TM 38

38 SiC MOSFET Module Product Roadmap The SiC MOSFET Module product range is based upon: Two die sizes S5F04 and S5F05 Two voltage ratings (700V and 1200V) APT70SM70D (700V /53 mohms typ, 60 mohms max) APT40SM120D (1200V/80 mohms typ, 100 mohms max) APT140SM70D (700V/30 mohms typ, 35 mohms max) APT80SM120D (1200V/40 mohms typ, 55 mohms max) Power Matters. TM 39

39 SiC MOSFET Module Product Roadmap Electrical configurations Boost Chopper Buck Chopper Single switch Phase leg Full bridge Triple phase leg Power Matters. TM 40

40 Packaging and power density To achieve the best switching performance and highest integration level a custom approach totally dedicated to the application efficiency target and mechanical constraints is the ultimate solution Duplicated +DC terminals Distributed +DC and DC terminals for ceramic capacitors decoupling G & S Thermal sensor OUT Duplicated -DC terminals Example of a high current, high frequency, high voltage SiC MOSFET phase leg Power Matters. TM 41

41 Packaging and Power Density Module performance and reliability depend on assembly material choice Material CTE (ppm/k) Thermal conductivity (W/m.K) Density (g/cc) CTE (ppm/k) Thermal conductivity (W/m.K) Rthjc (K/W) Base Substrate CuW AlSiC Cu Al 2 O AlN Si 3 N Silicon Die (120 mm 2 ) or SiC Die (40mm2) Cu/Al 2 O 3 17/7 390/ AlSiC/Al 2 O 3 7/7 170/ Cu/AlN 17/5 390/ AlSiC/AlN 7/5 170/ AlSiC/Si 3 N 4 7/3 170/ DBC substrateso ld er Jo int Dice Die Si SiC Solder Base More closely matched TCEs of materials increases module lifetime. Higher thermal conductivity maximizes thermal performance Engineered materials such as AlSiC provide substantial weight reductions (up to 50%) over traditional copper material. AlSiC and Alumina offer best CTE matching AlN and Si3N4 on AlSiC offer higher thermal performance with good CTE matching Power Matters. TM 42

42 Packaging and Power Density All full SiC Mosfet modules from Microsemi are built with Aluminium Nitride (AlN) substrate for best thermal performance Si3N4 substrates is offered as an option Any full SiC power module can be converted from a standard d copper base plate to an AlSiC base plate for extended operating temperature range and higher temperature cycling capability Power Matters. TM 43

43 Packaging and Power Density SiC technology is capable of high temperature operation All Microsemi SiC MOSFET modules use high temperature solder alloy for die attach as a standard to allow maximum junction temperature operation As SiC technology will improve, high temperature solder alloy will become a limitation it ti for extreme junction temperatures operation Ag sintering technology is the future for SiC devices assembly Power Matters. TM 44

44 Packaging and Power Density Basic Ag sintering process As printed ºC After sintering Organic cap Ag Nano particle During Sintering process solvents and organic cap escape, exposing pure silver core to allow particles to coalesce and form solid conductive Ag structure Power Matters. TM 45

45 Packaging and Power Density Ag is an ideal Die Attach Material Melting Tensile Thermal Electrical Density CTE Modulus range strength conductivity resistivity Material C g/cm 3 ppm/ C MPa GPa W/m.K µωcm Silver Pb5Sn2.5Ag Au20Sn Sn3.5Ag Ag paste is processed at 250 C 300 C under pressure to form pure Ag interface After processing, Ag paste acts as bulk Ag with a melting point of 962 C Density (85 to 90%) Thermal conductivity: W/m.K Electrical resistivity: µωcm No intermettallic phases formed Ag paste allows highest thermal performance and reliability Power Matters. TM 46

46 Thank You Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiationhardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable antitamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA USA Within the USA: +1 (800) Outside the USA: +1 (949) Sales: +1 (949) Fax: +1 (949) sales.support@microsemi.com Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided as is, where is and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Power Matters. TM 47

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