ADA4350. FET Input Analog Front End with ADC Driver. Data Sheet

Transcription

1 FET Input Analog Front End with ADC Driver ADA435 FEATURES Low noise, low input bias current FET input amplifier Very low input bias current: ±.25 pa typical at 25 C Low input voltage noise 92 nv/ Hz typical at Hz at 5 V 5 nv/ Hz typical at khz at ±5 V Gain bandwidth product: 75 MHz Input capacitance 3 pf typical, differential mode 2 pf typical, common mode Integrated gain switching Sampling and feedback switch off leakage: ±.5 pa typical Worst case ton/toff times: 5 ns typical/65 ns typical Integrated analog-to-digital converter (ADC) driver Differential mode and single-ended mode Adjustable output common-mode voltage 5 V to +3.8 V typical for ±5 V supply Wide output voltage swing: ±4.8 V minimum for ±5 V supply Linear output current: 8 ma rms typical for ±5 V supply SPI or parallel switch control of all functions Wide operating range: 3.3 V to 2 V Quiescent current: 8.5 ma typical (±5 V full system) APPLICATIONS Current to voltage (I to V) conversions Photodiode preamplifiers Chemical analyzers Mass spectrometry Molecular spectroscopy Laser/LED receivers Data acquisition systems GENERAL DESCRIPTION The ADA435 is an analog front end for photodetectors or other sensors whose output produces a current proportional to the sensed parameter or voltage input applications where the system requires the user to select between very precise gain levels to maximize the dynamic range. The ADA435 integrates a FET input amplifier, a switching network, and an ADC driver with all functions controllable via a serial peripheral interface (SPI) or parallel control logic into a single IC. The FET input amplifier has very low voltage noise and current noise making it an excellent choice to work with a wide range of photodetectors, sensors, or precision data acquisition systems. Its switching network allows the user individual selection of up to six different, externally configurable feedback networks; by using external components for the feedback network, the user can more easily match the system to their desired photodetector or sensor capacitance. This feature also allows the use of low thermal drift resistors, if required. The design of the switches minimizes error sources so that they add virtually no error in the signal path. The output driver can be used in either single-ended or a differential mode and is ideal for driving the input of an ADC. The ADA435 can operate from a single +3.3 V supply or a dual ±5 V supply, offering user flexibility when choosing the polarity of the detector. It is available in a Pb-free, 28-lead TSSOP package and is specified to operate over the 4 C to +85 C temperature range. Multifunction pin names may be referenced by their relevant function only. FUNCTIONAL BLOCK DIAGRAM FB FB FB2 FB3 FB4 FB5 SWA_OUT SWB_OUT VIN RF IN-N IN-P ADA435 S S S2 S3 S4 S SPI INTERFACE 27 S6 S7 S8 S9 S S 28 2 P M 3 26 VOUT VOUT SWA_IN FET AMP SWB_IN EN MODE LATCH/P SCLK/P SDO/P2 SDI/P3 CS/P4 SWITCHING NETWORK Figure. REF ADC DRIVER 247- Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADA435 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 ±5 V Full System... 3 ±5 V FET Input Amplifier... 4 ±5 V Internal Switching Network and Digital Pins... 5 ±5 V ADC Driver V Full System V FET Input Amplifier V Internal Switching Network and Digital Pins... 5 V ADC Driver... Timing Specifications... 3 Absolute Maximum Ratings... 5 Thermal Resistance... 5 Maximum Power Dissipation... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... 6 Data Sheet Typical Performance Characterisitics... 7 Full System... 7 FET Input Amplifier... 9 ADC Driver Test Circuits Theory of Operation Kelvin Switching Techniques Applications Information Configuring the ADA Selecting the Transimpedance Gain Paths Manually or Through the Parallel Interface Selecting the Transimpedance Gain Paths Through the SPI Interface (Serial Mode) SPICE Model... 3 Transimpedance Amplifier Design Theory Transimpedance Gain Amplifier Performance The Effect of Low Feedback Resistor RFx Using The T Network to Implement Large Feedback Resistor Values Outline Dimensions Ordering Guide REVISION HISTORY 3/6 Rev. A to Rev. B Change to Table /5 Rev. to Rev. A Changes to Table... 3 Changes to Table Deleted Figure 4; Renumbered Sequentially... 4 Changes to Table... 5 Changes to Table /5 Revision : Initial Version Rev. B Page 2 of 37

3 ADA435 SPECIFICATIONS ±5 V FULL SYSTEM TA = 25 C, +VS = +5 V, V S = 5 V, RL = kω differential, unless otherwise specified. Table. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth Gain (G) = 5, VOUT = 2 mv p-p 2 MHz G = 5, VOUT = 2 V p-p 2 MHz Slew Rate VOUT = 2 V step, % to 9% 6 V/µs HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) G = 5, fc = khz 95/ 4 dbc G = 5, fc = MHz 77/ 78 dbc DC PERFORMANCE Input Bias Current At 25 C ±.25 ± pa At 85 C ±8 ±25 pa INPUT CHARACTERISTICS Input Resistance Common mode GΩ Input Capacitance Common mode 2 pf Differential mode 3 pf Input Common-Mode Voltage Range Common-mode rejection ratio (CMRR) > 8 db V CMRR > 68 db V Common-Mode Rejection VCM = ±3. V 92 4 db OUTPUT CHARACTERISTICS Linear Output Current VOUT = 4 V p-p, 6 db spurious-free dynamic 8 ma rms range (SFDR) Short-Circuit Current Sinking/sourcing 43/76 ma Settling Time to.% G = 5, VOUT = 2 V step ns ANALOG POWER SUPPLY (+VS, VS) Operating Range V Quiescent Current Enabled 8.5 ma M disabled (see Figure ) 7 ma All disabled 2 µa Positive Power Supply Rejection Ratio 9 db Negative Power Supply Rejection Ratio 85 db DIGITAL SUPPLIES DVDD, DGND Digital Supply Range V Quiescent Current Enabled 5 µa Disabled.6 µa +VS to DGND Head Room 3.3 V Rev. B Page 3 of 37

4 ADA435 Data Sheet ±5 V FET INPUT AMPLIFIER TA = 25 C, +VS = +5 V, V S = 5 V, RL = kω, unless otherwise specified. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G = 5, VOUT = mv p-p 26 MHz G = 5, VOUT = 2 V p-p 24 MHz Gain Bandwidth Product 75 MHz Slew Rate VOUT = 2 V step, % to 9% V/µs Settling Time to.% G = 5, VOUT = 2 V step 28 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) f = khz, VOUT = 2 V p-p, G = 5 6/ 4 dbc f = MHz, VOUT = 2 V p-p, G = 5 83/ 93 dbc Input Voltage Noise f = Hz 85 nv/ Hz f = khz 5 nv/ Hz DC PERFORMANCE Input Offset Voltage 5 8 µv Input Offset Voltage Drift From 4 C to +85 C..6 µv/ C From 25 C to 85 C.. µv/ C Input Bias Current At 25 C ±.25 ± pa At 85 C ±8 ±25 pa Input Bias Offset Current At 25 C ±. ±.8 pa At 85 C ±.5 pa Open-Loop Gain VOUT = ±2 V 6 5 db INPUT CHARACTERISTICS Input Resistance Common mode GΩ Input Capacitance Common mode 2 pf Differential mode 3 pf Input Common-Mode Voltage Range CMRR > 8 db V CMRR > 68 db V Common-Mode Rejection Ratio VCM = ±3 V 92 5 V OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VOUT = VS ± % 6 ns Output Voltage Swing G = +2, RF = kω, RL open measured at FBx 3.6 to to +4.7 V G = +2, RF = kω, RL open measured at FBx 4.7 to to V Linear Output Current VOUT = 2 V p-p, 6 db SFDR 8 ma rms Short-Circuit Current Sinking/sourcing 4/45 ma POWER SUPPLY Operating Range V Positive Power Supply Rejection Ratio 9 9 db Negative Power Supply Rejection Ratio 9 9 db Rev. B Page 4 of 37

5 ADA435 ±5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS TA = 25 C, +VS = +5 V, V S = 5 V, unless otherwise specified. See Figure for feedback and sampling switches notation. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FEEDBACK/SAMPLE ANALOG SWITCH Analog Signal Range 5 +5 V Switch On-Resistance Feedback RON, FB For S to S2, VCM = V Ω TA = 85 C 95 Ω For S3 to S5, VCM = V Ω TA = 85 C 95 Ω Sampling RON, S For S6 to S8, VCM = V Ω TA = 85 C 39 Ω For S9 to S, VCM = V Ω TA = 85 C 388 Ω On-Resistance Match Between Channels Feedback Resistance ΔRON, FB VCM = V 2 5 Ω Sampling Resistance ΔRON, S VCM = V 2 4 Ω SWITCH LEAKAGE CURRENTS Sampling and Feedback Switch Off Leakage IS (OFF) ±.5 ±.7 pa TA = 85 C ±4 ±2 pa DYNAMIC CHARACTERISTICS Power-On Time ton DVDD = 5 V 76 ns DVDD = 3.3 V 8 ns Power-Off Time toff DVDD = 5 V 86 ns DVDD = 3.3 V 9 ns Off Isolation RL = 5 Ω, f = MHz Feedback Switches 92 db Sampling Switches 8 db Channel to Channel Crosstalk RL = 5 Ω, f = MHz 86 db Worst Case Switch Feedback Capacitance (Switch Off ) CFB (OFF). pf THRESHOLD VOLTAGES FOR DIGITAL INPUT PINS EN, MODE, DGND, LATCH/P, SCLK/P, SDO/P2, SDI/P3, CS/P4 Input High Voltage VIH DVDD = 5 V 2. V DVDD = 3.3 V.5 V Input Low Voltage VIL DVDD = 5 V.4 V DVDD = 3.3 V. V DIGITAL SUPPLIES DVDD, DGND Digital Supply Range V Quiescent Current Enabled 5 µa Disabled.6 µa +VS to DGND Head Room 3.3 V When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. B Page 5 of 37

6 ADA435 Data Sheet ±5 V ADC DRIVER TA = 25 C, +VS = +5 V, V S = 5 V, unless otherwise specified. See Figure for the P and M amplifiers. RL = kω when differential, and RL = 5 Ω when single-ended. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth When used differentially, VOUT =. V p-p 38 MHz When used differentially, VOUT = 2. V p-p 6 MHz When P is used, VOUT = 5 mv p-p 55 MHz When P is used, VOUT =. V p-p 7 MHz When M is used, VOUT = 5 mv p-p 45 MHz When M is used, VOUT =. V p-p 2 MHz Overdrive Recovery Time Positive recovery/negative recovery for P 2/8 ns Positive recovery/negative recovery for M / ns Slew Rate When differentially used, VOUT = 2 V step 57 V/µs When P or M is single-ended, VOUT = V step 3 V/µs Settling Time.% When used differentially, VOUT = 2 V step 95 ns When P is used, VOUT = V step 8 ns When M is used, VOUT = V step 8 ns NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) When used differentially, fc = khz, VOUT = 4 V p-p 5/ 9 dbc When used differentially, fc = MHz, VOUT = 4 V p-p 75/ 73 dbc When P is used, fc = khz, VOUT = 2 V p-p 2/ 8 dbc When P is used, fc = MHz, VOUT = 2 V p-p 75/ 73 dbc When M is used, fc = khz, VOUT = 2 V p-p 98/ 3 dbc When M is used, fc = MHz, VOUT = 2 V p-p 7/ 69 dbc Referred to Input (RTI) Voltage Noise For P, f = Hz 55 nv/ Hz For P, f = khz 5 nv/ Hz Referred to Output (RTO) Voltage Noise For P and M, f = Hz, measured at VOUT2 95 nv/ Hz For P and M, f = khz, measured at VOUT2 6 nv/ Hz Input Current Noise f = khz, referred to P. pa/ Hz DC PERFORMANCE Output Offset Voltage Differential.25.5 mv Output Offset Voltage Drift Differential.7 3 µv/ C Input Offset Voltage Single-ended, P only 5 8 µv Single-ended, M only 4 8 µv Input Offset Voltage Drift Single-ended, P only µv/ C Single-ended, M only µv/ C Input Bias Current P only at VIN pin 6 22 na P only at RF pin na M at REF pin 6 2 na Input Offset Current P only 6 26 na Open-Loop Gain P only, VOUT = ±2 V 2 2 db Gain M only V/V Gain Error % Gain Error Drift.6.9 ppm/ C INPUT CHARACTERISTICS Input Resistance VIN and REF 2 MΩ Input Capacitance VIN and REF.4 pf Input Common-Mode Voltage Range V Common-Mode Rejection Ratio For P, VCM = ±3. V 82 db Rev. B Page 6 of 37

7 ADA435 Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing RL = no load, single-ended ±4.8 ±4.83 V RL = 5 Ω, single-ended ±4.55 ±4.6 V Output Common-Mode Voltage Range V Linear Output Current P or M, VOUT = 2 V p-p, 6 db SFDR 8 ma rms Differential output, VOUT = 4 V p-p, 6 db SFDR 8 ma rms Short Circuit Current P or M, sinking/sourcing 43/76 ma Capacitive Load Drive When used differentially at each VOUTx, 3% overshoot, 33 pf VOUT = 2 mv p-p When P/M is used, 3% overshoot, VOUT = mv p-p 47 pf POWER SUPPLY Operating Range V Positive Power Supply Rejection Ratio For P 9 6 db For M 86 db Negative Power Supply Rejection Ratio For P 8 db For M 78 9 db P and M within this table refer to the amplifiers shown in Figure. Rev. B Page 7 of 37

8 ADA435 Data Sheet 5 V FULL SYSTEM TA = 25 C, +VS = 5 V, V S = V, RF = kω differential, unless otherwise specified. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G = 5, VOUT = 2 mv p-p 5 MHz G = 5, VOUT = V p-p 4 MHz Slew Rate VOUT = 2 V step, % to 9% 3 V/µs HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) G = 5, fc = khz 85/ 94 dbc G = 5, fc = MHz 66/ 75 dbc Input Voltage Noise f = Hz 92 nv/ Hz f = khz 4.4 nv/ Hz DC PERFORMANCE Input Bias Current At 25 C ±.35 ±.6 pa At 85 C ±8.5 ±3 pa INPUT CHARACTERISTICS Input Resistance Common mode GΩ Input Capacitance Common mode 2 pf Differential mode 3 pf Input Common-Mode Voltage Range CMRR > 8 db V CMRR > 68 db 3.9 V Common-Mode Rejection VCM = ±.5 V db OUTPUT CHARACTERISTICS Linear Output Current VOUT = V p-p, 6 db SFDR 9 ma rms Short-Circuit Current Sinking/sourcing, RL < Ω 4/63 ma Settling Time to.% G = 5, VOUT = 2 V step 3 ns POWER SUPPLY Operating Range V Quiescent Current Enabled 8 9 ma M disabled (see Figure ) 6.5 ma All disabled 2 µa Positive Power Supply Rejection Ratio 86 db Negative Power Supply Rejection Ratio 8 db DIGITAL SUPPLIES (DVDD, DGND) DVDD, DGND Digital Supply Range V Quiescent Current Enabled 5 µa Disabled.6 µa +VS to DGND Head Room 3.3 V Rev. B Page 8 of 37

9 ADA435 5 V FET INPUT AMPLIFIER TA = 25 C, +VS = 5 V, V S = V, RL = kω, unless otherwise specified. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G = 5, VOUT = mv p-p 25 MHz G = 5, VOUT = V p-p 24 MHz Gain Bandwidth Product 75 MHz Slew Rate VOUT = 2 V step, % to 9% 56 V/µs Settling Time to.% G = 5, VOUT = 2 V step 6 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) f = khz, VOUT = V p-p, G = 5 3/ 7 dbc f = MHz, VOUT = V p-p, G = 5 82/ 83 dbc Input Voltage Noise f = Hz 92 nv/ Hz f = khz 4.4 nv/ Hz DC PERFORMANCE Input Offset Voltage 25 8 µv Input Offset Voltage Drift From 4 C to +85 C..5 µv/ C From 25 C to 85 C.5 µv/ C Input Bias Current At 25 C ±.35 ±.6 pa At 85 C ±8.5 ±3 pa Input Bias Offset Current At 25 C ±.25 ±.25 pa At 85 C ±.4 pa Open-Loop Gain VOUT =.5 V to 3.5 V 98 2 db INPUT CHARACTERISTICS Input Resistance Common mode GΩ Input Capacitance Common mode 2 pf Differential mode 3 pf Input Common-Mode Voltage Range CMRR > 8 db V CMRR > 68 db 3.9 V Common-Mode Rejection Ratio VCM = ±.5V db OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VOUT = VS ± %, positive/negative 6/5 ns Output Voltage Swing G = +2, RF = kω, RL open measured at FBx.5 to to 3.66 V G = +2, RF = kω, RL open measured at FBx.27 to to 4.87 V Linear Output Current VOUT = V p-p, 6 db SFDR ma rms Short-Circuit Current Sinking/sourcing 32/38 ma POWER SUPPLY Operating Range V Positive Power Supply Rejection Ratio 9 db Negative Power Supply Rejection Ratio 86 db Rev. B Page 9 of 37

10 ADA435 Data Sheet 5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS TA = 25 C, +VS = 5 V, V S = V, unless otherwise specified. See Figure for sampling and feedback switches position. Table 7. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FEEDBACK/SAMPLE ANALOG SWITCH Analog Signal Range 5 V Switch On Resistance Feedback RON, FB S to S2, VCM = 2.5 V Ω TA = 85 C 382 Ω S3 to S5, VCM = 2.5 V Ω TA = 85 C 384 Ω Sampling RON, S S6 to S8, VCM = 2.5 V 6 77 Ω TA = 85 C 762 Ω S9 to S, VCM = 2.5 V Ω TA = 85 C 764 Ω On-Resistance Match Between Channels Feedback Resistance ΔRON, FB VCM = 2.5 V 3 2 Ω Sampling Resistance ΔRON, S VCM = 2.5 V 3 23 Ω SWITCH LEAKAGE CURRENTS Sampling and Feedback Switch Off Leakage IS (OFF) ±.4 ±.2 pa TA = 85 C ±3 ±8 pa DYNAMIC CHARACTERISTICS Power-On Time ton DVDD = 3.3 V 5 ns Power-Off Time toff DVDD = 3.3 V 65 ns Off Isolation RL = 5 Ω, f = MHz Feedback Switches 93 db Sampling Switches 6 db Channel to Channel Crosstalk RL = 5 Ω, f = MHz 83 db Worst Case Switch Feedback Capacitance (Switch Off ) CFB (OFF). pf THRESHOLD VOLTAGES FOR DIGITAL INPUT PINS EN, MODE, DGND, LATCH/P, SCLK/P, SDO/P2, SDI/P3, CS/P4 Input High Voltage VIH DVDD = 5 V 2. V DVDD = 3.3 V.5 V Input Low Voltage VIL DVDD = 5 V.4 V DVDD = 3.3 V. V DIGITAL SUPPLIES DVDD, DGND Digital Supply Range V Quiescent Current Enabled 5 µa Disabled.6 µa +VS to DGND Head Room 3.3 V When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. B Page of 37

11 ADA435 5 V ADC DRIVER TA = 25 C, +VS = 5 V, VS = V, unless otherwise specified. See Figure for the P and M amplifiers, RL = kω when differential, and RL = 5 Ω when single-ended. Table 8. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth When used differentially, VOUT =. V p-p 33 MHz When used differentially, VOUT = 2. V p-p 6 MHz When P is used, VOUT = 5 mv p-p 47 MHz When P is used, VOUT =. V p-p 6 MHz When M is used, VOUT = 5 mv p-p 37 MHz When M is used, VOUT =. V p-p 8 MHz Overdrive Recovery Time For P, positive recovery/negative recovery 2/2 ns For M, positive recovery/negative recovery 4/2 ns Slew Rate When differentially used, VOUT = 2 V step 37 V/µs When P or M is single-ended, VOUT = V step 2 V/µs Settling Time.% When used differentially, VOUT = 2 V step 75 ns When P is used, VOUT = V step 6 ns When M is used, VOUT = V step 6 ns NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) When used differentially, fc = khz, VOUT = V p-p When used differentially, fc = MHz, VOUT = V p-p 7/ 6 8/ 85 When P is used, fc = khz, VOUT = 5 mv p-p 8/ 5 dbc When P is used, fc = MHz, VOUT = 5 mv p-p 8/ 83 dbc When M is used, fc = khz, VOUT = 5 mv p-p 3/ 7 dbc When M is used, fc = MHz, VOUT = 5 mv p-p 75/ 78 dbc Referred to Input (RTI) Voltage Noise For P, f = Hz 6 nv/ Hz For P, f = khz 5.2 nv/ Hz Referred to Output (RTO) Voltage Noise For Pand M, f = Hz, measured at VOUT2 4 nv/ Hz For P and M, f = khz, measured at VOUT2 8 nv/ Hz Input Current Noise f = khz, referred to P. pa/ Hz DC PERFORMANCE Output Offset Voltage Differential.5.75 mv Input Offset Voltage Drift Differential.6 6 µv/ C Output Offset Voltage Single-ended, P only µv Single-ended, M only 7 25 µv Input Offset Voltage Drift Single-ended, P only. 5.9 µv/ C Single-ended, M only µv/ C Input Bias Current P only at VIN pin 6 23 na P only at RF pin 6 35 na M only at REF pin 6 2 na Input Offset Current P only 6 27 na Open-Loop Gain P only, VOUT =.5 V to 3.5 V 94 db Gain M only V/V Gain Error % Gain Error Drift ppm/ C dbc dbc Rev. B Page of 37

12 ADA435 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance VIN and REF 2 MΩ Input Capacitance VIN and REF.4 pf Input Common-Mode Voltage Range 3.9 V Common-Mode Rejection Ratio For P, VCM = ±.5 V db OUTPUT CHARACTERISTICS Output Voltage Swing RL = no load, single-ended.5 to to V RL = 5 Ω, single-ended.28 to to 4.76 V Output Common-Mode Voltage Range 3.9 V Linear Output Current For Por M, VOUT = V p-p, 6 db SFDR 4 ma rms Differential output, VOUT = V p-p, 6 db SFDR ma rms Short-Circuit Current For P or M, sinking/sourcing 4/63 ma Capacitive Load Drive When used differentially at each VOUTx, 33 pf 3% overshoot, VOUT = mv p-p When P/M is used, 3% overshoot, 47 pf VOUT = 5 mv p-p POWER SUPPLY Operating Range V Positive Power Supply Rejection Ratio For P 86 4 db For M 8 94 db Negative Power Supply Rejection Ratio For P 8 92 db For M db P and M within this table refer to the amplifiers shown in Figure. Rev. B Page 2 of 37

13 ADA435 TIMING SPECIFICATIONS All input signals are specified with tr = tf = 2 ns (% to 9% of DVDD) and timed from a voltage threshold level of VTH =.3 V at DVDD = 3.3 V or VTH =.7 V at DVDD = 5 V. Guaranteed by characterization; not production tested. See Figure 2 and Figure 3. Table 9. DVDD = 3.3 V DVDD = 5 V Parameter Description Min Max Min Max Unit t SCLK period. 2 2 ns t2 SCLK positive pulse width. ns t3 SCLK negative pulse width. ns t4 CS setup time. The time required to begin sampling data after CS goes low. ns t5 CS hold time. The amount of time required for CS to be held low after the last data bit is sampled before bringing CS high. Data is latched on the CS rising edge. If LATCH is held low, data is also applied on the CS rising edge. 7 5 ns t6 CS positive pulse width. The amount of time required between consecutive words. 2 ns t7 Data setup time. The amount of time the data bit (SDI) must be set before sampling ns on the falling edge of SCLK. t8 Data hold time. The amount of time SDI must be held after the falling edge of SCLK for valid data to be sampled. 2 2 ns t9 Data latched to the internal switches updated. The amount of time it takes from the 45 4 ns latched data being applied until the internal switches are updated. LATCH disabled referenced from the rising edge of CS. LATCH enabled referenced from the falling edge of LATCH. t LATCH negative pulse width. 3 3 ns t 2 SCLK rising edge to SDO valid. The amount of time between the SCLK rising edge and the valid SDO transitions (CLSDO 3 = 2 pf). 5 ns t2 CS rising edge to the SCLK falling edge. The amount of time required to prevent a 25 th SCLK edge from being recognized (only 24 bits allowed for valid word). ns When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. 2 This is while in daisy-chain mode and in readback mode. 3 CLSDO is the capacitive load on the SDO output. Timing Diagrams for Serial Mode LATCH ENABLED: LATCHED DATA APPLIED ON FALLING EDGE OF LATCH LATCH LATCH DISABLED: DATA LATCHED AND APPLIED ON RISING EDGE OF CS t 6 t V TH CS V TH t t 4 t 5 SCLK V TH t8 t 2 t 3 SDI V TH t 7 t 9 INTERNAL SWITCHES POSITION SWITCHES UPDATED t 9 INTERNAL SWITCHES POSITION SWITCHES UPDATED Figure 2. Write Operation Rev. B Page 3 of 37

14 ADA435 Data Sheet LATCH LATCH DISABLED: DATA LATCHED AND APPLIED ON RISING EDGE OF CS CS READ COMMAND LATCHED ON RISING EDGE OF CS t 6 READBACK COMPLETED ON RISING EDGE OF CS t2 V TH SCLK V TH SDI V TH READ COMMAND: INPUT WORD SPECIFIES REGISTER TO BE READ t NOP COMMAND SDO V TH UNDEFINED Figure 3. Read Operation READBACK: SELECTED REGISTER DATA CLOCKED OUT Rev. B Page 4 of 37

15 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Analog Supply Voltage 4 V Digital Supply Voltage 5.5 V Power Dissipation See Figure 4 Common-Mode Input Voltage ±Vs ±.3V Differential Input Voltage ±.7 V Input Current (IN-N, IN-P, VIN, RF, and REF) 2 ma Storage Temperature Range 65 C to +25 C Operating Temperature Range 4 C to +85 C Lead Temperature (Soldering, sec) 3 C Junction Temperature 5 C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θja is specified for the worst case conditions, that is, θja is specified for a device soldered in a circuit board for surfacemount packages. Table lists the θja for the ADA435. Table. Thermal Resistance Package Type θja Unit 28-Lead TSSOP 72.4 C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA435 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 5 C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA435. Exceeding a junction temperature of 75 C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA435 output load drive. ADA435 The quiescent power dissipation is the voltage between the supply pins (±VS) multiplied by the quiescent current (IS). PD = Quiescent Power + (Total Drive Power Load Power) P D = ( ± V I ) S S ± V + 2 S V R OUT L V RL 2 OUT Consider rms output voltages. If RL is referenced to VS, as in single-supply operation, the total drive power is +VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = +VS/4 for RL to midsupply for dual supplies and VOUT = +VS/2 for single supply. P D = ( + V I ) S S + ( V ) OUT R L 2 Airflow increases heat dissipation, effectively reducing θja. In addition, more metal directly in contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes reduces θja. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a JEDEC standard 4-layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (W) LEAD TSSOP AMBIENT TEMPERAURE ( C) T J = 5 C Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. B Page 5 of 37

16 ADA435 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SWB_OUT RF VOUT VIN SWA_OUT VOUT2 FB5 FB4 FB3 FB2 FB FB ADA435 TOP VIEW (Not to Scale) REF DVDD CS/P4 SDI/P3 SDO/P2 SCLK/P IN-N IN-P SWA_IN SWB_IN V S LATCH/P DGND MODE EN +V S Figure 5. Pin Configuration Table 2. Pin Function Descriptions Pin No. Mnemonic Description SWB_OUT Switch Group B (S3 to S5 and S9 to S) Output. 2 RF Feedback Resistor for Output Differential Amplifier. 3 VOUT Differential Amplifier Output. 4 FB5 Feedback Pin 5 for FET Input Amplifier. 5 FB4 Feedback Pin 4 for FET Input Amplifier. 6 FB3 Feedback Pin 3 for FET Input Amplifier. 7 FB2 Feedback Pin 2 for FET Input Amplifier. 8 FB Feedback Pin for FET Input Amplifier. 9 FB Feedback Pin for FET Input Amplifier. IN-N FET Input Amplifier Inverting Input. IN-P FET Input Amplifier Noninverting Input. 2 SWA_IN Switch Group A (S to S2 and S6 to S8) Input. 3 SWB_IN Switch Group B (S3 to S5 and S9 to S) Input. 4 VS Analog Negative Supply. 5 +VS Analog Positive Supply. 6 EN Enable Pin. 7 MODE Mode Pin. Use this pin to switch between the SPI interface and the parallel interface. 8 DGND Digital Ground. 9 LATCH/P Latch Bit in the Serial Mode (LATCH). Parallel Data Bit in parallel mode (P). 2 SCLK/P Digital Clock in Serial Mode (SCLK). Parallel Data Bit in parallel mode (P). 2 SDO/P2 Serial Data Out in Serial Mode (SDO). Parallel Data Bit 2 in parallel mode (P2). 22 SDI/P3 Serial Data In in Serial Mode (SDI). Parallel Data Bit 3 in parallel mode (P3). 23 CS/P4 Select Bit in Serial Mode (CS). Parallel Data Bit 4 in parallel mode (P4). 24 DVDD Digital Positive Supply. 25 REF Reference for the ADC Driver at M. 26 VOUT2 Differential Amplifier Output SWA_OUT Switch Group A (S to S2 and S6 to S8) Output. 28 VIN Differential Amplifier Noninverting Input. Rev. B Page 6 of 37

17 ADA435 TYPICAL PERFORMANCE CHARACTERISITICS FULL SYSTEM These plots are for the full system, which includes the FET input amplifier, the switching network, and the ADC driver. Unless otherwise stated, RL = kω differential. For Vs = ±5 V, DVDD = +5 V, and for Vs = +5 V (or ±2.5 V), DVDD = +3.3 V. NORMALIZED CLOSED-LOOP GAIN (db) V S = +5V 8 R F = 5kΩ V OUT = 2mV p-p G = 5 9. FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Supplies, See Test Circuit in Figure DISTORTION (dbc) TIA GAIN = 5, ADC DRIVER GAIN = + R F = 5kΩ V OUT = 4V p-p V S = +5V, HD3 V S = +5V, HD2, HD FREQUENCY (MHz), HD3 Figure 9. Harmonic Distortion vs. Frequency for Various Supplies, See Test Circuit in Figure NORMALIZED CLOSED-LOOP GAIN (db) V OUT = 2V p-p V OUT = 2mV p-p 8 Vs = ±5V 9 G = 5 R F = 5kΩ. FREQUENCY (MHz) V OUT = V p-p INPUT REFERRED VOLTAGE NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) Figure 7. Frequency Response for Various Voltage Outputs, See Test Circuit in Figure 49 Figure. Input Referred Voltage Noise vs. Frequency OUTPUT VOLTAGE (V) G = 5 V OUT = 2V p-p R F = 5kΩ V S = ±2.5V TIME (ns/div) SUPPLY CURRENT [ENABLE AND M DISABLE] (ma) 2 8 DIGITAL ENABLE M DISABLE ALL DISABLE TEMPERATURE ( C) SUPPLY CURRENT [DIGITAL AND ALL DISABLE] (µa) Figure 8. Large Signal Step Response, G = 5 for Various Supplies Figure. Supply Current vs. Temperature at Different Modes Rev. B Page 7 of 37

18 ADA435 Data Sheet 5 6 V S = ±5 V PSRR (db) PSRR +PSRR SWTICH ON RESISTANCE (Ω) SAMPLE SWITCH AT 85 C SAMPLE SWITCH AT 25 C FEEDBACK SWITCH AT 85 C FEEDBACK SWITCH AT 25 C. FREQUENCY (khz) COMMON-MODE VOLTAGE (V CM ) Figure 2. PSRR vs. Frequency Figure 4. Switch On-Resistance vs. Common-Mode Voltage at Switches for Various Temperature.3.2 SETTLING TIME (%)...2 V OUT = 4V p-p TIA GAIN = 5, ADC DRIVER GAIN = TIME (ns) Figure 3..% Settling Time, See Test Circuit in Figure Rev. B Page 8 of 37

19 ADA435 FET INPUT AMPLIFIER Unless otherwise stated, RL = kω. For Vs = ±5 V, DVDD = +5 V, and for Vs = ±2.5 V, DVDD = +3.3 V. NORMALIZED CLOSED-LOOP GAIN (db) V OUT = mv p-p G = + R F = 9kΩ G = 5 R F = 5kΩ G = +2 R F = kω C F = 3pF NORMALIZED CLOSED-LOOP GAIN (db) V S = 5V V OUT = V p-p G = + R F = 9kΩ G = 5 R F = 5kΩ G = +2 R F = kω C F = 3pF 8. FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Gains, VS = ±5 V, See Test Circuit Diagrams in Figure 5 and Figure FREQUENCY (MHz) Figure 8. Large Signal Frequency Response for Various Gains, VS = 5 V, See Test Circuit Diagrams in Figure 5 and Figure NORMALIZED CLOSED-LOOP GAIN (db) V S = 5V V OUT = mv p-p G = + R F = 9kΩ G = 5 R F = 5kΩ G = +2 R F = kω C F = 3pF OUTPUT VOLTAGE (V) V S = ±2.5V G = 5 V OUT = 2V p-p 8. FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Gains, VS = 5 V, See Test Circuit Diagrams in Figure 5 and Figure TIME (ns/div) Figure 9. Large Signal Step Response for Various Supplies, G = NORMALIZED CLOSED-LOOP GAIN (db) V OUT = 2V p-p G = + R F = 9kΩ G = 5 R F = 5kΩ 8. FREQUENCY (MHz) G = +2 R F = kω, C F = 3pF Figure 7. Large Signal Frequency Response for Various Gains, VS = ±5 V, See Test Circuit Diagrams in Figure 5 and Figure SETTLING TIME (%) TIME (ns/div) Figure 2..% Settling Time V OUT = 2V STEP G = 5 R F = 5kΩ TIME = ns/div Rev. B Page 9 of 37

20 ADA435 Data Sheet DISTORTION (dbc) G = 5 V OUT = 2V p-p R L = kω HD FREQUENCY (MHz) HD3 Figure 2. Distortion (HD2/HD3) vs. Frequency, G = NUMBER OF PARTS UNITS X =.µv/ C σ =.25µV/ C INPUT OFFSET VOLTAGE DRIFT (µv/ C) Figure 24. Input Offset Voltage Drift INPUT REFERRED VOLTAGE NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) Figure 22. Input Voltage Noise OPEN-LOOP GAIN (db) GAIN PHASE k k k M M M G FREQUENCY (Hz) Figure 25. Open-Loop Gain and Phase vs. Frequency PHASE (Degrees) UNITS x =.88µV σ = 3.58µV NUMBER OF PARTS 3 2 CMRR (db) INPUT OFFSET VOLTAGE (µv) Figure 23. Input Offset Voltage k k k M M FREQUENCY (Hz) Figure 26. CMRR vs Frequency Rev. B Page 2 of 37

21 ADA435 PSRR (db) PSRR INPUT AND OUTPUT VOLTAGE (V) V IN 6 V G = +6 OUT R L = kω +PSRR 2 k k k M M FREQUENCY (Hz) Figure 27. PSRR vs Frequency TIME (ns/div) Figure 28. Output Overdrive Recovery when Used as an Amplifier Rev. B Page 2 of 37

22 ADA435 Data Sheet ADC DRIVER Unless stated otherwise, RL = kω differential, and RL = 5 Ω when single-ended. For VS = ±5 V, DVDD = +5 V, and for VS = +5 V (or ±2.5 V), DVDD = +3.3 V. NORMALIZED MAGNITUDE (db) V S = 5V R F = kω V OUT (SINGLE-ENDED) = 5mV p-p V OUT (DIFFERENTIAL) = mv p-p P GAIN = DIFFERENTIAL SINGLE-ENDED OUTPUT AT VOUT2 SINGLE-ENDED OUTPUT AT VOUT 9. FREQUENCY (MHz) Figure 29. Small Signal Frequency Response, VS = 5 V NORMALIZED MAGNITUDE (db) 3 3 SINGLE-ENDED OUTPUT AT VOUT2 DIFFERENTIAL SINGLE-ENDED OUTPUT AT VOUT 6 R F = kω V OUT (SINGLE-ENDED) = V p-p V OUT (DIFFERENTIAL) = 2V p-p P GAIN = 9. FREQUENCY (MHz) Figure 32. Large Signal Frequency Response, VS =±5 V NORMALIZED MAGNITUDE (db) 3 3 SINGLE-ENDED OUTPUT AT VOUT2 SINGLE-ENDED OUTPUT AT VOUT 6 V S = 5V R F = kω V OUT (SINGLE-ENDED) = V p-p V OUT (DIFFERENTIAL) = 2V p-p P GAIN = 9. FREQUENCY (MHz) DIFFERENTIAL Figure 3. Large Signal Frequency Response, VS = 5 V AMPLITUDE (V) G = + VOUT TIME (ns/div) VOUT2 Figure 33. Large Signal Step Response (Single-Ended Output), VS = ±5 V NORMALIZED MAGNITUDE (db) R F = kω V OUT (SINGLE-ENDED) = 5mV p-p V OUT (DIFFERENTIAL) = mv p-p P GAIN = DIFFERENTIAL SINGLE-ENDED OUTPUT AT VOUT2 SINGLE-ENDED OUTPUT AT VOUT AMPLITUDE (V) G = + R L = kω 9. FREQUENCY (MHz) Figure 3. Small Signal Frequency Response, VS = ±5 V TIME (ns/div) Figure 34. Large Signal Step Response (Differential Output), VS = ±5 V Rev. B Page 22 of 37

23 ADA435 AMPLITUDE (V) V S = ±2.5V G = + VOUT TIME (ns/div) VOUT2 Figure 35. Large Signal Step Response (Single-Ended Output), VS = ±2.5 V NUMBER OF PARTS UNITS x = 35.9µV σ = 85.8µV OUTPUT OFFSET VOLTAGE (µv) Figure 38. Differential Output Offset Voltage V S = ±2.5V G = UNITS X =.5µV/ C σ =.37µV/ C AMPLITUDE (V) NUMBER OF PARTS TIME (ns/div) OFFSET VOLTAGE DRIFT (µv/ C) Figure 36. Large Signal Step Response (Differential Output), VS = ±2.5 V Figure 39. Differential Output Offset Voltage Drift DISTORTION (dbc) V OUT = 4V p-p DIFFERENTIAL, 2V p-p SINGLE-ENDED G = + HD2, DIFFERENTIAL HD2, SINGLE-ENDED OUTPUT AT VOUT HD2, SINGLE-ENDED OUTPUT AT VOUT2 HD3, DIFFERENTIAL HD3, SINGLE-ENDED OUTPUT AT VOUT HD3, SINGLE-ENDED OUTPUT AT VOUT2 NUMBER OF PARTS UNITS FOR P: x =.87µV σ = 37.µV FOR M: x = 6.7µV σ = 3.27µV FREQUENCY (MHz) Figure 37. Harmonic Distortion vs. Frequency OFFSET VOLTAGE (µv) Figure 4. Single-Ended Output Offset Voltage Rev. B Page 23 of 37

24 ADA435 Data Sheet NUMBER OF PARTS UNITS FOR P: x =.6µV/ C σ =.54µV/ C FOR M: x =.22µV/ C σ =.4µV/ C INPUT AND OUTPUT VOLTAGE (V) V IN 2 V OUT G = +2 R F = kω R L = 5Ω OFFSET VOLTAGE DRIFT (µv/ C) TIME (ns/div) Figure 4. Single-Ended Offset Voltage Drift Figure 44. Output Overdrive Recovery (M Only) V CM = ±.5V PSRR CMRR (db) 6 7 PSRR (db) 6 +PSRR FREQUENCY (MHz) Figure 42. CMRR vs. Frequency k k k M M FREQUENCY (Hz) Figure 45. PSRR vs. Frequency (P Only) INPUT AND OUTPUT VOLTAGE (V) V IN 2 V OUT G = +2 R F = kω R L = 5Ω 6 TIME (ns/div) Figure 43. Output Overdrive Recovery (P Only) Rev. B Page 24 of 37

25 ADA435 INPUT REFERRED VOLTAGE NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) Figure 46. Input Referred Voltage Noise vs. Frequency, P Only, See Test Circuit Diagram in Figure OUTPUT REFERRED VOLTAGE NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) Figure 47. Output Referred Voltage Noise vs. Frequency, P and M, See Test Circuit Diagram in Figure Rev. B Page 25 of 37

26 ADA435 Data Sheet TEST CIRCUITS 5kΩ FUNCTION GENERATOR LPF kω 825Ω G = 5 kω P kω VOUT 5Ω 5Ω MEASURE DISTORTION WITH DIFFERENTIAL OUTPUT FET AMP M VOUT2 5Ω DIFFERENTIAL GAIN = ADC DRIVER Figure 48. Harmonic Distortion for Full System kΩ V IN kω P VOUT 825Ω G = 5 kω kω 5Ω 5Ω MEASURE PARAMETERS AT DIFFERENTIAL OUTPUT FET AMP M VOUT2 5Ω DIFFERENTIAL GAIN = ADC DRIVER Figure 49. Full System Measurement for Other Parameters C F R G AC SIGNAL OF DIFFERENCE FREQUENCY FET AMP R F G = + R F R G MEASURE FREQUENCY RESPONSE Figure 5. Frequency Response for FET Input Amplifier, Noninverting Gain Configuration AC SIGNAL OF DIFFERENCE FREQUENCY R G FET AMP C F R F R L MEASURE FREQUENCY RESPONSE G = R F R G Figure 5. Frequency Response for FET Input Amplifier, Inverting Gain Configuration V N P MEASURE OUTPUT NOISE HERE G = + INPUT REFERRED NOISE V N = OUTPUT NOISE Figure 52. Input Referred Voltage Noise for P P INSIDE CHIP kω 5Ω kω M MEASURE OUTPUT REFERED VOLTAGE NOISE HERE Figure 53. Output Referred Voltage Noise for P and M Rev. B Page 26 of 37

27 THEORY OF OPERATION KELVIN SWITCHING TECHNIQUES Traditional gain selectable amplifiers use analog switches in a feedback loop to connect discrete external resistors and capacitors to the inverting input by selecting the appropriate feedback path. This approach introduces several errors due to the nonideal nature of the analog switches in the loop. For example, the on-resistance of the analog switch causes voltage and temperature dependent gain errors, while the leakage current causes offset errors, especially at high temperature. The Kelvin switching technique solves this problem by introducing two switches in each gain selection loop, one to connect the transimpedance/ op amp output to the feedback network, and the other to connect the feedback network output to the downstream components. Figure 54 shows a programmable gain transimpedance amplifier with Kelvin switching. C F R F C F2 R F2 HIGH IMPEDANCE LOAD EXAMPLE ADA435 Although this technique requires using twice as many switches, the voltage (Vx) in the center node is no longer switch dependent; it is only dependent on the current across the selected resistor (see Equation through Equation 3). VOUT = IPHOTO (RF2 + RSB) () V = VOUT (RF2/(RF2 + RSB)) (2) Substituting Equation into Equation 2, V = IPHOTO RF2 (3) where: VOUT is the output of the first amplifier. IPHOTO is the current from the photodiode. RF2 is the feedback resistor of Transimpedance Path 2. RSB is the switch resistance of the SB switch. The switches shown on the right (S2A and S2B) in Figure 54 only have a small output impedance and contribute negligible error if the amplifier drives a high impedance load. In the case of the ADA435, the high impedance load is the integrated ADC driver. I PHOTO V OUT SB SA V V2 S2B S2A R L NOTES. SA, SB, S2A, AND S2B ARE THE ANALOG SWITCHES. R Fx ARE THE FEEDBACK RESISTORS SPECIFIC TO EACH TRANSIMPEDANCE PATH. C Fx ARE THE FEEDBACK CAPACITORS SPECIFIC TO EACH TRANSIMPEDANCE PATH. Figure 54. Programmable Gain Transimpedance Amplifier with Kelvin Switching Rev. B Page 27 of 37

28 ADA435 APPLICATIONS INFORMATION CONFIGURING THE ADA435 See the EVAL-ADA435RUZ-P user guide for details on the basic configuration of the ADA435, and how to use the evaluation board. For more details on configuring the ADC driver in a different gain setting, see the ADA494- data sheet. The gain settings of the ADA435 can be chosen via the SPI interface or manually through a 5-lead DIP switch. SELECTING THE TRANSIMPEDANCE GAIN PATHS MANUALLY OR THROUGH THE PARALLEL INTERFACE In the manual mode (or parallel mode), only five out of the six transimpedance paths can be accessed (FB to FB4). Figure 55 shows the simplified schematics of the ADA435 and the positions of FB to FB4. In this example, the first two feedback paths (FB and FB) are configured as two different transimpedance gain paths. To operate in manual mode or in parallel mode, set the EN pin (Pin 6) and the MODE pin (Pin 7) to Logic. In this mode, Pin 9 to Pin 23 represent P through P4, respectively. To select one gain, set the corresponding Px pin to Logic, and set all other Px pins to Logic. Table 3 shows the relationship between the gain select switches (P through P4) and the gain path selected. Data Sheet Setting more than one Px pin to Logic results in connecting the selected gain paths in parallel. Table 3. Manual Mode or Parallel Mode Operation Bit On Switch Closed Gain Path Selected P S and S6 FB P S and S7 FB P2 S2 and S8 FB2 P3 S3 and S9 FB3 P4 S4 and S FB4 SELECTING THE TRANSIMPEDANCE GAIN PATHS THROUGH THE SPI INTERFACE (SERIAL MODE) For serial mode operation, set the EN pin (Pin 6) to Logic and the MODE pin (Pin 7) to Logic. In serial mode, Pin 9 is LATCH, Pin 2 is SCLK, Pin 2 is SDO, Pin 22 is SDI, and Pin 23 is CS. Serial mode operation uses a 24-bit command to configure each individual switch, S through S, as well as additional options. Table 4 shows the 24-bit map used in serial mode operation. Table 5 shows the example codes that select the various transimpedance gain paths. Multifunction pin names may be referenced by their relevant function only. C F R F C F R F FB FB FB2 FB3 FB4 FB5 SWA_OUT SWB_OUT VIN RF ADA IN-N IN-P S S S2 S6 S7 S8 P 3 VOUT S3 S4 S5 S9 S S M 26 VOUT2 SPI INTERFACE SWA_IN EN MODE LATCH/P REF SCLK/P SDI/P3 CS/P SWB_IN SDO/P2 FET AMP SWITCHING NETWORK ADC DRIVER 247- Figure 55. Simplified Schematic Rev. B Page 28 of 37

29 ADA435 Table Bit Map Used in Serial Mode Operation Bit No. Function Default Setting S on/off control. Write to this bit to close Switch S. S on/off control. Write to this bit to close Switch S. 2 S2 on/off control. Write to this bit to close Switch S2. 3 S3 on/off control. Write to this bit to close Switch S3. 4 S4 on/off control. Write to this bit to close Switch S4. 5 S5 on/off control. Write to this bit to close Switch S5. 6 S6 on/off control. Write to this bit to close Switch S6. 7 S7 on/off control. Write to this bit to close Switch S7. 8 S8 on/off control. Write to this bit to close Switch S8. 9 S9 on/off control. Write to this bit to close Switch S9. S on/off control. Write to this bit to close Switch S. S on/off control. Write to this bit to close Switch S. 2 Reserved. Set to logic low. 3 Optional internal pf feedback capacitor between the inverting input and the output of the amplifier. Write to this bit to turn the capacitor on. 4 Disable the SDO pin. Write to this bit to disable the SDO pin. 5 Disable the M amplifier. Write to this bit to disable the M amplifier. 6 Reserved. Set to logic low. 7 Reserved. Set to logic low. 8 Reserved. Set to logic low. 9 Reserved. Set to logic low. 2 Reserved. Set to logic low. 2 Reserved. Set to logic low. 22 Reserved. Set to logic low. 23 Read/write bit. Set to to read and set to to write. The optional internal pf feedback capacitor provides a quick and convenient way to compensate the TIA when using a high value feedback resistor (> MΩ). Table 5. Serial Mode Operation Command (Hex Code Format, B23 B) Switch Closed Gain Path Selected 4(MSB Side) S and S6 FB 2 4 S and S6 FB, optional internal feedback capacitor on 82 S and S7 FB 4 S2 and S8 FB2 2 8 S3 and S9 FB3 4 S4 and S FB4 8 2 S5 and S FB5 Rev. B Page 29 of 37

30 ADA435 SPICE MODEL The SPICE model only supports parallel mode operation. Pin P5 enables parallel mode and allows full switching network functionality. Data Sheet The EN and MODE inputs are internally set to high and low, respectively, and are not accessible in this model. Figure 56 shows the recommended symbol pins when creating the ADA435 symbol in the SPICE simulator IN_N IN_P 5 VCC 4 VEE FB FB FB2 FB3 FB4 FB5 SWA_OUT ADA435 U SWB_OUT VIN RF VOUT 3 VOUT DVDD 8 DGND SWA_IN SWB_IN LATCH/P SCLK/P SDO/P2 SDI/P3 CS/P4 P5 REF Figure 56. Recommended Symbol Layout Table 6. Model Pin Descriptions Symbol Pin Model Node Pin No. Mnemonic N IN_N 2 N IN_P 3 VCC 5 VCC 4 VEE 4 VEE 5 VDD 24 DVDD 6 DGND 8 DGND 7 N2 2 SWA_IN 8 N3 3 SWB_IN 9 PO 9 LATCH/P P 2 SCLK/P P2 2 SDO/P2 2 P3 22 SDI/P3 3 P4 23 CS/P4 4 P5 Not applicable P5 5 N25 25 REF 6 N26 26 VOUT2 7 N3 3 VOUT 8 N2 2 RF 9 N28 28 VIN SWA_OUT 2 SWB_OUT FB FB FB FB FB FB Rev. B Page 3 of 37

31 ADA435 C6 R6 3kΩ C5 R5 kω C4 R4 3kΩ C3 R3 kω C2 R2 3kΩ C R kω AC SlNE ( m k ) I C PHOTODIODE IN_N IN_P FB FB FB2 FB3 FB4 FB5 SWA_OUT SWB_OUT VIN RF VOUT 3 VOUT 5 V 5 V2 5 V3 5 VCC 4 VEE 24 DVDD 8 DGND SWA_IN 2 SWB_IN ADA435 U LATCH/P SCLK/P SDO/P2 SDI/P3 CS/P4 P5 VOUT2 26 REF Figure 57. SPICE Schematic Example to Test Basic Functionality VOUT Rev. B Page 3 of 37

32 ADA435 Data Sheet TRANSIMPEDANCE AMPLIFIER DESIGN THEORY Because its low input bias current minimizes the dc error at the preamp output, the ADA435 works well in photodiode preamp applications. In addition, its high gain bandwidth product and low input capacitance maximizes the signal bandwidth of the photodiode preamp. Figure 58 shows the transimpedance amplifier model of the ADA435. C F Equating the zero frequency, fz, with the fx frequency maximizes the signal bandwidth with a 45 phase margin. Calculate fx as follows because fx is the geometric mean of fp and fgbw: f x f f (7) P GBW By combining Equation 5, Equation 6, and Equation 7, the CF value that produces fx is defined by I PHOTO V B C S R SH = Ω + C D R F C M C M ADA435 Figure 58. Transimpedance Amplifier Model of the ADA435 The basic transfer function in Equation 4 describes the transimpedance gain of the photodiode preamp. V OUT F F V OUT I PHOTO RF (4) sc R where: IPHOTO is the output current of the photodiode. RF is the feedback resistor. CF is the feedback capacitance. The signal bandwidth is /(RF CF), as determined by Equation 4. In general, set RF such that the maximum attainable output voltage corresponds to the maximum diode current, IPHOTO, allowing the use of the full output swing. The signal bandwidth attainable with this preamp is a function of RF, the gain bandwidth product (fgbw) of the amplifier, and the total capacitance at the amplifier summing junction, including CS and the amplifier input capacitance of CD and CM. RF and the total capacitance produce a pole with the loop frequency (fp). fp = /2πRFCS (5) With the additional pole from the open-loop response of the amplifier, the two-pole system results in peaking and instability due to an insufficient phase margin (see gray lines for the noise gain and phase in Figure 59). Adding CF to the feedback loop creates a zero in the loop transmission that compensates for the effect of the input pole, which stabilizes the photodiode preamp design because of the increased phase margin (see the gray lines for the noise gain and phase in Figure 6). It also sets the signal bandwidth, fz (see the I to V gain line for the signal gain in Figure 6). The signal bandwidth and the zero frequency, fz, are determined by f z (6) 2πR C F F C F CS 2π R f F GBW The frequency response in this case shows approximately 2 db peaking and 5% overshoot. Doubling CF and cutting the bandwidth in half results in a flat frequency response with approximately 5% transient overshoot. PHASE ( ) A (db) OPEN-LOOP GAIN G = f P G = R 2 C s f X f GBW log f log f Figure 59. Noise Gain and Phase Bode Plot of the Transimpedance Amplifier Design Without Compensation (8) Rev. B Page 32 of 37

33 ADA435 A (s) OPEN-LOOP GAIN I TO V GAIN f Z f X f N G = + C S /C F The dominant output noise sources in the transimpedance amplifier design are the input voltage noise of the amplifier, VNOISE, and the resistor noise due to RF. The effect due to the current noise is negligible in comparison. The gray line in Figure 6 shows the noise gain and phase over frequencies for the transimpedance amplifier. The noise bandwidth is at the fn frequency, and is calculated by fgbw f N ( C C )/ C (9) S F F G = f P G = R F C S (s) f GBW f Table 7 shows the dominant noise sources (RF and VNOISE) for the transimpedance amplifier when it has a 45 phase margin for the maximum bandwidth, and in this case, fz = fx = fn. PHASE ( ) f Table 7. RMS Noise Contributions of Transimpedance Amplifier Contributor Expression RF π 4kT R F fn 2 VNOISE C S CM CF 2CD π VNOISE fn C 2 F 9 35 Figure 6. Signal and Noise Gain and Phase of the Transimpedance Amplifier Design with Compensation Rev. B Page 33 of 37

34 ADA435 Data Sheet C F4 R F4 C F3 R F3 C F2 R F2 C F R F C F R F S S6 I PHOTO C D = 9pF TO nf TIA S S2 S7 S8 Ω S3 S9 S4 S NOTES. R Fx ARE THE FEEDBACK RESISTORS SPECIFIC TO EACH TRANSIMPEDANCE PATH. C Fx ARE THE FEEDBACK CAPACITORS SPECIFIC TO EACH TRANSIMPEDANCE PATH. TRANSIMPEDANCE GAIN AMPLIFIER PERFORMANCE Figure 6 shows the ADA435 configured as a transimpedance amplifier with five different gains. The photodiode sensor capacitance, CD, varies from 9 pf to nf to showcase the transimpedance gain performance at various frequency. Figure 62 to Figure 65 shows the transimpedance vs. frequency at different CD settings. Note that the compensation capacitors, CF to CF4, correct for the inherent instability of the transimpedance configuration. Capacitors chosen were such that the transimpedance gain response compensates for the maximum bandwidth and is close to having a 45 phase margin. TRANSIMPEDANCE (Ω) M k k k C D = 9pF.k R F = kω, C F = 5pF R F = 3kΩ, C F = 6.8pF R F2 = kω, C F2 = 3.3pF R F3 = 3kΩ, C F3 = 2.2pF R F4 = kω, C F4 = pf.k.m M M M FREQUENCY (Hz) Figure 6. ADA435 Configured as a Transimpedance Amplifier with Five Different Gains C D = 9pF R F = kω R F = 3kΩ R F2 = kω R F3 = 3kΩ R F4 = kω Figure 62. Transimpedance vs. Frequency, CD = 9 pf TRANSIMPEDANCE (Ω) M k k k C D = nf.k R F = kω, C F = 33pF R F = 3kΩ, C F = 5pF R F2 = kω, C F2 = pf R F3 = 3kΩ, C F3 = 5.6pF R F4 = kω, C F4 = 3.3pF.k k k M M M FREQUENCY (Hz) Figure 63. Transimpedance vs. Frequency, CD = nf Rev. B Page 34 of 37