Ultralow Distortion, High Speed 0.95 nv/ Hz Voltage Noise Op Amp AD8099

Transcription

1 Ultralow Distortion, High Speed.9 nv/ Hz Voltage Noise Op Amp AD99 FEATURES Ultralow noise:.9 nv/ Hz,. pa/ Hz Ultralow distortion nd harmonic RL = kω, 9 MHz rd harmonic RL = kω, MHz High speed GBWP:. GHz db bandwidth: MHz () MHz (G = +) Slew rate: V/µs () V/µs (G = +) New pinout Custom external compensation, gain range, + to + Supply current: ma Offset voltage:. mv max Wide supply voltage range: V to V APPLICATIONS Pre-amplifiers Receivers Instrumentation Filters IF and baseband amplifiers A-to-D drivers DAC buffers Optical electronics CONNECTION DIAGRAMS DISABLE FEEDBACK IN +IN +V S V OUT C C V S Figure. -Lead CSP (CP-) -- FEEDBACK DISABLE IN +V S +IN V OUT V S C C Figure. -Lead SOIC-ED (RD-) -- GENERAL DESCRIPTION The AD99 is an ultralow noise (.9 nv/ Hz) and distortion ( 9 MHz) voltage feedback op amp, the combination of which make it ideal for - and -bit systems. The AD99 features a new, highly linear, low noise input stage that increases the full power bandwidth (FPBW) at low gains with high slew rates. ADI s proprietary next generation XFCB process enables such high performance amplifiers with relatively low power. The AD99 is available in a mm mm lead frame chip scale package (LFCSP) with a new pinout that is specifically optimized for high performance, high speed amplifiers. The new LFCSP package and pinout enable the breakthrough performance that previously was not achievable with amplifiers. The AD99 is rated to work over the extended industrial temperature range, C to + C. The AD99 features external compensation, which lets the user set the gain bandwidth product. External compensation allows gains from + to + with minimal trade-off in bandwidth. The AD99 also features an extremely high slew rate of V/µs, giving the designer flexibility to use the entire dynamic range without trading off bandwidth or distortion. The AD99 settles to.% in ns and recovers from overdrive in ns. The AD99 drives Ω loads at breakthrough performance levels with only ma of supply current. With the wide supply voltage range ( V to V), low offset voltage (. mv typ), wide bandwidth ( MHz for ), and a GBWP up to. GHz, the AD99 is designed to work in a wide variety of applications. HARMONIC DISTORTION (dbc) 9 V OUT = V p-p R L = kω SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... Figure. Harmonic Distortion vs. Frequency and Gain (SOIC) -A- Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel:.9. Fax:.. Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... Specifications with ± V Supply... Specifications with + V Supply... Absolute Maximum Ratings... Maximum Power Dissipation... ESD Caution... Typical Performance Characteristics... Theory of Operation... Applications... Using the AD99... Circuit Components... Recommended Values... Circuit Configurations... Performance vs. Component values... 9 Total Output Noise Calculations and Design... Input Bias Current and DC Offset... DISABLE Pin and Input Bias Cancellation... -Bit ADC Driver... Circuit Considerations... Design Tools and Technical Support... Outline Dimensions... Ordering Guide... REVISION HISTORY / Data Sheet changed from REV. A to REV. B Change to General Description... Changes to Maximum Power Dissipation section... Changes to Applications section... Changes to Table... Changes to Ordering Guide... / Data Sheet changed from REV. to REV. A Inserted new Figure... Changes to Specifications... Inserted new Figures to... Inserted new Figures to... Changes to Theory of Operation section... Changes to Circuit Components section... Changes to Table... Changes to Figure... Changes to Total Output Noise Calculations and Design section... Changes to Figure... Changes to Figure... Changes to -Bit ADC Driver section... Changes to Table... Additions to PCB Layout section... / Revision : Initial Version Rev. B Page of

3 SPECIFICATIONS SPECIFICATIONS WITH ± V SUPPLY AD99 TA = C,, RL = kω to ground, unless otherwise noted. Refer to Figure through Figure for component values and gain configurations. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VOUT =. V p-p MHz G = +, VOUT = V p-p MHz Bandwidth for. db Flatness (SOIC/CSP), VOUT =. V p-p / MHz Slew Rate G = +, VOUT = V Step V/µs, VOUT = V Step V/µs Settling Time to.%, VOUT = V Step ns NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dbc) HD/HD fc = khz, VOUT = V p-p, G = + / dbc fc = MHz, VOUT = V p-p, G = + / 9 dbc Input Voltage Noise f = khz.9 nv/ Hz Input Current Noise f = khz, DISABLE pin floating. pa/ Hz f = khz, DISABLE pin = +VS. pa/ Hz DC PERFORMANCE Input Offset Voltage.. mv Input Offset Voltage Drift. µv/ C Input Bias Current DISABLE pin floating µa DISABLE pin = +VS. µa Input Bias Current Drift na/ C Input Bias Offset Current. µa Open-Loop Gain db INPUT CHARACTERISTICS Input Resistance Differential mode kω Common mode MΩ Input Capacitance pf Input Common-Mode Voltage Range. to +. V Common-Mode Rejection Ratio VCM = ±. V 9 db DISABLE PIN DISABLE Input Voltage Output disabled <. V Turn-Off Time % of DISABLE to < % of final VOUT, ns VIN =. V, Turn-On Time % of DISABLE to < % of final VOUT, 9 ns VIN =. V, Enable Pin Leakage Current DISABLE =+ V µa DISABLE Pin Leakage Current DISABLE = V µa OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rise/Fall) VIN = -. V to. V, G =+ / ns Output Voltage Swing RL = Ω. to +.. to +. V RL = kω. to +.. to +. V Short-Circuit Current Sinking and sourcing / ma Off Isolation f = MHz, DISABLE = low db POWER SUPPLY Operating Range ± ± V Quiescent Current ma Quiescent Current (Disabled) DISABLE = Low. ma Positive Power Supply Rejection Ratio +VS = V to V, VS = V (input referred) 9 db Negative Power Supply Rejection Ratio +VS = V, VS = V to V (input referred) 9 db Rev. B Page of

4 SPECIFICATIONS WITH + V SUPPLY VS = TA = C,, RL = kω to midsupply, unless otherwise noted. Refer to Figure through Figure for component values and gain configurations. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VOUT =. V p-p MHz G = +, VOUT = V p-p MHz Bandwidth for. db Flatness (SOIC/CSP), VOUT =. V p-p / MHz Slew Rate G = +, VOUT = V Step V/µs, VOUT = V Step V/µs Settling Time to.%, VOUT = V Step ns NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dbc) HD/HD fc = khz, VOUT = V p-p, G = + / 9 dbc fc = MHz, VOUT = V p-p, G = + / dbc Input Voltage Noise f = khz.9 nv/ Hz Input Current Noise f = khz, DISABLE pin floating. pa/ Hz f = khz, DISABLE pin = +VS. pa/ Hz DC PERFORMANCE Input Offset Voltage.. mv Input Offset Voltage Drift. µv/ C Input Bias Current DISABLE pin floating. µa DISABLE pin = +VS. µa Input Bias Offset Current. µa Input Bias Offset Current Drift. na/ C Open-Loop Gain VOUT = V to V db INPUT CHARACTERISTICS Input Resistance Differential mode kω Common mode MΩ Input Capacitance pf Input Common-Mode Voltage Range. to. V Common-Mode Rejection Ratio VCM = V to V db DISABLE PIN DISABLE Input Voltage Output disabled <. V Turn-Off Time % of DISABLE to <% of Final VOUT, ns VIN =. V, Turn-On Time % of DISABLE to <% of Final VOUT, ns VIN =. V, Enable Pin Leakage Current DISABLE = V µa DISABLE Pin Leakage Current DISABLE = V µa OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rise/Fall) VIN = to. V, / ns Output Voltage Swing RL = Ω. to.. to. V RL = kω. to.. to. V Short-Circuit Current Sinking and Sourcing / ma Off Isolation f = MHz, DISABLE = Low db POWER SUPPLY Operating Range ± ± V Quiescent Current.. ma Quiescent Current (Disabled) DISABLE = Low.. ma Positive Power Supply Rejection Ratio +VS =. V to. V, VS = V (input referred) 9 db Negative Power Supply Rejection Ratio +VS = V, -VS=. V to +. V (input referred) 9 db Rev. B Page of

5 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage. V Power Dissipation See Figure Differential Input Voltage ±. V Differential Input Current ±ma Storage Temperature C to + C Operating Temperature Range C to + C Lead Temperature Range (Soldering sec) C Junction Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD99 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD99. Exceeding a junction temperature of C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θja), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as J A ( P θ ) T = T + D JA The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/ IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power Load Power) P D = ( V I ) S S VS V + RL OUT V R OUT RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/ for RL to midsupply: P D = ( V I ) S S + ( V / ) S R L In single-supply operation with RL referenced to VS, worst case is VOUT = VS/. Airflow will increase heat dissipation, effectively reducing θja. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the θja. Soldering the exposed paddle to the ground plane significantly reduces the overall thermal resistance of the package. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in the PCB Layout section. Figure shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle (e-pad) SOIC- ( C/W), and CSP ( C/W), packages on a JEDEC standard -layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (Watts) LFCSP AND SOIC. AMBIENT TEMPERATURE ( C) L -- ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Figure. Maximum Power Dissipation Rev. B Page of

6 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = ± V, TA = C, RL = kω tied to ground unless otherwise noted. Refer to Figure through Figure for component values and gain configurations. NORMALIZED 9 V OUT =.V p-p R LOAD = kω G = G = + G = + NORMALIZED 9 V OUT =.V p-p R LOAD = kω G = G = + G = Figure. Small Signal Frequency Response for Various Gains (SOIC) Figure. Small Signal Frequency Response for Various Gains (CSP) G = + V OUT =.V p-p R L = Ω, CSP R L = kω, CSP G = + R L = kω V OUT =.V p-p 9 R L = kω, SOIC R L = Ω, SOIC 9, SOIC V S = ±.V, CSP, CSP -- V S = ±.V, SOIC -- Figure. Small Signal Frequency Response for Various Load Resistors Figure 9. Small Signal Frequency Response for Various Supply Voltages V OUT =.V p-p + C V OUT =.V p-p + C + C 9 + C 9 + C C C + C R L = kω --9 R L = kω --9 Figure. Small Signal Frequency Response for Various Temperatures (SOIC) Figure. Small Signal Frequency Response for Various Temperatures (CSP) Rev. B Page of

7 9 G = + pf, CSP 9 9 pf, SOIC pf, CSP pf, SOIC -- OPEN-LOOP GAIN (db) PHASE MAGNITUDE R L = kω UNCOMPENSATED OPEN-LOOP PHASE (Degrees) -- Figure. Small Signal Frequency Response for Various Capacitive Loads Figure. Open Loop Frequency Response NORMALIZED G = + G = + 9 V OUT = V p-p R LOAD = kω -- NORMALIZED G = + G = + V OUT = V p-p R LOAD = kω 9 -- Figure. Large Signal Frequency Response for Various Gains (SOIC) Figure. Large Signal Frequency Response for Various Gains (CSP)... R L = Ω V OUT =.V p-p... R L = Ω V OUT =.V p-p V OUT = mv p-p V OUT = mv p-p Figure.. db Flatness (SOIC) Figure.. d B Flatness (CSP) Rev. B Page of

8 R L = kω, CSP, CSP 9 G = + V OUT = V p-p R L = Ω, CSP R L = Ω, SOIC R L = kω, SOIC -- 9 G = + R L = kω V OUT = V p-p V S = ±.V, CSP, SOIC V S = ±.V, SOIC --9 Figure. Large Signal Frequency Response for Various Load Resistances Figure. Large Signal Frequency Response for Various Supply Voltages.. R L = kω V DIS = V INPUT IMPEDANCE (kω)... OFF ISOLATION (db) CSP SOIC Figure. Input Impedance vs. Frequency Figure. Off Isolation vs. Frequency OUTPUT IMPEDANCE (Ω). G = + G = + HARMONIC DISTORTION (dbc) 9 G = + V OUT = V p-p R L = Ω SOIC CSP.. -- SOLID LINES SECOND HARMONICS DOTTED LINES THIRD HARMONICS... -A- Figure 9. Output Impedance vs. Frequency for Various Gains Figure. Harmonic Distortion vs. Frequency Rev. B Page of

9 HARMONIC DISTORTION (dbc) 9 G = + V OUT = V p-p R L = kω HARMONIC DISTORTION (dbc) 9 G = + V OUT = V p-p R L = kω SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... -A-9 SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... -A- Figure. Harmonic Distortion vs. Frequency (SOIC) Figure. Harmonic Distortion vs. Frequency (CSP) HARMONIC DISTORTION (dbc) 9 V OUT = V p-p R L = kω HARMONIC DISTORTION (dbc) 9 V OUT = V p-p R L = kω SOLID LINES SECOND HARMONICS DOTTED LINE LINE THIRD HARMONICS... -A- SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... -A- Figure. Harmonic Distortion vs. Frequency (SOIC) Figure. Harmonic Distortion vs. Frequency (CSP) HARMONIC DISTORTION (dbc) 9 G = V OUT = V p-p R L = kω HARMONIC DISTORTION (dbc) 9 G = V OUT = V p-p R L = kω SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... -A- SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC... -A- Figure. Harmonic Distortion vs. Frequency (SOIC) Figure. Harmonic Distortion vs. Frequency (CSP) Rev. B Page 9 of

10 HARMONIC DISTORTION (dbc) 9 G = + R L = kω V S = ±.V V OUT = V p-p V OUT = V p-p SOLID LINES SECOND HARMONICS DOTTED LINES THIRD HARMONICS... -A- HARMONIC DISTORTION (dbc) 9 G = + R L = kω V S = ±.V V OUT = V p-p V OUT = V p-p SOLID LINES SECOND HARMONICS DOTTED LINES THIRD HARMONICS... -A- Figure 9. Harmonic Distortion vs. Frequency and Supply Voltage (SOIC) Figure. Harmonic Distortion vs. Frequency for Various Supplies ( CSP) G = + f = MHz R L = Ω G = + f = MHz R L = Ω HARMONIC DISTORTION (dbc) 9 SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC OUTPUT AMPLITUDE (V p-p) -A- HARMONIC DISTORTION (dbc) 9 SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC OUTPUT AMPLITUDE (V p-p) -A-9 Figure. Harmonic Distortion vs. Output Amplitude (SOIC) Figure. Harmonic Distortion vs. Output Amplitude (CSP) HARMONIC DISTORTION (dbc) 9 G = + f = MHz R L = kω HARMONIC DISTORTION (dbc) 9 G = + f = MHz R L = kω SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC OUTPUT AMPLITUDE (V p-p) -A- SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC OUTPUT AMPLITUDE (V p-p) -A- Figure. Harmonic Distortion vs. Output Amplitude (SOIC) Figure. Harmonic Distortion vs. Output Amplitude (CSP) Rev. B Page of

11 . pf, Ω R SNUB. pf, Ω R SNUB.... OUTPUT VOLTAGE (V)... pf R SNUB OUTPUT VOLTAGE (V)... pf R SNUB. G = + R L = kω. C L R L TIME (ns) --9. G = + R L = kω. C L R L TIME (ns) --9 Figure. Small Signal Transient Response for Various Capacitive Loads (SOIC) Figure. Small Signal Transient Response for Various Capacitive Loads (CSP).. V S = ±.V AND ±.V, CSP.. V S = ±.V CSP V S = ±.V CSP OUTPUT VOLTAGE (V)... G = + R L = kω. V S = ±.V AND ±.V, SOIC TIME (ns) Figure. Small Signal Transient Response for Various Supply Voltages -- OUTPUT VOLTAGE (V)..... R L = kω, Ω V OUT = mv p-p G = +. V S = ±.V SOIC V S = ±.V SOIC TIME (ns) Figure 9. Small Signal Transient Response for Various Supply Voltages -- OUTPUT VOLTAGE(V) R L = Ω INPUT R L = kω OUTPUT VOLTAGE (V) TURN OFF INPUT TURN ON TURN ON INPUT G = TURN OFF 9 TIME (ns) -A-. TIME (ns) -- Figure. Output Overdrive Recovery for Various Resistive Loads Figure. Disable/Enable Switching Speed Rev. B Page of

12 ...% V S = ±.V OUTPUT...% OUTPUT VOLTAGE (V)... G = + R L = kω. V S = ±.V TIME (ns) -- OUTPUT/INPUT VOLTAGE (V).. INPUT ERROR.%..% R LOAD = kω. V s = ±V.% TIME (ns) %.% -- Figure. Large Signal Transient Response vs. Supply Voltage (CSP) Figu re. Short Term Settling Time (CSP). V S = ±.V. OUTPUT.%...% OUTPUT VOLTAGE (V)... G = + R L = kω. V S = ±.V TIME (ns) -- OUTPUT/INPUT VOLTAGE (V).. INPUT ERROR.%.%..% R LOAD = kω. V s = ±V.% TIME (ns) % -- F igure. Large Signal Frequency Response vs. Supply Voltage (SOIC) Figure. Short Term Settling Time (SOIC).. OUTPUT.% OUTPUT VOLTAGE (V).... V S = ±.V OUTPUT/INPUT VOLTAGE (V).... ERROR INPUT.%.% %.%.% R L = kω, Ω G = +. TIME (ns) --. TIME (µs).% -- Figure. Large Signal Transient Response for Various Supply Voltages and Load Resistance s (SOIC and CSP) Figure. Long Term Settling Time Rev. B Page of

13 R L = kω G = + R L = kω COMMON-MODE REJECTION (db) 9 POWER SUPPLY REJECTION (db) 9 NEGATIVE POSITIVE Figure. Common-Mode Rejection vs. Frequency Figure. Power Supply Rejection vs. Frequency INPUT CURRENT NOISE (pa Hz) INPUT CURRENT NOISE (pa Hz) k k k M M M G FREQUENCY (Hz) -- k k k M M M G FREQUENCY (Hz) -- Figure. Input Current Noise v s. Frequency (DISABLE = Open) Figure. Input Current Noise vs. Frequency (DISABLE = +VS) INPUT VOLTAGE NOISE (nv Hz) COUNT N =, X = µv σ = µv. k k k M M M G FREQUENCY (Hz) -- V OFFSET (µv) -- Figure 9. Input Voltage Noise vs. Frequency Figure. Input Offset Voltage Distribution Rev. B Page of

14 V S =V OFFSET VOLTAGE (µv) SUPPLY CURRENT (ma) V S =V 9 TEMPERATURE (C) -A- 9 TEMPERATURE (C) -A- Figure. Input Offset Voltage vs. Temperature Figure. Supply Current vs. Temperature... I B +,.. I B +, BIAS CURRENT (µa)... I B, I B, V S =V BIAS CURRENT (µa).... I B, I B +, V S =V. I B +, V S =V.. I B, V S =V. 9 TEMPERATURE (C) -A-. 9 TEMPERATURE (C) -A- Figure. Input Bias Current vs. Temperature (DISABLE Pin Floating) Figure. Input Bias Current vs. Temperature (DISABLE Pin = +VS). OUTPUT SATURATION VOLTAGE (V)..... V S +V OUT V S +V OUT +V S V OUT +V S V OUT V S =V. 9 TEMPERATURE (C) -A- Figure. Output Saturation Voltage vs. Temperature Rev. B Page of

15 THEORY OF OPERATION The AD99 is a voltage feedback op amp that employs a new highly linear low noise input stage. With this input stage, the AD99 can achieve better than 9 db distortion for a V p-p, MHz output signal with an input referred voltage noise of less than nv/ Hz. This noise level and distortion performance has been previously achievable only with fully uncompensated amplifiers. The AD99 achieves this level of performance for gains as low as +. This new input stage also triples the achievable slew rate for comparably compensated nv/ Hz amplifiers. The simplified AD99 topology is shown in Figure. The amplifier is a single gain stage with a unity gain output buffer fabricated in Analog Devices extra fast complimentary bipolar process (XFCB). The AD99 has db of open-loop gain and maintains precision specifications such as CMRR, PSRR, VOS, and VOS/ T to levels that are normally associated with topologies having two or more gain stages. gm BUFFER V OUT R C C R L Figure. AD99 Topology The AD99 can be externally compensated down to a gain of through the use of an RC network. Above gains of, no external compensation network is required. To realize the full gain bandwidth product of the AD99, no PCB trace should be connected to or within close proximity of the external compensation pin for the lowest possible capacitance. External compensation allows the user to optimize the closedloop response for minimal peaking while increasing the gain bandwidth product in higher gains, lowering distortion errors that are normally more prominent with internally compensated parts in higher gains. For a fixed gain bandwidth, wideband distortion products would normally increase by db going from a closed-loop gain of to. Increasing the gain bandwidth product of the AD99 eliminates this effect with increasing closed-loop gain. The AD99 is available in both a SOIC and an LFCSP, each of which has a thermal pad for lower operating temperature. To help avoid this pad in board layout, both packages have an extra output pin on the opposite side of the package for ease in connecting a feedback network to the inputs. The secondary output pin also isolates the interaction of any capacitive load on the -- output and self-inductance of the package and bond wire from the feedback loop. While using the secondary output for feedback, inductance in the primary output will now help to isolate capacitive loads from the output impedance of the amplifier. Since the SOIC has greater inductance in its output, the SOIC will drive capacitive loads better than the LFCSP. Using the primary output for feedback with both packages will result in the LFCSP driving capacitive load better than the SOIC. The LFCSP and SOIC pinouts are identical, except for the rotation of all pins counterclockwise by one pin on the LFCSP. This isolates the inputs from the negative power supply pin, removing a mutually inductive coupling that is most prominent while driving heavy loads. For this reason, the LFCSP second harmonic, while driving a heavy load, is significantly better than that of the SOIC. A three-state input pin is provided on the AD99 for a high impedance power-down and an optional input bias current cancellation circuit. The high impedance output allows several AD99s to drive the same ADC or output line time interleaved. Pulling the DISABLE pin low activates the high impedance state. See Table for threshold levels. When the DISABLE pin is left floating, the AD99 operates normally. With the DISABLE pin pulled within. V of the positive supply, an optional input bias current cancellation circuit is turned on, which lowers the input bias current to less than na. In this mode, the user can drive the AD99 with a high dc source impedance and still maintain minimal output referred offset without having to use impedance matching techniques. In addition, the AD99 can be ac-coupled while setting the bias point on the input with a high dc impedance network. The input bias current cancellation circuit will double the input referred current noise, but this effect is minimal as long as wideband impedance is kept low (see Figure and Figure ). A pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the AD99. Each set of diodes has two series diodes, which are connected in anti-parallel. This limits the differential voltage between the inputs to approximately ±. V. All of the AD99 pins are ESD protected with voltage limiting diodes connected between both rails. The protection diodes can handle ma of steady state current. Currents should be limited to ma or less through the use of a series limiting resistor. Rev. B Page of

16 APPLICATIONS USING THE AD99 The AD99 offers unrivaled noise and distortion performance in low signal gain configurations. In low gain configurations (less than), the AD99 requires external compensation. The amount of gain and performance needed will determine the compensation network. Understanding the subtleties of the AD99 gives the user insight on how to exact its peak performance. Use the component values and circuit configurations shown in the Applications section as starting points for designs. Specific circuit applications will dictate the final configuration and value of your components. CIRCUIT COMPONENTS The circuit components are referenced in Figure 9, the recommended noninverting circuit schematic for the AD99. See Table for typical component values and performance data. V IN R R G R S DISABLE C F R F AD99 C.µF C µf +V S V S C µf C.µF R C C C C V OUT Figure 9. Wideband Noninverting Gain Configuration (SOIC) RF and RG The feedback resistor and the gain set resistor determine the noise gain of the amplifier; typical RF values range from Ω to 99 Ω. -- CF Creates a zero in the loop response to compensate the pole created by the input capacitance (including stray capacitance) and the feedback resistor RF. CF helps reduce high frequency peaking and ringing in the closed-loop response. Typical range is. pf to. pf for evaluation circuits used here. R This resistor terminates the input of the amplifier to the source resistance of the signal source, typically Ω. (This is application specific and not always required.) RS Many high speed amplifiers in low gain configurations require that the input stage be terminated into a nominal impedance to maintain stability. The value of RS should be kept to Ω or lower to maintain low noise performance. At higher gains, RS may be reduced or even eliminated. Typical range is Ω to Ω. CC The compensation capacitor decreases the open-loop gain at higher frequencies where the phase is degrading. By decreasing the open-loop gain here, the phase margin is increased and the amplifier is stabilized. Typical range is pf to pf. The value of CC is gain dependent. RC The series lead inductance of the package and the compensation capacitance (CC) forms a series resonant circuit. RC dampens this resonance and prevents oscillations. The recommended value of RC is Ω for a closed-loop gain of. This resistor introduces a zero in the open-loop response and must be kept low so that this zero occurs at a higher frequency. The purpose of the compensation network is to decrease the open-loop gain. If the resistance becomes too large, the gain will be reduced to the resistor value, and not necessarily to Ω, which is what a single capacitor would do over frequency. Typical value range is Ω to Ω. C To lower the impedance of RC, C is placed in parallel with RC. C is not required, but greatly reduces peaking at low closed-loop gains. The typical value range is pf to pf. C and C Bypass capacitors are connected between both supplies for optimum distortion and PSRR performance. These capacitors should be placed as close as possible to the supply pins of the amplifier. For C, C, a case size should be used. The case size offers reduced inductance and better frequency response. C and C Electrolytic bypass capacitors. Rev. B Page of

17 RECOMMENDED VALUES Table. Recommended Values and AD99 Performance Feedback Network Values Compensation Network Values Gain Package RF RG RS CF RC CC C db SS Bandwidth (MHz) Slew Rate (V/µs) Peaking (db) Output Noise (AD99 Only) (nv/ Hz) AD99 Total Output Noise Including Resistors (nv/ Hz), SOIC.. /./.. CSP... CSP... CSP/SOIC CSP/SOIC CSP/SOIC CIRCUIT CONFIGURATIONS Figure through Figure show typical schematics for the AD99 in various gain configurations. Table data was collected using the schematics shown in Figure through Figure. Resistor R, as shown in Figure through Figure, is the test equipment termination resistor. R is not required for normal operation, but is shown in the schematics for completeness. V IN R Ω R G Ω R S Ω DISABLE C F.pF R F Ω AD99 C.µF +V S C µf C.µF R C Ω C.pF R L kω V OUT V IN R Ω R G Ω R S Ω DISABLE C F pf R F Ω AD99 C.µF +V S C µf C.µF R C Ω C pf RL kω V OUT C µf C C pf C µf C C pf V S -- V S -- Figure. Amplifier Configuration for SOIC Package, Gain = Figure. Amplifier Configuration for CSP Package, Gain = V IN R G Ω R S Ω R Ω DISABLE C F.pF R F Ω AD99 C.µF +V S C µf C.µF R C Ω C.pF R L kω V OUT V IN R G Ω R S Ω R Ω DISABLE C F.pF R F Ω AD99 C.µF +V S C µf C.µF R C Ω C pf V OUT R L kω C µf C C pf C µf C C pf V S -- V S -- Figure. Amplifier Configuration for SOIC Package, Gain = + Figure. Amplifier Configuration for CSP Package, Gain = + Rev. B Page of

18 V IN R G Ω R S Ω R Ω DISABLE C F.pF R F 99Ω + FB AD99 D C.µF C µf V V S +V S +V C C C µf C.µF V O R C Ω C C pf R L kω V OUT Figure. Amplifier Configuration for CSP and SOIC Package, Gain = + -- V IN R G Ω R Ω DISABLE R F 99Ω + AD99 D FB C.µF C µf V V S +V S +V C C C µf C.µF R L kω V OUT Figure. Amplifier Configuration for CSP and SOIC Packages, Gain = + V O -- V IN R G Ω R Ω DISABLE R F 99Ω + FB AD99 D C.µF V +V S +V C C C µf C.µF V O R L kω V OUT C µf C C.pF V S -- Figure. Amplifier Configuration for CSP and SOIC Packages, Gain = + Rev. B Page of

19 PERFORMANCE VS. COMPONENT VALUES The influence that each component has on the AD99 frequency response can be seen in Figure and Figure. In Figure and Figure, all component values are held constant, except for the individual component shown, which is varied. For example, in the RS performance plot of Figure, all components are held constant except RS, which is varied from Ω to Ω.; and clearly indicates that RS has a major influence on peaking and bandwidth of the AD99. R G R S V IN R DISABLE SOIC PINOUT SHOWN C F R F AD99 C.µF C µf +V S V S C µf C.µF R C C C C -- V OUT 9 C = pf C =.pf R LOAD = kω SOIC PACKAGE C = pf -- 9 R LOAD = kω SOIC PACKAGE C C = pf C C = pf C C = pf 9 R LOAD = kω SOIC PACKAGE R C = Ω R C = Ω -- R C = Ω -- Figure. Frequency Response for Various Values of C, CC, RC Rev. B Page 9 of

20 9 R F = R G = 9 C F =.pf R LOAD = kω SOIC PACKAGE R F = R G = R F = R G = -- R LOAD = kω SOIC PACKAGE C F = pf C F =.pf -- 9 R LOAD = kω SOIC PACKAGE R S = R S = R S = -- R G R S V IN R DISABLE SOIC PINOUT SHOWN C F R F AD99 C.µF C µf +V S V S C µf C.µF R C C C C -- V OUT Figure. Frequency Response for Various Values of RF, CF, RS TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN To analyze the noise performance of an amplifier circuit, the individual noise sources must be identified. Then determine if the source has a significant contribution to overall noise performance of the amplifier. To simplify the noise calculations, we will work with noise spectral densities, rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nv/ Hz, is equivalent to the noise in a Hz bandwidth). The noise model shown in Figure 9 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally specified RTI (referred to input), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise. All resistors have a Johnson noise of (kbtr), where k is Boltzmann s Constant (. J/K), T is the absolute temperature in Kelvin, B is the bandwidth in Hz, and R is the resistance in ohms. A simple relationship, which is easy to remember, is that a Ω resistor generates a Johnson noise of nv Hz at C. The AD99 amplifier has roughly the same equivalent noise as a Ω resistor. Rev. B Page of

21 B A V N, R ktr V N, R ktr R R RTI NOISE = I N I N+ V N V N, R ktr R V R N + ktr + ktr R + R GAIN FROM "A" TO OUTPUT = NOISE GAIN = NG = + R R GAIN FROM "B" TO OUTPUT = R R I N+ R + I R R + N + ktr R + R RTO NOISE = NG RTI NOISE V OUT R R + R -- For RTO calculations, the input offset voltage and the voltage generated by the bias current flowing through R are multiplied by the noise gain of the amplifier. The voltage generated by IB through R is summed together with the previous offset voltages to arrive at a final output offset voltage. The offset voltage can also be referred to the input (RTI) by dividing the calculated output offset voltage by the noise gain. As seen in Figure if IB+ and IB are the same and R equals the parallel combination of R and R, then the RTI offset voltage can be reduced to only VOS. This is a common method used to reduce output offset voltage. Keeping resistances low helps to minimize offset error voltage and keeps the voltage noise low. Figure 9. Op Amp Noise Analysis Model In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table. INPUT BIAS CURRENT AND DC OFFSET In high noise gain configurations, the effects of output offset voltage can be significant, even with low input bias currents and input offset voltages. Figure shows a comprehensive offset voltage model, which can be used to determine the referred to output (RTO) offset voltage of the amplifier or referred to input (RTI) offset voltage. DISABLE PIN AND INPUT BIAS CANCELLATION The AD99 DISABLE pin performs three functions; enable, disable, and reduction of the input bias current. When the DISABLE pin is brought to within. V of the positive supply, the input bias current is reduced by an approximate factor of. However, the input current noise doubles to. pa/ Hz. Table outlines the DISABLE pin functionality. Table. DISABLE Pin Truth Table Supply Voltage ± V + V Disable to +. to. Enable Open Open Low Input Bias Current. to. to R GAIN FROM "A" TO OUTPUT = B R I B NOISE GAIN = NG = + R R A R I B+ V OS V OUT GAIN FROM "B" TO OUTPUT = R R OFFSET (RTO) = V OS + R + I B+ R + R I B R R R OFFSET (RTI) = V OS + I B+ R I B R R R + R FOR BIAS CURRENT CANCELLATION: OFFSET (RTI) = V OS IF I B+ = I B AND R = R R R + R -- Figure. Op Amp Total Offset Voltage Model Rev. B Page of

22 AVDD.µF.µF DVDD V IN R G Ω R S Ω DISABLE R F Ω AD99 +V S C µf C.µF R C Ω C pf R Ω REF µf µf C.nF AGND AVDD DGND DVDD REF AD REFGND IN INGND +.V R 9Ω R 9Ω C µf C.µF V S C C 9pF -- -BIT ADC DRIVER Ultralow noise and distortion performance make the AD99 an ideal ADC driver. Even though the AD99 is not unity gain stable, it can be configured to produce a net gain of + amplifier, as shown in Figure. This is achieved by combining a gain of + and a gain of for a net gain of +. The input range of the ADC is V to. V. Table shows the performance data of the AD99 and the Analog Devices AD a MSPS -bit ADC. Figure. ADC Driver Table. ADC Driver Performance, fc = khz, VOUT =. V p-p Parameter Measurement (db) Second Harmonic Distortion. Third Harmonic Distortion. THD. SFDR. SNR. Rev. B Page of

23 CIRCUIT CONSIDERATIONS Optimizing the performance of the AD99 requires attention to detail in layout and signal routing of the board. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. The AD99 features an exposed paddle on the backs of both the CSP and SOIC packages. The exposed paddle provides a low thermal resistive path to the ground plane. For best performance, solder the exposed paddle to the ground plane. PCB Layout The compensation network is determined by the amplifier gain requirements. For lower gains, the layout and component placement are more critical. For higher gains, there are fewer compensation components, which results in a less complex layout. With diligent consideration to layout, grounding, and component placement, the AD99 evaluation boards have been optimized for peak performance. These are the same evaluation boards that are available to customers; see Table for ordering information. The noninverting evaluation board artwork for SOIC and CSP layouts are shown in Figure and Figure. Incorporating the layout information shown in Figure and Figure into new designs is highly recommended and helps to ensure optimal circuit performance. The concepts of layout, grounding, and component placement, llustrated in Figure and Figure,also apply to inverting configurations. For scale, the boards are. Parasitics The area surrounding the compensation pin is very sensitive to parasitic capacitance. To realize the full gain bandwidth product of the AD99, there should be no trace connected to or within close proximity of the external compensation pin for the lowest possible capacitance. When compensation is required, the traces to the compensation pin, the negative supply, and the interconnect between components (i.e. CC, C, and RC in Figure 9) should be made as wide as possible to minimize inductance. All ground and power planes under the pins of the AD99 should be cleared of copper to prevent parasitic capacitance between the input and output pins to ground. A single mounting pad on a SOIC footprint can add as much as. pf of capacitance to ground as a result of not clearing the ground or power plane under the AD99 pins. Parasitic capacitance can cause peaking and instability, and should be minimized to ensure proper operation. The new pinout of the AD99 reduces the distance between the output and the inverting input of the amplifier. This helps to minimize the parasitic inductance and capacitance of the feedback path, which, in turn, reduces ringing and second harmonic distortion. Grounding When possible, ground and power planes should be used. Ground and power planes reduce the resistance and inductance of the power supply feeds and ground returns. If multiple planes are used, they should be stitched together with multiple vias. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the AD99 as possible. Ground vias should be placed at the very end of the component mounting pad to provide a solid ground return. The output load ground and the bypass capacitor grounds should be returned to a common point on the ground plane to minimize parasitic inductance and improve distortion performance. The AD99 packages feature an exposed paddle. For optimum performance, solder this paddle to ground. For more information on PCB layout and design considerations, refer to section - of the Analog Devices Op Amp Applications book. Power Supply Bypassing The AD99 power supply bypassing has been optimized for each gain configuration as shown in Figure through Figure in the Circuit Configurations section. The values shown should be used when possible. Bypassing is critical for stability, frequency response, distortion, and PSRR performance. The. µf capacitors shown in Figure through Figure should be as close to the supply pins of the AD99 as possible and the electrolytic capacitors beside them. Component Selection Smaller components less than SMT case size, offer smaller mounting pads, which have less parasitics and allow for a more compact layout. It is critical for optimum performance that high quality, tight tolerance (where critical), and low drift components be used. For example, tight tolerance and low drift is critical in the selection of the feedback capacitor used in Figure. The feedback compensation capacitor in Figure is.pf. This capacitor should be specified with NPO material. NPO material typically has a ± ppm/ C change over C to + C temperature range. For a C change, this would result in a. ff change in capacitance, compared to an XR material, which would result in a. pf change, a % change from the nominal value. This could introduce excessive peaking, as shown in Figure, CF vs. Frequency Response. DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools. ADI offers technical support via free evaluation boards, sample ICs, SPICE models, interactive evaluation tools, application notes, phone and support all available at Rev. B Page of

24 -A- Figure. SOIC Evaluation Board Artwork -A- Figure. CSP Evaluation Board Artwork Evaluation Boards There are four different evaluation boards available, as shown in Table, and an Application Note, AN-, that explains the use of the evaluation boards. Table. Evaluation Board Selection Guide Package Type Board Configuration CSP SOIC Inverting EVAL-ADOPAMP-CSP-I EVAL-ADOPAMP-R-IN Noninverting EVAL-ADOPAMP-CSP-N EVAL-ADOPAMP-R-NI Rev. B Page of

25 OUTLINE DIMENSIONS. (.).9 (.). (.). (.9).9 (.9). (.9) TOP VIEW. (.). (.). (.) BOTTOM VIEW (PINS UP).9 (.9).9 (.9). (.9). (.9) COPLANARITY. SEATING PLANE. (.) BSC. (.9). (.). (.). (.). (.9). (.). (.). (.). (.). (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure. -Lead Standard Small Outline Package [SOIC-ED] (RD--) PIN INDICATOR. BSC SQ TOP VIEW. BSC SQ.. BSC... MAX. PIN INDICATOR BOTTOM VIEW. REF MAX. MAX.TYP. MAX. NOM. MIN... SEATING PLANE.... REF Figure. -Lead Plastic Surface-Mount Package [CSP] (CP-) Dimensions shown in millimeters Rev. B Page of

26 ORDERING GUIDE Model Minimum Ordering Quantity Temperature Range Package Description Branding Package Option AD99ARD C to + C -Lead SOIC-ED RD-- AD99ARD-REEL, C to + C -Lead SOIC-ED RD-- AD99ARD-REEL, C to + C -Lead SOIC-ED RD-- AD99ARDZ C to + C -Lead SOIC-ED RD-- AD99ARDZ-REEL, C to + C -Lead SOIC-ED RD-- AD99ARDZ-REEL, C to + C -Lead SOIC-ED RD-- AD99ACP-R C to + C -Lead CSP HDB CP- AD99ACP-REEL, C to + C -Lead CSP HDB CP- AD99ACP-REEL, C to + C -Lead CSP HDB CP- AD99ACPZ-R C to + C -Lead CSP HDB CP- AD99ACPZ-REEL, C to + C -Lead CSP HDB CP- AD99ACPZ-REEL, C to + C -Lead CSP HDB CP- Z = Pb free Rev. B Page of

27 NOTES Rev. B Page of

28 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /(B) Rev. B Page of