Low Noise Rail-to-Rail Differential ADC Driver AD8139

Transcription

1 Low Noise Rail-to-Rail Differential ADC Driver AD89 FEATURES Fully differential Low noise. nv/ Hz. pa/ Hz Low harmonic distortion 98 dbc MHz 8 dbc MHz 7 dbc MHz High speed 4 MHz, db BW (G = ) 8 V/µs slew rate 4 ns settling time to.% 69 db output MHz 8 db dc CMRR Low offset: ±. mv max Low input offset current:. µa max Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Wide supply voltage range: V to V Available in small SOIC package GENERAL DESCRIPTION The AD89 is an ultralow noise, high performance differential amplifier with rail-to-rail output. With its low noise, high SFDR, and wide bandwidth, it is an ideal choice for driving ADCs with resolutions to 8 bits. The AD89 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order harmonic distortion products. Fully differential and singleended-to-differential gain configurations are easily realized by the AD89. Simple external feedback networks consisting of a total of four resistors determine the amplifier s closed-loop gain. The AD89 is manufactured on ADI s proprietary second generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only.8 nv/ Hz. APPLICATIONS ADC drivers to 8 bits Single-ended-to-differential converters Differential filters Level shifters Differential PCB board drivers Differential cable drivers FUNCTIONAL BLOCK DIAGRAM IN V OCM V+ +OUT 4 AD89 NC = NO CONNECT Figure IN NC V OUT The AD89 is available in an 8-lead SOIC package with an exposed paddle (EP) on the underside of its body and a mm mm LFCSP. It is rated to operate over the temperature range of 4 C to + C. INPUT VOLTAGE NOISE (nv/ Hz) k k k M M M G FREQUENCY (Hz) Figure. Input Voltage Noise vs. Frequency Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD89 TABLE OF CONTENTS VS = ± V, VOCM = V Specifications... VS = V, VOCM =. V Specifications... Absolute Maximum Ratings... 7 Thermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Typical Connection and Definition of Terms... 8 Applications... 9 Estimating Noise, Gain, and Bandwidth with Matched Feedback Networks... 9 Outline Dimensions... 4 Ordering Guide... 4 Typical Performance Characteristics... 9 Theory of Operation... 8 REVISION HISTORY 8/4 Data Sheet Changed from a Rev. to Rev. A. Added 8-Lead LFCSP...Universal Changes to General Description... Changes to Figure... Changes to VS = ± V, VOCM = V Specifications... Changes to VS = V, VOCM =. V Specifications... Changes to Table Changes to Maximum Power Dissipation Section... 7 Changes to Figure 6 and Figure 9... Inserted Figure 9 and Figure Changes to Figure 4 to Figure Inserted Figure Changes to Figure and Figure... 6 Changes to Figure and Figure Changes to Table Changes to Voltage Gain Section... 9 Changes to Driving a Capacitive Load Section... Changes to Ordering Guide... 4 Updated Outline Dimensions... 4 /4 Revision : Initial Version Rev. A Page of 4

3 V S = ± V, V OCM = V C, Diff. Gain =, RL, dm = kω, RF = RG = Ω, unless otherwise noted. TMIN to TMAX = 4 C to + C. AD89 Table. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE db Small Signal Bandwidth VO, dm =. V p-p 4 4 MHz db Large Signal Bandwidth VO, dm = V p-p 4 MHz Bandwidth for. db Flatness VO, dm =. V p-p 4 MHz Slew Rate VO, dm = V Step 8 V/µs Settling Time to.% VO, dm = V Step, CF = pf 4 ns Overdrive Recovery Time G =, VIN, dm = V p-p Triangle Wave ns NOISE/HARMONIC PERFORMANCE SFDR VO, dm = V p-p, fc = MHz 98 db VO, dm = V p-p, fc = MHz 8 db VO, dm = V p-p, fc = MHz 7 db Third-Order IMD VO, dm = V p-p, fc =. MHz ±. MHz 9 dbc Input Voltage Noise f = KHz. nv/ Hz Input Current Noise f = KHz. pa/ Hz DC PERFORMANCE Input Offset Voltage VIP = VIN = VOCM = V ± + µv Input Offset Voltage Drift TMIN to TMAX. µv/ºc Input Bias Current TMIN to TMAX. 8. µa Input Offset Current.. µa Open-Loop Gain 4 db INPUT CHARACTERISTICS Input Common-Mode Voltage Range 4 +4 V Input Resistance Differential 6 kω Common Mode. MΩ Input Capacitance Common Mode. pf CMRR VICM = ± V dc, RF = RG = kω 8 84 db OUTPUT CHARACTERISTICS Output Voltage Swing Each Single-Ended Output, RF = RG = kω VS +. +VS. V Each Single-Ended Output, VS +. +VS. V RL, dm = Open Circuit, RF = RG = kω Output Current Each Single-Ended Output ma Output Balance Error f = MHz 69 db VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE db Bandwidth VO, cm =. V p-p MHz Slew Rate VO, cm = V p-p V/µs Gain V/V VOCM INPUT CHARACTERISTICS Input Voltage Range V Input Resistance. MΩ Input Offset Voltage VOS, cm = VO, cm VOCM; VIP = VIN = VOCM = V 9 ± +9 µv Input Voltage Noise f = khz. nv/ Hz Input Bias Current. 4. µa CMRR VOCM/ VO, dm, VOCM = ± V db Rev. A Page of 4

4 AD89 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 4. ±6 V Quiescent Current 4.. ma +PSRR Change in +VS = ±V 9 db PSRR Change in VS = ±V 9 9 db OPERATING TEMPERATURE RANGE 4 + C Rev. A Page 4 of 4

5 V S = V, V OCM =. V C, Diff. Gain =, RL, dm = kω, RF = RG = Ω, unless otherwise noted. TMIN to TMAX = 4 C to + C. AD89 Table. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE db Small Signal Bandwidth VO, dm =. V p-p 8 MHz db Large Signal Bandwidth VO, dm = V p-p 6 MHz Bandwidth for. db Flatness VO, dm =. V p-p 4 MHz Slew Rate VO, dm = V Step 4 V/μs Settling Time to.% VO, dm = V Step ns Overdrive Recovery Time G =, VIN, dm = 7 V p-p Triangle Wave ns NOISE/HARMONIC PERFORMANCE SFDR VO, dm = V p-p, fc = MHz 99 db VO, dm = V p-p, fc = MHz, (RL = 8 Ω) 87 db VO, dm = V p-p, fc = MHz, (RL = 8 Ω) 7 db Third-Order IMD VO, dm = V p-p, fc =. MHz ±. MHz 87 dbc Input Voltage Noise f = khz. nv/ Hz Input Current Noise f = khz. pa/ Hz DC PERFORMANCE Input Offset Voltage VIP = VIN = VOCM = V ± + µv Input Offset Voltage Drift TMIN to TMAX. µv/ºc Input Bias Current TMIN to TMAX. 7. μa Input Offset Current.. µa Open-Loop Gain db INPUT CHARACTERISTICS Input Common-Mode Voltage Range 4 V Input Resistance Differential 6 KΩ Common-Mode. MΩ Input Capacitance Common-Mode. pf CMRR VICM = ± V dc, RF = RG = kω 7 79 db OUTPUT CHARACTERISTICS Output Voltage Swing Each Single-Ended Output, RF = RG = kω VS +. +VS. V Each Single-Ended Output, VS +. +VS. V RL, dm = Open Circuit, RF = RG = kω Output Current Each Single-Ended Output 8 ma Output Balance Error f = MHz 7 db VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE db Bandwidth VO, cm =. V p-p 44 MHz Slew Rate VO, cm = V p-p V/μs Gain V/V VOCM INPUT CHARACTERISTICS Input Voltage Range..8 V Input Resistance. MΩ Input Offset Voltage VOS, cm = VO, cm VOCM; VIP = VIN = VOCM =. V. ±.4 +. mv Input Voltage Noise f = KHz. nv/ Hz Input Bias Current. 4. μa CMRR VOCM/ VO(dm), VOCM = ± V db Rev. A Page of 4

6 AD89 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range +4. ±6 V Quiescent Current.. ma +PSRR Change in +VS = ± V db PSRR Change in VS = ± V 9 db OPERATING TEMPERATURE RANGE 4 + C Rev. A Page 6 of 4

7 AD89 ABSOLUTE MAXIMUM RATINGS Table. Parameter Supply Voltage Rating V VOCM ±VS Power Dissipation See Figure Input Common-Mode Voltage ±VS Storage Temperature C to + C Operating Temperature Range C to + C Lead Temperature Range C (Soldering sec) Junction Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, i.e., θja is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type θja Unit SOIC-8 with EP/4-Layer 7 C/W LFCSP/4-Layer 7 C/W Maximum Power Dissipation The maximum safe power dissipation in the AD89 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD89. Exceeding a junction temperature of 7 C for an extended period of time can result in changes in the silicon devices potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a kω differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θja. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the θja. Figure shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle (EP) SOIC-8 (θja = 7 C/W) package and LFCSP (θja = 7 C/W) on a JEDEC standard 4-layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (W) SOIC AND LFCSP AMBIENT TEMPERATURE ( C) Figure. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A Page 7 of 4

8 AD89 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN AD89 8 +IN V OCM 7 NC V+ 6 V +OUT 4 NC = NO CONNECT OUT Figure 4. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic Description IN Inverting Input. VOCM An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the amplifier s operation remains linear. V+ Positive Power Supply Voltage. 4 +OUT Positive Side of the Differential Output. OUT Negative Side of the Differential Output. 6 V Negative Power Supply Voltage. 7 NC No Internal Connection. 8 +IN Noninverting Input. R F V TEST TEST SIGNAL SOURCE Ω Ω 6.4Ω 6.4Ω R G = Ω C F V OCM AD89 R L, dm = kω V O, dm + R G = Ω C F R F Figure. Basic Test Circuit V TEST TEST SIGNAL SOURCE Ω Ω 6.4Ω 6.4Ω R F = Ω R G = Ω R S V OCM AD89 C L, dm R L, dm V O, dm + R G = Ω R S R F = Ω Figure 6. Capacitive Load Test Circuit, G = + Rev. A Page 8 of 4

9 TYPICAL PERFORMANCE CHARACTERISTICS AD89 Unless otherwise noted, Diff. Gain = +, RG = RF = Ω, RL, dm = kω, VS = ± V, TA = C, VOCM = V. Refer to the basic test circuit in Figure for the definition of terms. NORMALIZED CLOSED-LOOP GAIN (db) CLOSED-LOOP GAIN (db) 9 G = G = G = G = R G = Ω V O, dm =.V p-p Figure 7. Small Signal Frequency Response for Various Gains 4 V S = +V 9 V O, dm =.V p-p Figure 8. Small Signal Frequency Response for Various Power Supplies CLOSED-LOOP GAIN (db) 9 + C +8 C C V O, dm =.V p-p + C Figure 9. Small Signal Frequency Response at Various ΩTemperatures NORMALIZED CLOSED-LOOP GAIN (db) CLOSED-LOOP GAIN (db) 9 R G = Ω V O, dm =.V p-p G = G = G = G = Figure. Large Signal Frequency Response for Various Gains 9 V O, dm =.V p-p V S = +V Figure. Large Signal Frequency Response for Various Power Supplies CLOSED-LOOP GAIN (db) 9 + C +8 C C + C V O, dm =.V p-p Figure. Large Signal Frequency Response at Various Temperatures Rev. A Page 9 of 4

10 AD89 CLOSED-LOOP GAIN (db) CLOSED-LOOP GAIN (db) R L = Ω R L = Ω R L = Ω 9 V O, dm =.V p-p R L = kω Figure. Small Signal Frequency Response for Various Loads C F = pf C F = pf C F = pf 9 V O, dm =.V p-p Figure 4. Small Signal Frequency Response for Various CF CLOSED-LOOP GAIN (db) CLOSED-LOOP GAIN (db) R L = Ω R L = Ω R L = kω 9 V O, dm =.V p-p R L = Ω Figure 6. Large Signal Frequency Response for Various Loads C F = pf C F = pf C F = pf 9 V O, dm =.V p-p Figure 7. Large Signal Frequency Response for Various CF CLOSED-LOOP GAIN (db) 6 V OCM = +4.V V OCM = +4V V OCM =.V 4 V OCM = V V OCM = V V O, dm =.V p-p 9 Figure. Small Signal Frequency Response at Various VOCM NORMALIZED CLOSED-LOOP GAIN (db) R L = Ω (V O, dm =.V p-p) R L = Ω (V O, dm =.V p-p) R L = kω (V O, dm =.V p-p) R L = kω (V O, dm =.V p-p). FREQUENCY (Hz) Figure 8.. db Flatness for Various Loads and Output Amplitudes Rev. A Page of 4

11 AD89 V O, dm =.V p-p V O, dm =.V p-p DISTORTION (dbc) 9 V S = +V DISTORTION (dbc) 9 V S = +V. Figure 9. Second Harmonic Distortion vs. Frequency and Supply Voltage Figure. Third Harmonic Distortion vs. Frequency and Supply Voltage V O, dm =.V p-p V O, dm =.V p-p DISTORTION (db) G = G = 9 G =. Figure. Second Harmonic Distortion vs. Frequency and Gain DISTORTION (db) 9 G = G = G =. Figure. Third Harmonic Distortion vs. Frequency and Gain V O, dm =.V p-p V O, dm =.V p-p DISTORTION (dbc) 9 R L = Ω R L = Ω R L = Ω R L = kω DISTORTION (dbc) 9 R L = Ω R L = Ω R L = Ω. Figure. Second Harmonic Distortion vs. Frequency and Load R L = kω. Figure 4. Third Harmonic Distortion vs. Frequency and Load Rev. A Page of 4

12 AD89 V O, dm =.V p-p V O, dm =.V p-p DISTORTION (dbc) 9 R F = Ω R F = Ω DISTORTION (dbc) 9 R F = Ω R F = kω. Figure. Second Harmonic Distortion vs. Frequency and RF R F = kω R F = Ω. Figure 8. Third Harmonic Distortion vs. Frequency and RF F C = MHz V S = +V 9 F C = MHz V S = +V DISTORTION (dbc) DISTORTION (dbc) V O, dm (V p-p) Figure 6. Second Harmonic Distortion Vs. Output Amplitude V O, dm (V p-p) Figure 9. Third Harmonic Distortion vs. Output Amplitude V O, dm = V p-p F C = MHz V O, dm = V p-p F C = MHz DISTORTION (dbc) 9 SECOND HARMONIC DISTORTION (dbc) 9 SECOND HARMONIC THIRD HARMONIC V OCM (V) Figure 7. Harmonic Distortion vs. VOCM, VS = + V THIRD HARMONIC 4 V OCM (V) Figure. Harmonic Distortion vs. VOCM, VS = ± V Rev. A Page of 4

13 AD89 V O, dm (V) 7 V O, dm = mv p-p C F = pf (C F = pf, ) V O, dm (C F = pf, ) V O, dm (V) C F = pf C F = pf C F = pf C F = pf 4V p-p V p-p.. TIME (ns) ns/div TIME (ns) ns/div Figure. Small Signal Transient Response for Various CF Figure 4. Large Signal Transient Response For CF..7 R S =.6Ω C L, dm = pf.. R S = 6.4Ω C L, dm = pf. V O, dm (V).. R S = 6.4Ω C L, dm = pf V O, dm (V).. R S =.6Ω C L, dm = pf..7. TIME (ns) ns/div TIME (ns) ns/div Figure. Small Signal Transient Response for Capacitive Loads Figure. Large Signal Transient Response for Capacitive Loads NORMALIZED OUTPUT (dbc) 9 9 V O, dm = V p-p F C = MHz F C =.MHz Figure. Intermodulation Distortion AMPLITUDE (V) V O, dm V IN TIME (ns) C F = pf V O, dm =.V p-p ERROR Figure 6. Settling Time (.%) ns/div 6 4 ERROR (µv) DIV =.% Rev. A Page of 4

14 AD89 V OCM (V) ±V +V V O, cm = V p-p V IN, dm = V TIME (ns) ns/div CLOSED-LOOP GAIN (db) 6 4 V S = +V V O, cm =.V p-p V O, cm =.V p-p V S = +V Figure 7. VOCM Large Signal Transient Response V IN, cm =.V p-p INPUT CMRR = V O, cm / V IN, cm Figure 4. VOCM Frequency Response for Various Supplies V O, cm =.V p-p V OCM CMRR = V O, dm / V O, cm CMRR (db) R F = R G = kω R F = R G = Ω V OCM CMRR (db) Figure 8. CMRR vs. Frequency Figure 4. VOCM CMRR vs. Frequency INPUT VOLTAGE NOISE (nv/ Hz) V OCM NOISE (nv/ Hz) k k k M M M G FREQUENCY (Hz) k k k M M M G FREQUENCY (Hz) Figure 9. Input Voltage Noise vs. Frequency Figure 4. VOCM Voltage Noise vs. Frequency Rev. A Page 4 of 4

15 AD89 R L, dm = kω PSRR = V O, dm / V S 4 8 G = V IN, dm V O, dm PSRR (db) PSRR +PSRR VOLTAGE (V) Figure 4. PSRR vs. Frequency V S = +V TIME (ns) Figure 46. Overdrive Recovery V O, dm = V p-p OUTPUT BALANCE = V O, cm / V O, dm ns/div SINGLE-ENDED OUTPUT SWING FROM RAIL (mv) OUTPUT IMPEDANCE (Ω)... Figure 44. Single-Ended Output Impedance vs. Frequency V S = +V V S+ V OP V ON V S k k RESISTIVE LOAD (Ω) Figure 4. Output Saturation Voltage vs. Output Load V OP SWING FROM RAIL (mv) OUTPUT BALANCE (db) Figure 47. Output Balance vs. Frequency G = (R F = R G = Ω) R L, dm = kω V S+ V OP V ON V S TEMPERATURE ( C) Figure 48. Output Saturation Voltage vs. Temperature V ON SWING FROM RAIL (mv) Rev. A Page of 4

16 AD I OS I BIAS (µa)... I BIAS 4 9 I OS (na) SUPPLY CURRENT (ma) 4 V S = +V TEMPERATURE ( C) TEMPERATURE ( C) Figure 49. Input Bias and Offset Current vs. Temperature Figure. Supply Current vs. Temperature 6 INPUT BIAS CURRENT (µa) V S = +V 4 V ACM (V) V OS, dm (µv) V OS, cm 4 V OS, dm TEMPERATURE ( C) V OS, cm (µv) Figure. Input Bias Current vs. Input Common-Mode Voltage V S = ±.V 4 4 Figure. Offset Voltage vs. Temperature COUNT = MEAN = µv STD DEV = µv V OUT, cm (V) FREQUENCY 4 V OCM (V) Figure. VO, cm vs. VOCM Input Voltage V OS, dm (µv) Figure 4. VOS, dm Distribution Rev. A Page 6 of 4

17 AD I VOCM (µa) V OCM CURRENT (µa) V S = +V TEMPERATURE ( C) Figure. VOCM Bias Current vs. Temperature V OCM (V) Figure 6. VOCM Bias Current vs. VOCM Input Voltage Rev. A Page 7 of 4

18 AD89 THEORY OF OPERATION The AD89 is a high speed, low noise differential amplifier fabricated on the Analog Devices second generation extra Fast Complementary Bipolar (XFCB) process. It is designed to provide two closely balanced differential outputs in response to either differential or single-ended input signals. Differential gain is set by external resistors, similar to traditional voltagefeedback operational amplifiers. The common-mode level of the output voltage is set by a voltage at the VOCM pin and is independent of the input common-mode voltage. The AD89 has an H-bridge input stage for high slew rate, low noise, and low distortion operation and rail-to-rail output stages that provide maximum dynamic output range. This set of features allows for convenient single-ended-to-differential conversion, a common need to take advantage of modern high resolution ADCs with differential inputs. TYPICAL CONNECTION AND DEFINITION OF TERMS Figure 7 shows a typical connection for the AD89, using matched external RF/RG networks. The differential input terminals of the AD89, VAP and VAN, are used as summing junctions. An external reference voltage applied to the VOCM terminal sets the output common-mode voltage. The two output terminals, VOP and VON, move in opposite directions in a balanced fashion in response to an input signal. C F balanced differential outputs of identical amplitude and exactly 8 degrees out of phase. The output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. Low frequency output balance is limited ultimately by the mismatch of an on-chip voltage divider, which is trimmed for optimum performance. Output balance is measured by placing a well matched resistor divider across the differential voltage outputs and comparing the signal at the divider s midpoint with the magnitude of the differential output. By this definition, output balance is equal to the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differentialmode voltage: ΔVO, cm Output Balance = () ΔV O, dm The block diagram of the AD89 in Figure 8 shows the external differential feedback loop (RF/RG networks and the differential input transconductance amplifier, GDIFF) and the internal common-mode feedback loop (voltage divider across VOP and VON and the common-mode input transconductance amplifier, GCM). The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other. R F V AN = V AP (4) V IP V OCM V IN R G R G V AP V AN + AD89 V ON V OP R L, dm V O, dm + The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two Ω resistors, to equal the voltage set at the VOCM terminal. This ensures that R F C F Figure 7. Typical Connection The differential output voltage is defined as V O, dm VOP VON = () Common-mode voltage is the average of two voltages. The output common-mode voltage is defined as V O, cm Output Balance VOP + VON = () Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 8 degrees out of phase with each other. It is the internal common-mode feedback loop that forces the signal component of the output common-mode towards zero, resulting in the near perfectly VO, dm V OP = VOCM + () and V ON R G V IN V AN V AP V IP R G VO, dm = VOCM (6) R F pf + G O Ω MIDSUPPLY G DIFF G CM Ω G O + pf R F Figure 8. Block Diagram V OP V OCM V ON Rev. A Page 8 of 4

19 AD89 APPLICATIONS ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage The total output noise is calculated as the root-sum-squared total of several statistically independent sources. Since the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 6 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed-loop gains. For most applications, % resistors are sufficient. Table 6. Recommended Values of Gain-Setting Resistors and Voltage Noise for Various Closed-Loop Gains db Bandwidth (MHz) Gain RG (Ω) RF (Ω) k 9.7 k 6 7 Total Output Noise (nv/ Hz) The differential output voltage noise contains contributions from the AD89 s input voltage noise and input current noise as well as those from the external feedback networks. The contribution from the input voltage noise spectral density is computed as R = + F Vo_n vn, or equivalently, vn/β (7) RG where vn is defined as the input-referred differential voltage noise. This equation is the same as that of traditional op amps. The contribution from the input current noise of each input is computed as Vo_n = i n ( R F ) (8) where in is defined as the input noise current of one input. Each input needs to be treated separately since the two input currents are statistically independent processes. The contribution from each RG is computed as RF Vo_n = 4kTRG (9) RG This result can be intuitively viewed as the thermal noise of each RG multiplied by the magnitude of the differential gain. The contribution from each RF is computed as Vo _ n4 = 4kTR F () Voltage Gain The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the previous definitions. Referring to Figure 7, (CF = ) and setting VIN = one can write VIP V R G AP V = AP V R F ON () RG V AN = VAP = VOP () RF + RG Solving the above two equations and setting VIP to Vi gives the gain relationship for VO, dm/vi. RF V OP VON = VO, dm = Vi () R G An inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to VIN and setting VIP =. For a balanced differential input, the gain from VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP VIN. Feedback Factor Notation When working with differential amplifiers, it is convenient to introduce the feedback factor β, which is defined as RG β = (4) R + R F G This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched. Input Common-Mode Voltage The linear range of the VAN and VAP terminals extends to within approximately V of either supply rail. Since VAN and VAP are essentially equal to each other, they are both equal to the amplifier s input common-mode voltage. Their range is indicated in the Specifications tables as input common-mode range. The voltage at VAN and VAP for the connection diagram in Figure 7 can be expressed as V AN = VAP = VACM = RF ( VIP + V RF + RG IN ) RG + RF + R G V OCM where VACM is the common-mode voltage present at the amplifier input terminals. () Rev. A Page 9 of 4

20 AD89 Using the β notation, Equation can be written as V ACM or equivalently, V ACM OCM ( β) V ICM = βv + (6) ICM ( V V ) = V + β (7) OCM ICM where VICM is the common-mode voltage of the input signal, i.e., VIP + VIN VICM =. For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges. Calculating Input Impedance The input impedance of the circuit in Figure 7 will depend on whether the amplifier is being driven by a single-ended or a differential signal source. For balanced differential input signals, the differential input impedance (RIN, dm) is simply R = R (8) IN, dm G For a single-ended signal (for example, when VIN is grounded and the input signal drives VIP), the input impedance becomes R IN RG = (9) RF ( R + R ) G F The input impedance of a conventional inverting op amp configuration is simply RG, but it is higher in Equation 9 because a fraction of the differential output voltage appears at the summing junctions, VAN and VAP. This voltage partially bootstraps the voltage across the input resistor RG, leading to the increased input resistance. Input Common-Mode Swing Considerations In some single-ended-to-differential applications, when using a single-supply voltage attention must be paid to the swing of the input common-mode voltage, VACM. Consider the case in Figure 9, where VIN is V p-p swinging about a baseline at ground and VREF is connected to ground. V Ω.µF.µF.µF 4Ω Ω +.V GND.V.V V IN V REF Ω V OCM Ω 8 + AD Ω Ω.7nF.7nF IN AVDD AD7674 DVDD IN+ DGND AGND REFGND REF REFBUFIN PDBUF V ACM WITH V REF = +.7V +.9V +.V.µF 47µF ADR4.V REFERENCE Figure 9. AD89 Driving AD7674, 8-Bit, 8 ksps A/D Converter Rev. A Page of 4

21 AD89 The circuit has a differential gain of.6 and β =.8. VICM has an amplitude of. V p-p and is swinging about ground. Using the results in Equation 6, the common-mode voltage at the AD89 s inputs, VACM, is a. V p-p signal swinging about a baseline of.9 V. The maximum negative excursion of VACM in this case is. V, which exceeds the lower input common-mode voltage limit. One way to avoid the input common-mode swing limitation is to bias VIN and VREF at midsupply. In this case, VIN is V p-p swinging about a baseline at. V and VREF is connected to a low-z. V source. VICM now has an amplitude of. V p-p and is swinging about. V. Using the results in Equation 7, VACM is calculated to be equal to VICM because VOCM = VICM. Therefore, VACM swings from. V to.7 V, which is well within the input common-mode voltage limits of the AD89. Another benefit seen in this example is that since VOCM = VACM = VICM no wasted common-mode current flows. Figure 6 illustrates how to provide the low-z bias voltage. For situations that do not require a precise reference, a simple voltage divider will suffice to develop the input voltage to the buffer. V This estimate assumes a minimum 9 degree phase margin for the amplifier loop, which is a condition approached for gains greater than 4. Lower gains will show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin. Estimating DC Errors Primary differential output offset errors in the AD89 are due to three major components: the input offset voltage, the offset between the VAN and VAP input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the input and output common-mode voltages in conjunction with matching errors in the feedback network. The first output error component is calculated as RF + RG Vo _ e = VIO, or equivalently as VIO/β () RG where VIO is the input offset voltage. The input offset voltage of the AD89 is laser trimmed and guaranteed to be less than μv. The second error is calculated as V IN V TO V.µF Ω V OCM Ω 8 4Ω + AD Ω RF + RG RGRF Vo _ e = IIO = IIO( RF ) () RG RF + RG where IIO is defined as the offset between the two input bias currents. The third error voltage is calculated as.µf V TO AD7674 REFBUFIN Vo_ e = enr ( V ICM V ) () OCM.µF µf + AD8 Figure 6. Low-Z. V Buffer + ADR4.V REFERENCE Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD89. In this case, the biasing circuitry is not required. Bandwidth Versus Closed-Loop Gain The AD89 s db bandwidth decreases proportionally to increasing closed-loop gain in the same way as a traditional voltage feedback operational amplifier. For closed-loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as RG f db, VOUT, dm = ( MHz) () R + R or equivalently, β( MHz). G F where Δenr is the fractional mismatch between the two feedback resistors. The total differential offset error is the sum of these three error sources. Other Impact of Mismatches in the Feedback Networks The internal common-mode feedback network will still force the output voltages to remain balanced, even when the RF/RG feedback networks are mismatched. The mismatch will, however, cause a gain error proportional to the feedback network mismatch. Ratio-matching errors in the external resistors will degrade the ability to reject common-mode signals at the VAN and VIN input terminals, much the same as with a four-resistor difference amplifier made from a conventional op amp. Ratio-matching errors will also produce a differential output component that is equal to the VOCM input voltage times the difference between the feedback factors (βs). In most applications using % resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored. Rev. A Page of 4

22 AD89 Driving a Capacitive Load A purely capacitive load will react with the bondwire and pin inductance of the AD89, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance, see Figure 6 and Figure 6. The resistor and load capacitance will form a firstorder low-pass filter; therefore, the resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. CLOSED LOOP GAIN (db) 4 9 V O, dm =.V p-p G = (R F = R G = Ω) R L, dm = kω R S =.Ω C L = pf R S = 6.4Ω C L = pf R S = 6.4Ω C L = pf M M G Figure 6. Frequency Response for Various Capacitive Load and Series Resistance R S =.Ω C L = pf R S = Ω C L, dm = pf The Typical Performance Characteristics that illustrate transient response versus the capacitive load were generated using series resistors in each output and a differential capacitive load. Layout Considerations Standard high speed PCB layout practices should be adhered to when designing with the AD89. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. To minimize stray capacitance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. Small amounts of stray summing-node capacitance will cause peaking in the frequency response, and large amounts can cause instability. If some stray summing-node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors. Terminating a Single-Ended Input Controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD The input resistance presented by the AD89 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into account. The Thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. An exact solution to the problem requires the solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. An iterative solution is also possible and simpler, especially considering the fact that standard % resistor values are generally used. Figure 6 shows the AD89 in a unity-gain configuration driving the AD664, which is a 4-bit high speed ADC, and with the following discussion, provides a good example of how to provide a proper termination in a Ω environment. The termination resistor, RT, in parallel with the 68 Ω input resistance of the AD89 circuit (calculated using Equation 9), yields an overall input resistance of Ω that is seen by the signal source. In order to have matched feedback loops, each loop must have the same RG if they have the same RF. In the input (upper) loop, RG is equal to the Ω resistor in series with the (+) input plus the parallel combination of RT and the source resistance of Ω. In the upper loop, RG is therefore equal to 8 Ω. The closest standard % value to 8 Ω is 6 Ω and is used for RG in the lower loop. Greater accuracy could be achieved by using two resistors in series to obtain a resistance closer to 8 Ω. Things get more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source generator VS is two times the amplitude of its output signal when terminated in Ω. Thus, a V p-p terminated amplitude is produced by a 4 V p-p amplitude from VS. The Thevenin equivalent circuit of the signal source and RT must be used when calculating the closed-loop gain because in the upper loop RG is split between the Ω resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output voltage when terminated in Ω because RT must always be greater than Ω. In this case, it is 6.9 Ω and the Thevenin voltage and resistance are. V p-p and 8 Ω, respectively. Now the upper input branch can be viewed as a. V p-p source in series with 8 Ω. Since this is a unity-gain application, a V p-p differential output is required, and RF must therefore be 8 (/.) = 6 Ω. The closest standard value to this is Ω. When generating the Typical Performance Characteristics data, the measurements were calibrated to take the effects of the terminations on closed-loop gain into account. Rev. A Page of 4

23 AD89 Since this is a single-ended-to-differential application on a single supply, the input common-mode voltage swing must be checked. From Figure 6, β =., VOCM =.4 V, and VICM is. V p-p swinging about ground. Using Equation 6, VACM is calculated to be. V p-p swinging about a baseline of. V, and the minimum negative excursion is approximately V. Exposed Paddle (EP) The SOIC-8 and LFCSP packages have an exposed paddle on the underside of its body. In order to achieve the specified thermal resistance, it must have a good thermal connection to one of the PCB planes. The exposed paddle must be soldered to a pad on top of the board that is connected to an inner plane with several thermal vias. V.V.µF.µF.µF V S Ω SIGNAL SOURCE V p-p R T 6.9Ω Ω V OCM 6Ω 8 Ω + AD Ω Ω Ω AV AIN CC AD664 AIN GND C C DV CC VREF.4V.µF.µF Figure 6. AD89 Driving AD664, 4-Bit, 8 MSPS/ MSPS A/D Converter Rev. A Page of 4

24 AD89 OUTLINE DIMENSIONS 4. (.7).9 (.4).8 (.). (.97) 4.9 (.9) 4.8 (.89) 8 TOP VIEW 4 6. (.44) 6. (.6).8 (.8) BOTTOM VIEW (PINS UP).9 (.9).9 (.9). (.98). (.9) COPLANARITY. SEATING PLANE.7 (.) BSC.7 (.69). (.). (.). (.). (.98).7 (.68). (.) 4. (.).7 (.).4 (.6) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8 Figure 6. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC/EP], Narrow Body (RD-8-) Dimensions shown in millimeters and (inches) PIN INDICATOR. BSC SQ TOP VIEW.7 BSC SQ.4. BSC..4.6 MAX. PIN INDICATOR 8 EXPOSED PAD (BOTTOM VIEW) 4. REF MAX.8 MAX.6TYP. MAX. NOM. MIN.6.4. SEATING PLANE...8. REF Figure Lead Lead Frame Chip Scale Package [LFCSP], mm mm Body (CP-8-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD89ARD C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ARD-REEL C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ARD-REEL7 C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ARDZ C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ARDZ-REEL C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ARDZ-REEL7 C to + C 8-Lead Small Outline Package (SOIC) RD-8- AD89ACP-R C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB AD89ACP-REEL C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB AD89ACP-REEL7 C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB AD89ACPZ-R C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB AD89ACPZ-REEL C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB AD89ACPZ-REEL7 C to + C 8-Lead Lead Frame Chip Scale Package (LFCSP) CP-8- HEB Z = Pb-free part. 4 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D4679 /4(A) Rev. A Page 4 of 4