AGENDA. Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

Transcription

1 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING, SENSING, AND PERCEPTION Dr Dennis Buss Texas Instruments Inc

2 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

3 Semi-Conductor Scaling Modern CMOS 10 um Beginning of Submicron CMOS 1 um Deep UV Litho 37 Years of Scaling History 100 nm 10 nm 1 nm nm in nm in 2006 Every generation Presumed Limit to Scaling Feature size shrinks by 70% Transistor density doubles Wafer cost increases by 20% Chip cost comes down by 40% Generations occur regularly On average every 2.9 years over the past 35 years Recently 2 years every

4 GSM Digital Baseband Evolution Year Nanometer Wafer size Die size (mm2) Dies per wafer nm 350n m 250nm 6" nm 130nm 90nm 65nm 45nm 8" 8" 12" 12" 12" 12" ,200 18,700 26, ,50 0 8" X increase in die per wafer

5 Typical 65 nm Product: DBB chip Features: Die Size: 13.3mm2 5.9M bits SRAM 1.9M gates of logic efuse (dieid) and repair ARM7 uc LEAD3 DSP (250K gates) MegaCell (300K gates) ASIC gates (1.3M gates) Volume Production

6 Lithography 10 Above Wavelength Near Wavelength Below Wavelength Resolutio n (µm) g-line λ = 436nm i-line λ = 365nm DUV λ = 248nm λ = 193nm 0.13 i-193 λ = 133nm EUV λ = 13.5nm Year of Production 2010

7 STRUCTURED LAYOUT (45 nm) Design Data Silicon Vertical poly gates only GHOST Poly Poly not required to overlap contact Max Xstor width change within ACTIVE

8 Si Technology Roadmap Issues/Trends Design for Manufacturing Variations Analog/RF & MEMS SOC Integration Co-Development of Process, Design Techniques and Architecture CMOS processes customized to the application Relentless focus on power reduction.

9 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

10 Deep Submicron Processes Demand Enhanced Power Management MHz Phone Performance Requirement MCU Product available Technology: memory Iddq Talk Time: Pwr_Active = CV2F + Leakage - C: Decrease/node,offset by complexity - F: Increases/node - Leakage: Increases/node, temp. Standby Time: Pwr_Idle = Leakage - Leakage: Increases/node, temp Without PM With PM Without PM 1000 Iddq norm. Iddq norm Memory Iddq vs. Power Management nm 130nm 90nm 65nm Technology Node 45nm 180nm 130nm 90nm 65nm 45nm

11 Power Domain Partitioning Main Power Domains DSP Data Memory Modem Logic Others Power Mngmt Control MCU DPLL Analog IO

12 Approaches to Power Reduction VDD for IO = 1.8V VDD Core: ~1.0V in retention ret VNW VDDVNW ret VDD SRAM ARRAY VSS ret retz LD O SRAM PERI VSUB VSUB VSS SRAM (0.5V) VSS (0V) VNW VDD LOGIC VSS VSUB VNW VDD Flip Flops VSS VSUB LOGI C VNW VDD Always On VSS VSUB

13 Silicon Measurements

14 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

15 Why Single-Chip Phone? "Integration is like gravity Already happened in harddisk drives, ADSL, etc Not a single example of reversal $20 phones Large untapped market in India and China More real estate space for advanced features Better reliability Today, more than half of the total components on a board are analog RF components Longer talk time

16 PA Passive s Baseband Logic Memor y Power Management User Interfac e Audio Synt h TX Radio CODE C Display LNA Typical Cell-Phone Block Diagram Digital RX High DSM Digital SiGe BICMOS Discrete voltage Analog Passives FLASH EEPROM CMOS High-power (typically (SAW Filters, GaAs) etc.) Area and cost must be reduced integrate!

17 What about SiP Integration? Monolithic integration of DRAM would result in significant cost increase due to the need for additional mask levels. Memory modules are highly reusable so modularity makes sense. No yield impact issue due to in-package integration of memory.

18 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

19 Conventional Transceivers RF transmitters in commercial wireless applications are traditionally based on charge-pump PLL s and IQ upconversion mixers RF receivers use continuous-time mixing, filtering and amplification Design flow and circuit techniques are analog intensive Technology incompatible with modern digital processors ILow-voltage deep-submicron CMOS D A LPF LPF PA Digital Base band 0 90 Q D A LNA I Digital Base band 0 90 LPF LPF LO A D LO Q A D

20 Digital Baseband and Application Processor DRP RF Architecture Chann el Digital Logic TX data RX data 0.2, 1.25, 2.5,5, 10, 15, 20MHz BW Amplitude Regulation DCO RF DPAOut Σ TDC TX/RX 450, 800, 900, Combin 1800, 1900, 2100, er 2500, 3400MHz Transmission bands LO clock TX GMSK, QPSK, 8-PSK, 16QAM, 64QAM Modulation RX Digital Logic A/D Power Management (PM) Discret LNTA e time Curre nt sampl er RF In TDMA, FDMA, RF Built-in Self Test (RFBIST) CDMA, OFDMA, IFDMA schemes Looks like SDR!!

21 DRP/SoC Proven in Many Products LoCosto GSM/GPRS 1/2 the silicon 1/2 the power 1/2 the board area NaviLink A-GPS BlueLink Bluetooth Hollywood mdtv WiLink Wi-Fi More to come

22 Single-Chip GSM Radio 90 nm CMOS All-digital PLL All-digital TX Digitallyintensive RX w/o 2-W PA Battery manageme nt VBAT Battery Management SRAM Digital Baseband Processor XO Σ DCXO Σ Digital logic AM Front-end Module DPA DCO TX RX Digital logic A/D Power Management Discrete time LNA Current sampler RF Built-in Self Test

23 New Paradigm In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of an analog signal

24 All-Digital PLL vs. Charge-pump PLL Charge Pump Phase/ Charge-pump Frequency PLL: Detector Suffers from UP FREF reference PFD DOWN (fr) spurs Tradeoff: bandwidth against spur level FCW All-digital PLL: True phase FREF domain (fr) operation Exploits time resolution of TDC and DCO Σ Loop Filter Frequency Divider N Reference phase Phase error Loop Variable phase (fv) Tuning voltage Filter TDC VCO DCO Tune Σ CKV (fv)

25 Deep-Submicron CMOS Rules Exploit: Fast switching characteristics of MOS transistors Small device geometries and precise device matching High density of digital logic: 250 kgates/mm2 in 90nm CMOS High density of SRAM memory: 1 Mbits / mm2 in 90nm CMOS Avoid: Biasing currents for analog circuits Reliance on voltage resolution Nonstandard devices not needed for memory and digital logic

26 SoC Drives Cost Reduction 90nm 65nm 45nm DRP SoC Integration Includes: Digital baseband SRAM Power management Analog RF Processors & Software The DRP technology enables digital implementation of traditional analog RF functions in standard CMOS Most advanced process technology used to maximize integration while minimizing cost 90nm (shipping) 65nm (mature design) 45nm and beyond (preliminary)

27 Digital Radios Offer Many Benefits Why Digital? Process Capability We can now clock systems at radio frequencies Digital technology takes advantage of Entitlement Node Migration advanced logic capability (and leverages the wafer process technology investment) Digital systems scale with lithography and are easy to migrate Performance Cost Performance improves with new technology, the job keeps getting easier Digital radios offer excellent performance, low power consumption, high manufacturing yield, and low cost

28 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog/RF Functions Digital Radio Processor Integrated MEMS Conclusion

29 MEMS Integration MEMS Integration will also enable products for ubiquitous computing, sensing and perception accelerometers pressure sensors rate gyros integrated microphones resonators RF switches and tuneable capacitors optical switches and phase modulators, micro-fluidic pumps and valves displays The Digital Mirror Device (DMD) is an example of integrated MEMS

30 How the DMD Works 0

31 How the DMD Works 0

32 How the DMD Works 0

33 How the DMD Works 0

34 How the DMD Works 0

35 MEMS Integration Today HDTV Front Projection Products Large Screen Movie Theaters Tomorrow Projection displays for cell phones and PDAs 3D imaging for medical

36 Si TECHNOLOGY ROADMAP FOR UBIQUITOUS COMPUTING AGENDA Moore s Law Scaling Design for Low Power SOC Integration of Analog Functions Digital Radio Processor Integrated MEMS Conclusion

37 Technology in the Next Decade Moore s Law is predicted to stagnate toward the end of the next decade

38 Technology in the Next Decade Moore s Law is predicted to stagnate toward the end of the next decade but SOC Integration has the potential to continue IC cost reduction and to perpetuate growth of products for ubiquitous computing, perception & sensing.

39 System Functionality Systems on Si System-on-Si Integration s e r o o M w a L g in l a c S 2015