Cell Phone Integration: SiP, SoC, and PoP

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1 System-in-Package Design and Test Cell Phone Integration: SiP, SoC, and PoP Peter Rickert and William Krenik Texas Instruments Editor s note: Engineers must make many cost-effective decisions during a product s design cycle. One challenge is deciding on the best packaging for their products. This article presents trade-offs among system-in-package, systemon-chip, and package-on-package integration for mobile phone applications. Bruce C. Kim, University of Alabama A FEW YEARS AGO, the cellular handset market was dominated by single-, dual-, and triple-band, single-mode phones. These phones supported only a few cellular bands and used the same modulation, multiple-access scheme, and protocol in all supported bands. In contrast, today s cellular handset designs are decidedly more complex: They have multiband, multimode cellular support as well as Bluetooth personal area networking, GPS-based positioning technology, WLAN for high-speed local-area data access, and mobile digital TV for real-time television functionality. In addition, user applications such as games, graphics, audio, and video are becoming commonplace in handsets. The communication-processing complexity of 3G cell phones is on the order of 50 times that of 2G voice-only phones. In addition, the applicationprocessing complexity of data handsets can be well over an order of magnitude higher than voice-only devices. Dramatic increases in communication and application processing, the number of radio interfaces, and the amount of memory integrated into advanced handsets are overwhelming compared to simple, voice-only designs. At the same time, handset users expect very small, sleek, low-cost handsets that feature large color displays and standby and talk times similar to those of voiceonly handsets. In response, handset component manufacturers are moving aggressively to include advanced power-management techniques, specially tailoring communication- and application-processing architectures to the required tasks and dramatically reducing component cost. The three main approaches to reducing component cost are SoC integration, system-in-package (SiP) integration (the stacked-die solution), and package-onpackage (PoP) integration (the stackedpackage solution). System integration requires a complete system-level tradeoff analysis that involves the entire bill of materials and the architectures used for the communication system being designed. Determining the best set of trade-offs to attain the most cost-effective solution requires close collaboration from diverse engineering disciplines, including process integration engineers, circuit engineers, and system engineers. Here, we investigate the trade-offs among SoC, SiP, and PoP, specifically for integrating memories, analog electronics, and RF electronics in the handset. Memory integration SoC products require a significant amount of RAM to operate most efficiently. Although incorporating large amounts of RAM onboard with the CPU (typically a DSP core or a microcontroller core) is often desirable, the bill-of-materials cost constraints usually determine the solution chosen. A key requirement is to ensure enough memory on chip to keep processor cores running with minimal or no wait states. This means on-chip level-one and level-two cache memory arrays are necessary to keep the processor core pipelines loaded and to prevent excessive fetches off chip, which would slow down the cores effective processing throughput. Design engineers typically implement such caches in SRAM. The density of SRAM follows a predictable Moore s law curve, doubling at each successive process generation. Onboard SRAMs as large as 2 to 8 Mbits provide a costeffective solution for many SoC designs today. However, other types of embedded memory have two to three times the density of the industry s best /06/$ IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers

2 Well bias generator V DD V NWELL V BP V CC SLPZVDD V DD' Periphery logic V in V out SRAM array V DDF V SS SLPZVSS V SS' efuse latches efuse interface Standby V BN Switches open when active low V SS Figure 1. Techniques for reducing power dissipation in SRAM during inactive data retention mode. Figure 2. Power management techniques for reducing SRAM leakage currents. embedded six-transistor SRAM. Also, the static power dissipated by SRAM leakage currents increases at each process node because of increases in transistor off-state or subthreshold leakage currents. Several well-known power management techniques, which can give ordersof-magnitude leakage reduction during standby or sleep modes in the application, can significantly reduce this impact. A technique typically used for this purpose is back-biasing the memory arrays, which increases the SRAM transistors threshold voltage, thus decreasing leakage. Another technique is to reduce the power supply voltage to the memory during sleep mode to reduce leakage. Figure 1 illustrates these techniques. Figure 2 shows a more-sophisticated power management technique developed for implementation at the 65-nm technology node. This technique uses diodes to create a virtual back-bias on both the PMOS and NMOS transistors to reduce their leakage. 1 The magnitude of memory required in cell phone SoC applications is considerable. Recent analysis by companies that tear down cell phones from the marketplace shows that a typical GSM (Global System for Mobile Communications) phone has 20 Mbytes of memory, and a typical UMTS (Universal Mobile Telecommunications System) or W-CDMA (Wideband Code Division Multiple Access) phone has 60 Mbytes of memory. This memory is typically a mix of SDRAM and flash. Providing sizes such as these in an embedded solution is inconceivable because of the area required and the resulting negative impact on the bill-of-materials cost constraint. The key to deciding whether these memories should be embedded or off chip is whether the embedded solution delivers more value than integrating the external memory on chip. This means that, while including an embedded solution, the design should leverage integration from an architectural perspective. A good example is an application such as graphics video processing that needs very high memory bandwidth. For this requirement, using a very wide memory bus to deliver the added bandwidth is advantageous. Bus width in these applications can be 256 or 512 bits. Such a bus width is not practical with external memory, and thus a wide memory bus leverages the embedded memory solution and delivers far more value than just a cost reduction. One cost-effective solution to the SoC embeddedmemory issue is a SiP. Although a SiP is not actually what we would typically call an embedded memory, it meets the same low-cost and small-footprint needs. Many SiP implementations are possible, but the most successful for memory is the stacked-die approach. In this implementation, one or more commodity memory dies are stacked on top of a SoC logic device, interconnected with low-cost wire bond assembly technology, and all is encapsulated in a low-cost chip-size ball grid array (BGA) package. Figure 3a shows a photomicrograph of a wire-bonded stacked-die SiP, and Figure 3b shows a cross section. The stacked-die approach uses commodity memories, thus leveraging the lowest-cost-per-bit memory in the industry. Because it doesn t add any process complexity May June

3 System-in-Package Design and Test (a) (b) 13 mm 13 mm 1.45 mm Figure 3. Photomicrograph of stacked-die SiP, with memory die over logic die, in low-cost wirebonded ball grid array (BGA) substrate (a). Schematic cross section of a SiP implementation in a wire-bonded, BGA-style package (b). to the high-performance CMOS SoC device, this approach truly offers the best of both worlds, especially in contrast to embedded DRAM or flash solutions. It doesn t require any custom chips, so it can enable a very fast time to market. Because it leverages the package s vertical dimension, it provides the PCB footprint benefit required by battery-operated consumer products. Clearly, this solution demonstrates that simplicity is often the best solution. SiP solutions are in volume production today for cellular handset electronics. As packaging engineers have progressed in developing SiPs, they have also looked at alternatives that might be an improvement on SiPs. This work has initiated the development of a new package variant, PoP, or stacked packages. Whereas a SiP is a vertical stack of multiple dies in a single encapsulation, a PoP is a vertical stack of independently encapsulated packages. Table 1 compares SiP and PoP trade-offs. In the never-ending pursuit of lower cost, PoP looks like a significant advantage over SiP because it essentially eliminates known-good-die issues and associated yield and procurement issues. PoP also enables a path using standard commodity memory footprints, rather than the custom designs typically required for SiP implementation. This is especially true because SiP implementation always requires a custom version of DFT implementation to permit testing after SiP encapsulation. In contrast, PoP testing can be independent of the final SoC solution, so a PoP can use standard commodity memory DFT modes. PoP also eliminates the procurement-related business issues of the SiP package, which is implemented by a logic chip supplier who must procure the memory chips from another IC supplier. Because low cost is the primary objective, any additional cost in the SiP implementation can be a showstopper. Business issues, not technical issues, can prevent SiP implementations from becoming a reality. PoP eliminates these problems because each individ- Table 1. Comparison of SiP and PoP trade-offs. Property SiP PoP Cost Component supplier chooses memory supplier System s original equipment manufacturer chooses memory supplier Complexity limits multiple sourcing Multiple sources are viable Multiple dies compound test yield loss Separate packages eliminate yield loss Memory options SDRAM and DDR; flash is difficult; Any memory no wafer-level known-good dies Die and package Often requires custom memory Can use a standard commodity memory design complexity Package size Smaller Larger Time to market Unique design cycle Developing PoP standards will allow faster implementation Assembly technology Wire bond with minor development New substrate capability required; basic wire-bond assembly technology is available 190 IEEE Design & Test of Computers

4 ual IC logic and memory supplier provides packaged devices to the original equipment manufacturer (OEM) or subcontractor who populates the PCB. This is a cleaner arrangement from a business perspective because it is identical to the standard procurement of other IC components. The single impediment to PoP s proliferating and taking over the SiP domain is the lack of pinout and footprint standards similar to the industry-standard pinouts and package footprints established for most commodity memory products. Such standards would enable PoP manufacturers to leverage supply from commodity suppliers. However, with the significant number of advantages of PoPs over SiPs, we expect quick and synergistic cooperation between logic suppliers and memory suppliers to realize this new package style. Indeed, with PoP s lower cost, many OEM and system manufacturers will demand it. An example of a PoP product is TI s OMAP 2420 multimedia processor, implemented in TI s low-power 90-nm CMOS technology. This chip has external memory interfaces to NOR flash, NAND flash, SRAM, and SDRAM. It has a 447-ball BGA package for its bottom interface, and a 152-ball BGA top interface for commodity memory devices. Figure 4 shows a cross section of this package. 1.6 mm max. Analog and power management integration Most cellular handsets contain an analog baseband chip that contains analog and power management functions. Here, we address the question of how best to achieve cost reduction in these functions. Today, analog and power management functions are optimally implemented in analog process technologies very different from the deep-submicron CMOS used for digital baseband (DBB) chips. If the analog and power management functions can be implemented in deep-submicron digital CMOS without adding process cost to the digital process, SoC integration of analog and power management functions is the lowest-cost approach. If additional process steps (reticle steps) are required, they substantially reduce the benefit of analog and power management integration because the additional process complexity affects the entire IC, not only the area associated with analog functions. The biggest challenge in implementing high-speed, 1.0 mm 0.6 mm 14 mm 14 mm Figure 4. OMAP Schematic cross-section of a PoP in a wire-bonded BGA package, with the logic package on bottom and memory package on top. It s possible to stack multiple memory dies inside. high-precision analog functions in digital CMOS technology is its low power supply voltage. 2 Other limitations include poor matching of small components, high 1/f noise, and the absence of on-chip passive components (resistors, capacitors, varactor diodes, and so forth) with adequate analog characteristics. These limitations usually make copying existing analog circuit functions in digital CMOS unfeasible. Instead, the designer must reoptimize the entire system: develop a specification for the analog function that takes advantage of digital CMOS, and new architectures that take advantage of low-voltage, low-cost digital logic. In most cases, these architectures are well-known, but the tradeoffs at low voltage are different. For example, consider the case of integrated ADCs and DACs: At low voltage, the power dissipated by flash converters is greatly reduced, making flash architectures advantageous. 3 Because flash converters have low power, multibit sigma-delta converter architectures have advantages over single-bit architectures. 4 Very fast logic allows offset compensation in a fraction of a sample period and enables small, lowpower comparators. Oversampling DACs and ADCs become increasingly feasible at low voltage, thus reducing kt/c noise and easing analog filter requirements. Digital, self-calibrating, and dynamic element matching have increasing advantages at small feature size and low voltage. Isolating sensitive analog nodes from digital clock noise is an important design consideration in SoC integration. Clock noise from digital logic couples to the substrate in various ways: IR drops in the digital V ss lines that contact the substrate to ground, May June

5 System-in-Package Design and Test channel hot carriers generated in the transistors, and capacitive coupling. Once clock noise is in the substrate, current flow in the substrate conducts it to analog nodes. This noise affects analog transistors in two ways: capacitive coupling to NMOS Source/Drain and modulation of NMOS V TH through body effect. If the substrate resistivity is R 1, and the resistance from the analog substrate contact is R 2, the degree of isolation is R 1 /R 2. Techniques for reducing clock noise feedthrough to sensitive analog nodes include using differential circuits, which see clock noise as common mode; placing sensitive nodes far from digital logic; using high-resistivity substrate material; 5,6 using n-well-to-ring analog circuitry; and placing low-impedance analog substrate contacts close to sensitive analog transistors. None of these techniques adds to process cost. However, if clock noise continues to be a problem after applying these techniques, a buried n+ can be added at the cost of an additional reticle. Power management is becoming increasingly distributed, especially in low-power applications, because of the need to reduce standby power by putting unused logic and memory in a standby or sleep mode. Switches that activate or deactivate logic blocks can provide much of this power management functionality. In addition, local, on-chip voltage regulation is needed, and this requires on-chip low-dropout (LDO) regulators. Activating a switch or realizing an LDO regulator at a voltage near V DD often requires circuits to operate in excess of V DD. Designers can achieve this by using drain-extended (DE) CMOS, 7 which can sustain voltage on the drain in excess of a normal MOSFET s breakdown voltage from drain to source (BV DSS ). Designers can also use DE CMOS to implement highvoltage battery charger circuitry in battery-operated products. A DE transistor is so constructed that the drain is not self-aligned to the gate. A large voltage can be applied to the drain because part of the drain voltage drops across a depletion layer in the moderate-to-lightly-doped drain, and the gate s electric field remains below breakdown. The source is self-aligned to the gate, and the gate-tosource voltage remains limited by the gate-to-source breakdown. In a DE transistor, V DS can be substantially higher than the transistor s V DD, which is limited by gate breakdown and reliability. 8 DE transistors can also be used for switching-mode power supplies and to interface to the battery charger if the charger is adequately voltage regulated. The past several years have seen tremendous progress in implementing analog and power management functions in deep-submicron CMOS. Today, virtually all analog functions required in a cellular handset can be implemented cost-effectively in deep-submicron digital CMOS. The cost reduction path for analog and power management circuitry is SoC integration with the DBB chip. Radio integration The radio in a modern handset faces many severe performance requirements. It must receive signals of only a few microvolts in amplitude despite strong interferers. The radio design must produce high output power levels (roughly 30 dbm) to drive the antenna, and it must account for isolation between various radios in the handset. Additionally, radio designs require accurate filtering at high frequencies and good matching between circuits in the signal path. These requirements make radio integration a considerable challenge and make the choice between SiP and SoC for the radio function a complex decision. Figure 5 shows a high-level block diagram of a modern GSM radio s typical functions. The radio transceiver function contains the small-signal radio electronics needed for up-and-down conversion of the information signal to the transmission band. The power amplifier module (PAM) amplifies the transceiver output to produce an output signal with adequate power for reliable transmission. The front-end module (FEM) normally includes the RF switch function (for separating the timemultiplexed transmit and receive signals) and the RF preselect filters, which are normally surface acoustic wave (SAW) devices (other partitionings of module functions are possible). A cellular standard such as CDMA, which implements full-duplex operation in the air interface, would have a similar block diagram, except that a duplexer would replace the switch function to allow simultaneous receive and transmit. The two ellipses in Figure 5 represent possible partitioning options for the radio electronics. A SoC would integrate the radio transceiver with the baseband-processing IC. Alternatively, a SiP would integrate the transceiver with the PAM and FEM to create a single analog radio module. The use of module technology in the 192 IEEE Design & Test of Computers

6 radio function is commonplace today, and production handsets have contained PAMs and FEMs for many years. Because interfacing radio signals between analog functions normally requires matching SoC networks, many passive components are associated with radio design. Therefore, pulling as many passive elements as possible into the PAM and the FEM is advantageous. Normally, the PAM and the FEM remain separate, to prevent the heat generated in the PAM from aggravating thermal-stability problems in the SAW filters. However, there are designs that integrate the entire radio function in a package (the SiP ellipse in Figure 5). Consequently, talking about SiP versus SoC for the radio function is somewhat misleading because the radio implementation will use packaged modules in either case. The discussion comes down to which is better integrating the radio transceiver through packaging technology with the FEM and/or PAM, or integrating the transceiver monolithically with the baseband-processing IC? Since SiP allows the use of a conventional analog RF transceiver, it requires no new transceiver architecture or special IC technology. The radio transceiver capability is well established, and apart from layout considerations associated with integration in a module (such as bond pad placement and IC aspect ratios), little stands in the way of SiP integration. However, at the system level, SiP integration has several significant drawbacks. Most notably, analog transceiver technology usually suffers significant parametric yield loss at IC final test. Performing fully parametric RF testing at wafer level (wafer probe) is very difficult, so there will undoubtedly be some parametric yield loss at SiP module test. Parametric yield loss in the transceiver (or any other component) means that the entire SiP module must be discarded. Thus, SiP integration faces a serious challenge in meeting cost targets. SoC integration of the radio transceiver is usually implemented monolithically in deep-submicron CMOS. Alternatively, a BiCMOS (SiGe) wafer process might allow a conventional radio architecture implementation. However, the additional reticles required for a SiGe wafer would drive up system logic and memory costs, and the lack of SiGe processes in current lithography would increase logic area. Additionally, a conventional Baseband processing IC Radio transceiver IC Figure 5. Radio partitioning and integration. Power amplifier module radio would not fully realize the benefits associated with tightly coupling system logic with the radio function. Hence, monolithic integration in BiCMOS is not an attractive option. Consequently, CMOS is the obvious choice for SoC integration of the radio transceiver. Fortunately, deepsubmicron CMOS transistors offer very good RF performance and easily meet the needs of integrated transceiver designs (low noise and high transition frequencies are possible). 9,10 However, conventional RF transceiver designs use analog components extensively and require high-performance passive elements. Given the tremendous logic density and high clock speeds offered by deep-submicron logic processes, it is only natural to exploit this capability to reduce the need for high-performance passive elements. Fortunately, radio architectures that achieve this are available. One such architecture eliminates the need for high-performance passive elements by using sampled-data techniques. 11,12 The sampling operation naturally gives rise to frequency translation, so the circuit easily achieves signal down-conversion. Once sampling capacitors have captured the input waveform, combining charge samples is also easy. Multiple samples of a waveform taken on the same capacitor allow implementation of a simple moving-average filter. More-complex FIR and IIR filters can also be easily Front-end module SiP May June

7 System-in-Package Design and Test Figure 6. TI s single-chip SoC cell phone die with digital radio processor on right-hand side. realized. Various techniques can achieve A/D conversion, and digital signal processing can further process the signal. Although generating a new radio technology to allow deep-submicron CMOS implementation imposes a significant burden, it can result in important benefits. Foremost is that such a radio will benefit from advancements in CMOS wafer-processing capability. As processswitching speed increases, higher sampling rates become possible. Oversampling the input signal reduces noisealiasing problems and relaxes the input networks design. More-complex filtering can be added, and A/D conversion can occur closer to the antenna, moving more of the signal-processing burden to the digital domain to realize the full benefit of logic scaling. Advancing process lithography will reduce sampling switch parasitics and improve device matching. Capacitors can easily use available metallization, and inductors can benefit from copper interconnections. Many additional benefits are obvious. SoC integration improves system yield because more system functionality is implemented as logic (in contrast to analog RF, which suffers parametric yield loss). The system baseband-processing function makes self-test possible. Moving the radio function to an aggressively scaled technology substantially reduces system board area and total IC silicon area. Extensively applied self-calibration techniques can further enhance yield and reduce the need for external elements. Since many radio functions are digital, system debugging engineers will gain enhanced visibility into radio performance by simply reading out register contents, rather than probing with a scope or analyzer. Similarly, self-calibration and self-test at the system level will enhance phone manufacturability and further reduce costs. Figure 6 shows a photo of a production SoC cell phone die. All analog, RF, logic, and power management functions are integrated on a single IC in 90-nm CMOS in a component called the digital radio processor. The device is fully certified to meet all GSM system requirements and offers excellent performance, attractive power levels, and low cost. It is not surprising that a system as complex as a modern cellular handset is best implemented through the use of multiple technologies. For system memory, SoC integration is simply not practical for very large memories if even a few additional reticle steps must be added to the wafer process to implement them. For such cases, SiP integration provides a low-cost, small-layout-area solution. However, PoP looks like the future pathway for memory integration from a package perspective. For smaller memories that require no additional processing steps, SoC integration is attractive because wide interface buses can be applied with no cost penalty. For analog integration, clever use of the benefits of high-speed CMOS make SoC integration attractive for many functions. For RF integration, a mix of SiP and SoC is optimal. We conclude that CMOS processes can meet most requirements of cellular handset integration. 13,14 IN THE NOT-TOO-DISTANT FUTURE, analog RF will virtually disappear from the wireless landscape as OEMs move to increasingly sophisticated handsets, incorporating multiple radios to deliver widely varied applications. CMOS technology will dominate the RF domain as semiconductor makers move to smaller process nodes. For wireless handsets with the multiple radios needed to deliver the functionality that consumers expect, digital RF clearly is the path to the future. Software-defined radio will be important in using radio components efficiently and in reducing the total number of radios needed. But there can be no question that board space considerations, if nothing else, will mandate the move to more compact RF. Power concerns and cost will add impetus to this shift away from analog RF processing. Acknowledgments We gratefully acknowledge support, encouragement, suggestions, and technical advice from G. Delfassy, H. Stork, J. Bellay, D. Leipold, J.Y. Yang, K. Maggio, K. Lyne, B. Staszewski, R. Tolbert, Y. Suzuki, J. Akiyama, C. Azuma, M. Amagai, and D. Edwards. 194 IEEE Design & Test of Computers

8 References 1. P. Royannez et al., 90nm Low Leakage SoC Design Techniques for Wireless Applications, Proc. Int l Solid- State Circuits Conf. (ISSCC 05), vol. 1, IEEE Press, 2005, p D.D. Buss, Device Issues in the Integration of Analog/RF Functions in Deep Submicron Digital CMOS, Proc. Int l Electron Devices Meeting (IEDM 99), IEEE Press, 1999, p J. Lin and B. Haroun, An Embedded 0.8V/480μW 6B/22MHz Flash ADC in 0.13 μm Digital CMOS Process Using Nonlinear Double Interpolation Technique, Proc. Int l Solid-State Circuits Conf. (ISSCC 02), vol. 1, IEEE Press, 2002, pp G. Gomez and B. Haroun, A 1.5V, 2.4/2.9μW, 79/50dB DR ΣΔ A/D for GSM/W-CDMA in 0.13 μm Digital Process, Proc. Int l Solid-State Circuits Conf. (ISSCC 02), vol. 1, IEEE Press, 2002, pp J.-Y. Yang et al., 0.1 μm RFCMOS on High Resistivity Substrate for System on Chip (SoC) Application, Proc. Int l Electron Devices Meeting (IEDM 02), IEEE Press, 2002, pp K. Benaissa et al., RFCMOS on High Resistivity Substrates for System on Chip (SoC) Applications, IEEE Trans. Electron Devices, vol. 50, no. 3, Mar. 2003, pp J. Mitros et al., High-Voltage Drain Extended MOS Transistors for 0.18 μm Logic CMOS Process, IEEE Trans. Electron Devices, vol. 48, no. 8, Aug. 2001, pp A. Chatterjee et al., Analog Integration in a 0.35 μm Cu Metal Pitch, 0.1 μm Gate Length, Low-Power Digital CMOS Technology, Proc. Int l Electron Devices Meeting (IEDM 01), IEEE Press, 2001, p H. Iwai, CMOS Technology for RF Application, Proc. Int l Conf. Microelectronics (MIEL 00), IEEE Press, vol. 1, 2000, pp L.F. Tiemeijer et al., A Record High 150 GHz fmax Realized at 0.18 μm Gate Length in an Industrial RF-CMOS Technology, Proc. Int l Electron Devices Meeting (IEDM 01), IEEE Press, 2001, pp K. Muhammad et al., A Discrete-Time Bluetooth Receiver in a 0.13 μm Digital CMOS Process, Proc. Int l Solid- State Circuits Conf. (ISSCC 04), IEEE Press, 2004, sec. 15.1, pp , B. Staszewski et al., All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13 μm CMOS, Proc. Int l Solid-State Circuits Conf. (ISSCC 04), IEEE Press, 2004, sec. 15.3, pp , D. Buss, Technology in the Internet Age, Proc. Int l Solid-State Circuits Conf. (ISSCC 02), IEEE Press, 2002, pp D. Buss et al., SoC CMOS Technology for Personal Internet Products, IEEE Trans. Electron Devices, vol. 50, no. 3, Mar. 2003, pp Peter Rickert is a Texas Instruments Fellow, responsible for developing platform technology for the Application Specific Products and Wireless Terminal Business organizations at TI. His technical interests include the definition, development, and deployment of TI s newest process technologies, including the 90-nm, 65-nm, and 45-nm platforms. Rickert has a BS in electrical engineering from Clarkson University. He is a registered professional engineer in the state of Texas and a senior member of the IEEE. William Krenik is a manager at Texas Instruments, responsible for developing advanced wireless technology. Krenik has a BEE from the University of Minnesota, an MSEE from Southern Methodist University, and a PhD in electrical engineering from the University of Texas at Dallas. He is a registered professional engineer in Texas and a Fellow of the IEEE. Direct questions and comments about this article to Peter Rickert, Texas Instruments, TI Blvd., MS 8661, Dallas, TX 75243; p-rickert@ti.com. Members save 25% on all conferences sponsored by the IEEE Computer Society. Not a member? Join online today! May June