A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

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1 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. ontent may change prior to final publication. itation information: DOI.9/TSII , IEEE A.95-mW 6-b 7-MS/s Single-hannel Loop-Unrolled SAR AD in 4-nm MOS Long hen, Student Member, IEEE, Kareem Ragab, Member, IEEE, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Student Member, IEEE, and Nan Sun, Member, IEEE Abstract This brief presents a low-power and high-speed single-channel SAR AD. It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage V cm. To remove the nonlinearity due to comparators offset mismatch, a simple and effective V cmadaptive offset calibration technique is proposed. The prototype AD in 4-nm MOS achieves 5dB and 48dB at 7MS/s sampling rate. It consumes.95mw, leading to a Walden FOM of fj/conv-step and a Schreier FOM of 5.4dB. Index Terms Analog-to-digital converter, successive approximation register, high speed, offset calibration. I. INTRODUTION High-speed low-resolution analog-to-digital converters (ADs) are required by many demanding applications, such as high speed serial link transceivers and communication systems. ompared with pipelined and Σ ADs, SAR ADs are more scaling friendly due to their mostly digital architecture and power efficient especially at low sampling rates [] []. In order to increase the speed of SAR ADs, several techniques have been developed [4] []. The first asynchronous SAR AD was proposed in [4] to shorten the time duration of each comparison cycle. The SAR AD speed can also be improved by using multi-bit-percycle architectures to reduce the number of comparisons, however at the cost of increased hardware complexity [6], [7]. Other effective high-speed techniques include using alternate comparators to save the comparator reset time [8] or pipelining two-stage SAR ADs [9]. Recently, several works arrange multiple comparators to further increase the speed [] []. A binary-search AD was proposed in [], which describes a transitional structure between flash and SAR ADs. However, the hardware cost is high in [] as this technique requires additional switching networks and N comparators for an N-bit design. The loop-unrolled architecture of [], [] employs a dedicated comparator for each comparison cycle. The comparison result is stored directly at the comparator output. As a result, the SAR logic is greatly simplified, leading to reduced power and The authors are with University of Texas at Austin, TX 787, USA. ( jackiechan.cl@utexas.edu, nansun@mail.utexas.edu). This work was supported in part by NSF grants 549, 59767, and 57. delay. Although more comparators are used compared to the conventional SAR architecture, the total comparator power does not increase since each of them is fired only once during the whole conversion. Nevertheless, the comparator common-mode voltage V cm varies significantly and eventually goes to V DD in [], [], resulting in large comparator offsets and reduced linearity. Both work [] and [] require complicated calibrations for comparators offset mismatches, which increase the power consumption and design complexity. This work proposes a novel loop-unrolled SAR AD with two new key techniques to improve the linearity and the power efficiency. First, in order to address the large V cm variation issue, a bidirectional single-side switching technique is employed. It reduces the comparator offset by appropriately controlling V cm. The comparator decision time is also optimized. In addition, it allows a reduced number of DA unit capacitors, which reduces the DA area and the routing parasitics. Second, to further improve the linearity, a novel V cm -adaptive offset calibration technique is proposed to calibrate the comparators offset mismatch. The proposed calibration technique has very low hardware complexity. It can calibrate the comparator offset at its operating V cm following the proposed switching procedure. A prototype AD is implemented in 4nm MOS. It achieves 4.8dB and 47.8dB at a sampling rate of 7MS/s, while consuming only.95mw power from a.v supply. The brief paper is organized as follows. Sec. II describes the proposed SAR AD architecture. Sec. III presents the circuit implementation. Sec. IV shows the measured results. The conclusion is drawn in Sec. V. II. PROPOSED SAR AD ARHITETURE The proposed 6-bit SAR AD architecture is shown in Fig. (a). It consists of a clock generator, a sampling network, capacitive DAs, 6 comparators, and a calibration unit. The clock generator generates the required timing phases. The sampling switches S and S are bootstrapped to ensure high sampling linearity at high input frequencies. The DAs are implemented using binary weighted capacitors. Small dynamic comparators with offset calibration are used to minimize power consumption. Dynamic OR gates with reset and controlled delay are used to generate the asynchronous clocks. The comparator offset mismatch is foreground calibrated by the calibration unit. The LSB comparator outputs are combined by a NOR gate to generate a ready signal, which indicates the end of the whole AD conversion (c) 6 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. ontent may change prior to final publication. itation information: DOI.9/TSII , IEEE Fig.. (a) Architecture and (b) timing diagram of the proposed SAR AD. (b) The timing diagram is shown in Fig. (b). When s is low, the input voltages are top-plate sampled on the DAs through S and S. All comparators outputs are reset to low through dynamic OR gates controlled by se. The ready signal is reset to high. When the sampling phase ends, both se and s go to high. The MSB comparator is triggered by [5] which is two gates delay of se. Depending on the sampled input voltages, the MSB comparator makes its decision dp[5] and dn[5], which directly control the capacitive DAs to perform the proposed switching technique without the need for any shift register based SAR logic. The dynamic OR gate delay is controlled to provide adequate time for DA settling. It generates [4] to trigger the second MSB comparator. This procedure propagates in a domino fashion until the LSB comparison finishes. The ready signal goes to low. The next sampling phases starts after the comparator outputs are latched by the falling edge of se. ompared to the conventional SAR AD, the SAR logic is greatly simplified in this loop-unrolled architecture. There is no need for any shift register based sequencer or DFF based data storage because all comparator results are directly stored at the comparator outputs. The asynchronous clock is generated easily by ORing the comparators outputs. The reduced logic complexity reduces the circuit power, minimizes the chip area, and increases the speed. In the proposed architecture, the conversion time is reduced in three ways compared to the conventional asynchronous SAR AD [4]. First, no DFF or latch delay is needed to store the comparator output. Second, comparators are reset simultaneously, and thus, no comparator reset time is needed for every comparison cycle. The comparator reset time can be a speed bottleneck especially in most advanced technology node where both logic delay and DA settling time are small [8]. Third, the proposed design allows independent optimization for each comparison cycle. In other words, each OR gate delay can be adjusted based on the corresponding DA settling time. The comparator power can also be optimized using the technique in []. Overall, the optimized critical path for each comparison cycle in the proposed design can be represented as: T = t comp,decision + max{t DA, t OR } () This design optimizes t comp,decision by optimizing comparator input common-mode voltage with a bidirectional single-side switching technique. t DA and t OR are optimized by using small unit capacitor and specially designed dynamic OR gate, respectively, as shown in Sec. III. Based on SPIE simulation, t DA is greater than t OR for the first MSB bits where the DA capacitors are large. t OR dominates over t DA for the last 4 LSB bits. A. omparator III. IRUIT IMPLEMENTATIONS Fig. shows the dynamic comparator with offset calibration. Two variable MOS capacitors are added at the drain of input transistors M and M for calibration purpose. omparator offset and decision time are two key parameters in this design. Unlike the conventional SAR AD with one single comparator, the loop-unrolled architecture employs 6 comparators. All comparators have offsets and their offset mismatches degrade the AD linearity. omparator decision time is in the critical timing path as shown in (). Thus, it is desirable to design comparator with small offset and fast decision time. One important factor that influences both offset and decision time is the comparator input common-mode voltage V cm [4]. A small V cm is preferred to reduce the offset. The reason is that the pre-amplification gain is larger at small V cm, which suppresses the offset contribution from the latch. A large V cm helps reduce the pre-amplification time but the time duration of the latch regeneration phase is longer due to the reduction in the pre-amplification gain [4]. There exists an optimized V cm for decision time. The simulated σ offset and decision time are shown in Fig.. Here the decision time is defined as the time it takes for the comparator output differential voltage to reach.7v DD given mv differential input. It suggests the optimal value of V cm is around.8v, where the decision time is minimized and the offset is also small. B. Modified bidirectional single-side switching technique A modified bidirectional single-side (BSS) switching technique based on [5], [6] is employed in the design. The BSS technique can reduce the number of unit capacitors by 4 times compared to conventional switching technique and times compared to monotonic switching technique [], []. The binary capacitors used in the DA are [8 U, 4 U, U, U, U ] for 6-bit implementation, with a unit capacitor U of.9ff. Thanks to the small unit capacitor, the DA settling time t DA is short and it is easy to guarantee (c) 6 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

3 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. ontent may change prior to final publication. itation information: DOI.9/TSII , IEEE M7 M5 M9 V in+ M M V indn dp M M6 M8 M4 M mv to mv and decision time can be reduced by % in the proposed switching technique. Note that V cm decreases slightly when the comparators are fired due to the comparator kick-back noise. The kick-back noise is a common-mode noise to the first order, which does not degrade the linearity for this 6-bit AD. calp M M M calm..8 Vin+ Vin- Vcm Vdm s Fig.. Dynamic comparator with varactor loading. offset [mv] 4 offset Decision time Vcm [V] Fig.. Simulated comparator offset and decision time at different V cm. the settling error to be within / LSB. No redundancy is provided to avoid additional comparison cycles. The reduced number of unit capacitors reduces the layout complexity since fewer interconnections are needed. The measured result shows the capacitors are matched well without calibration for 6-bit accuracy with a similar layout strategy in [5]. The proposed BSS switching scheme is shown in Fig. 4. DA is connected to [,,,, /] when sampling the inputs, where, and / indicate ground, V DD and V DD /, respectively. The two references V DD and V DD / are provided off-chip for simplicity, although they can be generated on-chip at low power cost [8]. Instead of switching DA capacitors from ground to V DD monotonically, the proposed technique switches the first MSB capacitors [8 U, 4 U, U ] from ground to V DD, and then, switches the left side U capacitors from V DD to ground. The right side U is switched from V DD / to ground similar to [7]. / V inp 8 4 V inm dn[5] dn[4] dn[] dp[] dp[] Fig. 4. BSS switching scheme. The simulated V cm variation is shown in Fig. 5. In the proposed switching scheme, V cm stays close to.8v after the first comparison cycle, where the optimized decision time is achieved and comparator offset is kept small. ompared with monotonic switching scheme in [], [], where V cm can converge to V DD, the σ offset can be reduced from 8 Decision time [ps] Voltages [V].4 [5] [4] [] Time [ns] Fig. 5. Simulated time-domain waveforms for comparator inputs Vin+/Vin-, its common mode voltage V cm and its differential mode voltage V dm. []. V cm -adaptive offset calibration In the prototype AD, the full-scale differential input swing is.4v and LSB size is about mv. The optimized comparator σ offset is mv, which is comparable to the LSB size. To avoid linearity degradation due to offset mismatch, a V cm -adaptive offset calibration technique is proposed. The calibration technique works as follows. When the AD is in the calibration mode, the calibration control switch S is on and a zero differential input voltage is sampled through S and S (see Fig. ). A low-frequency external clock ext is provided. Each OR gate s delay is set large enough such that before each comparator is triggered, its differential inputs settle well and stay close to zero. If there is no offset, each comparator s output jumps between and due to thermal noise. omparator thermal noise in the design is about 4µV, which is much smaller than the offset. With a large offset in presence, the comparator s output keeps staying at either or. The offset can be calibrated by tuning the MOSFET based varactors shown in Fig., whose values are controlled by its gate voltage calp/calm. The calibration range is designed to be mv which is times the simulated σ offset. By observing the comparator s output, we can tell whether the comparator offset has been calibrated or not. The calibration is finished when the comparator output is evenly distributed between and. 4 AD outputs are captured by a logic analyzer during the calibration. The comparator offset is removed when the probability that its output code equals to is around 5%. Note that the probability does not need to be exactly 5% since the calibration accuracy is relaxed for a 6-b design. The measured probability of comparator outputs being versus its calibration voltage calm for the MSB comparator is plotted in Fig. 6. The proposed calibration is simple as it only requires one additional switch S. It does not require special DA patterns to generate the operating [] [] (c) 6 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

4 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. ontent may change prior to final publication. itation information: DOI.9/TSII , IEEE 4 V cm in [] or special input voltages that cause metastability at different comparators in []. Furthermore, since the same DA switching procedure happens during calibration, each comparator offset is calibrated at the same V cm as that of the normal AD operation. This is necessary in BSS or monotonic switching technique since V cm varies in each comparison cycle and the comparator offset depends strongly on V cm [4], [5]. Probability of output = calm voltage [V] Fig. 6. Probability of MSB comparator output being versus its calm with calp fixed at.v. D. Switches and logic A clock generator similar to [4] is used. The input sampling switches S and S are bootstrapped with the circuit shown in Fig. 7(a) [9]. A thick-oxide device provided in the process is used to tolerate a potential voltage higher than.v. OR gate needs to have a reset function together with controlled delay with the aim to provide enough time for DA settling. Since the unit capacitor employed in this design is quite small (.9fF), the DA settling time is comparable with the MOS logic gate delay. To minimize the number of logic gates and their delay, a dynamic OR gate shown in Fig.7(b) is used instead of traditional MOS gates. V B is used to control the current flowing through OR gate, thus tuning the gate delay. Fig. 8. hip micrograph. to comparator offset mismatches. After performing the V cm - adaptive offset calibration, DNL and INL are reduced significantly to -.4LSB/.9LSB and -./.6LSB, respectively. The effectiveness of the calibration can also be observed from the measured spectrum shown in Fig., where 4.dB and 8.5dB improvements are achieved after calibration. DNL [LSB] INL [LSB] Output code Fig. 9. Measured DNL/INL before calibration (dotted line) and after calibration (solid line). Spectrum [dbfs] =.5dB =4.8dB =4.8dB =5.dB Fig. 7. Schematic of (a) bootstrapped switch and (b) dynamic OR gate. IV. MEASUREMENT RESULTS The prototype AD is fabricated in 4-nm MOS and occupies an active area of only.4mm, as shown in Fig. 8. Unlike the floor plan in [], where the DA and SAR logic are placed side by side, SAR logic is placed between two DAs in our design. By doing this, long routing wires are avoided, which saves both area and power. The outputs are decimated by using 5 divide-by- toggle flipflops to facilitate AD measurements. All measurements are performed under.v power supply. Fig. 9 shows the measured DNL and INL before and after performing the proposed comparator offset calibration. ibration, large DNL and INL jumps happen due Fig.. Measured 4p FFT spectrum before calibration and after calibration with 6MS/s sampling rate and MHz input. Fig. shows the measured FFT spectrum with 7MS/s sampling rate and MHz input. The measured and are 4.8dB and 47.8dB, respectively, leading to 5.5-bit ENOB. When the input frequency is reduced to MHz, the measured and are 5.dB and 49.5dB, respectively. Fig. shows and at different sampling frequencies with a 5MHz input, at different input frequencies with 7MS/s sampling rate, and at different input amplitudes with MHz input and 7MS/s sampling rate. The measured is above 4.7dB across the whole Nyquist band. The maximum sampling rate of 7MS/s is limited by insufficient sampling time discovered during chip measurements. When (c) 6 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

5 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. ontent may change prior to final publication. itation information: DOI.9/TSII , IEEE 5 se goes low, it takes longer time to reset comparators in measurements than that in simulation, which reduces the effective sampling time. The total power consumption at 7MS/s is.95mw, whose breakdown is:.84mw used by SAR logic and comparator,.9mw used by DA, and.mw used by clock generator. The measured Walden figure-of-merit (FOM) [] at Nyquist rate is fj/conversion-step and Schreier FOM [] is 5.4dB. As shown in Table I, this work achieves the highest and the best FOM with the smallest chip area compared to other state-of-art 6-bit designs. Spectrum [dbfs] fs=7ms/s fin=mhz =4.8dB =47.8dB Fig.. Measured 4p FFT spectrum with 7MS/s sampling rate and MHz input. / [db] fs [MS/s] fin [MHz] Input amplitude [dbfs] Fig.. Measured / under different sampling rates with 5MHz input (left), under different input frequencies with 7MS/s sampling rate (middle), and under different input amplitudes with 7MS/s sampling rate and MHz input (right). V. ONLUSION This brief presented a high-speed and low-power singlechannel loop-unrolled SAR AD. It proposed a simple method to calibrate the comparator offsets. The proposed switching technique allows the designers to control comparator input common-mode voltage for comparator offset and speed optimization. It can be easily time-interleaved (TI) for even higher speed applications. VI. AKNOWLEDGMENT The authors are grateful to the TSM University Shuttle Program for chip fabrication. REFERENES [] Z. Zhu and Y. Liang, A.6-V 8-nW 9.4-ENOB -ks/s SAR AD in.8µm MOS for medical implant devices, IEEE Trans. ircuits and Systems I, vol. 6, no. 9, pp , Sep. 5. [] L. hen et al, A.5-b ENOB 6nW ks/s SAR AD with statistical estimation based noise reduction, IEEE I, pp. 4, Sep. 5. TABLE I PERFORMANE OMPARISON. [4] [5] [9] [] This work Resolution [Bits] Process [nm] Supply voltage [V]..... Active area [mm ] Number of TI channels Sampling rate [GS/s] (Nyq) [db] ENOB [bit] Power [mw] Walden FoM [fj/step] Schreier FOM [db] [] Z. Zhu et al., A 6-to--Bit.5 V-to-.9 V reconfigurable MS/s power scalable SAR AD in.8µm MOS, IEEE Trans. ircuits and Systems I, vol. 6, no., pp , March 5. [4] S. hen and R. Brodersen, A 6-bit 6-MS/s 5.-mW asynchronous AD in.-µm MOS, IEEE J. Solid-State ircuits, vol. 4, no., pp , Dec. 6. [5] J. Yang, T. Naing, and R. Brodersen, A GS/s 6 bit 6.7 mw successive approximation AD using asynchronous processing, IEEE J. Solid-State ircuits, vol., no. 8, pp , Aug.. [6] H. Wei et al., An 8-b 4-MS/s -b-per-cycle SAR AD with resistive DA, IEEE J. Solid-State ircuits, vol. 47, no., pp , Nov.. [7] H.-K. Hong et al., A.6 b/cycle-architecture-based b.7 GS/s 5.4mW 4X-time-interleaved SAR AD with a multistep hardwareretirement technique, IEEE Int. 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