Baker Ch 13: Clocked Circuits
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1 Topics: 1. Intro Foil 2. CMOS Transmission Gate Definition 3. Delay of TG 4. Applications of TG-Selector 5. Applications of TG-MUX 6. TG vs. Pass Transistor 7. Applications of TG-OR, XOR, XNOR 8. SR Latch-NAND, NOR 9. NAND Arbiter 10. Latch I/O Characteristics 11. Level Sensitive Latch 12. Edge-Triggered DFF 13. Edge DFF with Async SR, DFF Setup and Hold Dr. Joseph A. Elias, Adjunct Professor 1
2 CMOS Transmission Gate Definition TG passes a signal from IN to OUT or Z state, based on control signal Designer must create S and Sbar control signal Timing of S and Sbar are ideally the same, but it may have an impact NMOS passes 0 and PMOS passes 1 Why? Hint: Think of definition of source in both NMOS and PMOS Dr. Joseph A. Elias, Adjunct Professor 2
3 CMOS Transmission Gate Delay TG has delay associated with passing signal from in to out RC delay is due to channel resistance of (N P) C load Control signals should be simulated through inverters to mimic Si driver Rn and Rp can be varied to modify delay Dr. Joseph A. Elias, Adjunct Professor 3
4 Applications of TG-Selector Z = A or B depending on S Output is always on, no high impedance state S 0 1 Z B A Dr. Joseph A. Elias, Adjunct Professor 4
5 Applications of TG-MUX MUX selects one output from multiple inputs Below example is 4-to-1 MUX What is the limitation of MUX input to output? DEMUX, flip inputs and outputs S S Z D C B A Dr. Joseph A. Elias, Adjunct Professor 5
6 TG vs. Pass Transistor TG uses CMOS, Pass Transistor uses NMOS TG count = 16 PT count = 8 or 6 Why not do it all the time? What is the limitation? Dr. Joseph A. Elias, Adjunct Professor 6
7 Applications of TG-OR, XOR, XNOR OR: A=1, B=1, PMOS=on, TG off, out=a (1) A=0, B=1, PMOS=off, TG on, out=b (1) A=1, B=0, PMOS=on, TG off, out=a (1) A=0, B=0, PMOS=off, TG on, out=b (0) Same ideas for XOR, XNOR Dr. Joseph A. Elias, Adjunct Professor 7
8 SR Latch-NAND, NOR Basic latch used in DFF Set Rest Latch : S=1 output is 1, R=1 output is 0, S=R depends on type Dr. Joseph A. Elias, Adjunct Professor 8
9 NAND Arbiter Arbiter choose which input arrived first In1=0, In2=0: zero and anything is zero, output of NANDs are 1, OUT=0 In1=1, In2=0: top output=0, keeps bot output=0, OUT2=0 So the IN1 is the winner regardless of what IN2 does Dr. Joseph A. Elias, Adjunct Professor 9
10 Latch I/O Characteristics Latch I/O, ideally sharp transfer between states Butterfly curve represents the regions where both inverters contribute What is the issue with the characteristic? Matastability is not a desired state, want inverters to settle Can avoid the problem by various methods described in the text Dr. Joseph A. Elias, Adjunct Professor 10
11 Level Sensitive Latch Level sensitive latch changes state with a level change NMOS PG will lower D value I2 will battle with D change, increase the lengths, i.e., reduce the current Q output will change when clock is high, stores that value Delays going 0 1 different than from 1 0 Q=D After delay Q=D After shorter delay Dr. Joseph A. Elias, Adjunct Professor 11
12 Improved Level Sensitive Latch Add in TG Delays between 1 0 and 0 1 are same Why? Q=D After delay Q=D After same delay Dr. Joseph A. Elias, Adjunct Professor 12
13 Edge-Triggered DFF DFF changes state on the rising edge of the clock Delays exist, why? Very important to have clocks with quick rise times What is the issue if the clocks are slow? D=0 (B=1) Latch Master Q=D After rising edge of clock After some delay Dr. Joseph A. Elias, Adjunct Professor 13
14 Edge DFF with Async SR Set and Reset DFF, duplicate for CAD4 Transfer of signal between D and B is setup time before clock latches Hold time is how long it must remain after clock is applied to latch t h can be smaller as the t s means t h must be latched before next t s Dr. Joseph A. Elias, Adjunct Professor 14
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