Monolithic Integration of Chip-scale Photonic Networks in Si-CMOS

Transcription

1 Monolithic Integration of Chip-scale Photonic Networks in Si-CMOS Mark Beals MIT Microphotonics Center Microphotonics Center Spring Meeting April 29, 2008

2 Acknowledgements This work was sponsored by: Defense Advanced Research Projects Agency's (DARPA) EPIC and UNIC programs supervised by Dr. Jagdeep Shah under contract no. HR C Andy Pomerene, Dan Carothers, Jim Beattie, Tim Conway, Joseph Gunta, Matthew Gregory, Craig Hill, Tom McIntyre, Vu A. Vu of BAE Systems - Douglas Gill, Sanjay Patel, Mahmud Rasras, Kun-Yi Tu, Y K Chen, Alice White of Alcatel Lucent Bell Laboratories - Michael Watts, Sandia National Labs - Jim Psota, Jonathan Eaststep, Jason Miller, and Prof. Anant Agarwal MIT CSAIL - Donghwan Ahn, Ching-yin Hong, Jifeng Liu, Jurgen Michel, Dan Sparacin, Rong Sun, and Prof. Lionel Kimerling MIT EMat & MPC

3 Outline Si CMOS Platform Photonic materials - Silicon - Germanium Active photonic devices - Detectors - Modulators Chip-scale Photonic Network Summary

4 RF Channelizer Elements for EPIC Technology Optical Channellizer Input: RF Signal Full Spectrum 300 MHz to >10 GHz DRIVER TUNING Filter 1 Detector TIA LASER Modulator Multi-mode Interferometric Splitter Output: to Signal Processing EPIC Filter n Detector TIA Functional Elements Optical power source Signal Encoding Signal Routing MUX/DEMUX Channel Tuning Signal decoding Photonic Devices - Mode transformer - Modulator - Waveguides - Splitters, Combiners MMI Directional Couplers - Filters Resonators Phase shifters - Photodiode Electronic Devices Modulator Driver Phase Shifter Control TIA

5 Silicon: Materials Platform for Photonics Potential Dense E-P integration with CMOS Leverage from silicon processing infrastructure Very low cost integration High volume production New applications with E-P convergence Barriers Light sources Packaging and interconnection infrastructure ICE Sept Has potential to provide the majority of low-cost photonic interconnects in the medium to long term

6 CMOS Device Fabrication CMOS Logic Platform Technology Insertion node: 180nm Bulk Silicon substrate, 150mm Transistor gate: Vdd: 1.8V, <3.3V Device Isolation: STI Global Planarization: CMP 193nm DUV Lithography Salicide contacts Contacts & Vias: W IMD: SiO 2 Interconnect: AlCu 1.1µm 1.0µm <450 < * 900 Metal AlCu, Local interconnect levels 1-4 IMD SiO2, Planarized Vias W studs Contacts W studs PMD SiO2, Planarized Salicide, Ti, Co Gate, S/D junctions Silicon Substrate p- CMOS FET & Interconnect *Salicide spike anneal 1050 C

7 Monolithic Integration of Photonics in CMOS Target Areas for Integration Si CMOS FEOL BEOL FEOL/PMD* Shared area with FET s BEOL Interconnect* SiGe T limit <450 C Hybrid integration 3D Interconnect stack Chip backside attach Integration Challenges Circuit Performance Thermal budget management cross contamination Yield Reliability Cost <450 < * 900 Bulk Si Si FET SiGe SOI Bulk Si or SOI Photonic Integration Scenarios

8 Outline Si CMOS Platform Photonic Materials - Silicon - Germanium Active photonic devices - Detectors - Modulators Chip-scale Photonic Network Summary

9 HIC Waveguides : Mode Size TE Polarization E field Contours Si Core, SiO2 Cladding Core: 200x500 nm 2 Core: 200x200 nm 2 z - um n eff =2.365, Γ= Simulated with FIMMWAVE For minimal size, waveguides should be designed for maximum confinement, but restricted to singlemode cutoff x - um n eff =1.473, Γ=0.044 Lower transmission loss can be achieved at low confinement, but requires a larger modal volume

10 Optical Interconnect Silicon Core Waveguide Materials SOI Silicon Waveguides degree Bend Loss (db/cm)2.5 r = 1 um r = 2 um r = 3 um r = 5 um r = 10 um α- - Silicon Waveguides SOI waveguides achieved Wavelength (nm) 0.35 db/cm transmission loss No bulk absorption, lowest loss High Temperature tolerance seed for EPI films: Ge, SiGe PECVD silicon waveguides, highly confined achieved state of the art ~4dB/cm loss Low temperature PECVD film <450 C Integration in metal interconnect Global & Local Optical Interconnect using DUV Photolithography 0.0

11 Low Loss SOI Waveguides at STI Level Following n-well & p-well implants: Resist Xtal-Silicon CVD-SiN/SiO 2 Xtal-Silicon CVD-SiO 2 SOI BOX BOX BOX Silicon Silicon Silicon Edge View Edge View STI/Channel Waveguide Etch 1. Pad Ox & nitride as hardmask 2. RIE Etch oxide* 3. RIE Etch - silicon 4. Resist Strip Waveguide Smoothing 1. 3X SC1 Wet Etch - Dilute HF - NH4OH:H2O2:H2O - Dilute HF 2. Sidewall Liner Oxidation Lower ILD & Initial Top Clad 1. CVD Oxide Deposition 2. Oxide CMP *Greater process reproducibility and uniformity using channel waveguides vs ridge Leverages existing STI process with compatibility post etch wet cleans

12 New: 2 nd Level Coupled Waveguides in PMD After transistor polysilicon gate formation, sidewall spacer, l dd & HALO implants: Resist α-silicon PECVD -SiO 2 PECVD -SiO 2 PECVD -SiO 2 SOI BOX Xtal-Silicon Silicon BOX Silicon Xtal-Silicon BOX Silicon Xtal-Silicon Deposit Oxide & Silicon Films - PECVD Oxide Deposition 200nm - Vertical coupling spacer - PECVD α-silicon deposition 200nm - Resist coat, expose, develop Etch waveguide & top clad - Silicon RIE - Resist Strip - HDP Oxide deposition Prep for next step - CMP to thickness

13 Active Photonic Materials

14 Ge Detector Designs Graded buffer layer growth + Low dislocation density (~10 6 cm -1 ) - Thick buffer (1µm) difficult integration - Absorption in buffer leads to diffusion tail - Integration with waveguides difficult GeOI + Very low dislocation density - Requires ultra-thin SOI or wafer bonding - Integration with waveguides difficult Ge-directly-on-Si + Flexible growth conditions + SOI compatible + Easy integration with waveguides - Dislocation density ~ 10 7 cm-1 Samavedam, et al. Koester, et al.

15 Ge Growth and Dislocation Reduction A. Single Step Growth Cyclic thermal annealing, 900 C 700 C 1 cycle 550C - Islanding B. Two Step Growth Ge SiO 2 10µm Ge Si 50 nm 1. Low temp <360 C amorphous Ge film C EPI Ge growth Deposit flat Ge epilayer on Si by a two-step CVD process. 10 cycles 10µm Annealing process results in dislocation free mesas A. Luan

16 Ge Processing for Active Photonic Devices UHV-CVD EPI Ge & SiGe Films Ge SiO Ge SiO Si Si AFM of as grown Ge Film Ge Growth on Si Temperature 700C, 4.5h Growth Rate = 2.4 nm/min Roughness < 4nm rms RIE Patterned Ge Ge growth, blanket Patterned Ge etch Oxide Fill CMP Ge Damascene Oxide deposition Oxide trench etch Ge Trench Fill CMP Planarization Two Processes for CMOS FEOL Integration

17 Outline Si CMOS Platform Photonic Materials - Silicon - Germanium Active photonic devices - Detectors - Modulators Chip-scale Photonic Network Summary

18 Ge Detector Design Comparison Discrete Free Space Waveguide Integrated λ l a λ t = l α Ge t l α Ge n - i p + n - p + Vertical pin Ge Diode Larger Area: 10 um x 70 um, - greater capacitance Thickness: t = 2.3 um - longer transit time - absorption length in line with E Capacitance: ff Vertical pin Ge Diode Smaller Area: 0.5 um x 25 um - smaller capacitance Thickness: t = 0.6 um - shorter carrier transit time - Absorption length independent of thickness Capacitance: 5-10 ff

19 Freespace Ge Diode Performance Diode size: 10 x 70 µm, Ge thickness: 2.3µm Broad detection spectrum of nm Internal efficiency > 90% nm Bandwidth: nm Low voltage operation at ~1V can be achieved Responsivity (A/W 1.2 Ideal Responsivity V 0V Wavelength (nm) Liu et al., Appl. Phys. Lett. 87, (2005) Normalized Response (db) dB Bandwidth (GHz) Reverse Bias (V) Frequency (GHz) f3db =8.5GHz

20 Bottom Coupled Ge Photodetector SOI Substrate - Si crystal waveguide - BOX lower cladding Ge (or SiGe) trench growth Planarized Multi-level interconnect a-si SOI Si Ge p Electrical isolation of contact regions in SOI Lower p+ contacts in SOI Si n Top n+ polysi electrode Selective, trench grown Ge λ Bottom coupled SOI silicon input waveguide

21 Bottom Coupled Ge-0.8% Si pin Detector Responsivity (A/W µm 5 µm Wavelength (nm) Photoresponse (V) 8.0m 6.0m 4.0m 2.0m 0.0 RF response (db) Frequency (GHz) Time (psec) Direct bandgap for Ge-0.8% Si is 1520nm 3dB Bandwidth ~1.5 GHz - RC delay limited - High series resistance of device contacts D. Ahn, MIT LEOS 2006

22 Butt Coupled Ge Devices w/vertically Coupled Si Multilevel Waveguides SOI Substrate - Low loss si waveguides - Device isolation Multi- level waveguides Vertical I/O couplers Through device butt couplers Center guided mode Selective, trench grown SiGe EPI Multi-level interconnect λ n p λ SiGe n+ contact p+ contacts Butt coupler Vertical I/O couplers Waveguides & Vertical Coupler α-silicon xtal-silicon CVD-SiO 2 vertical coupler Ge growth, CMP & Top electrode butt coupler n+ region Contacts & Interconnect n+ region SiGe 0.6um SOI BOX λ in p+ region λ out p+ region Silicon Edge View Side View Edge View

23 Bottom SOI waveguide taper Responsivity (A/W) Taper tip width Si WG Vertical Couplers Taper Length SOI Oxide 1.4 Ideal Responsivity a-si Top a-si waveguide taper Loss per coupler: ~0.14 db TE Butt coupled detector performance improvement Without improved coupler a-si waveguide butt-coupled µm SiGe detector -30 Phase Phase Wavelength (nm) Responsivity (A/W) Insertion loss (db) Wavelength (nm) 45um long, 250 nm wide tip RF Power (dbm) -40 Roll off due to the limitation of TIA With improved coupler -50 Detector bandwith >4.5GHz RF Frequency (GHz) Wavelength (nm) y = x R 2 = Number of couplers

24 Bottom Coupled Ge Photodetector After STI Etch/waveguide formation & FET fabrication: Salicide contact Ldd p-implant a-silicon Oxide Resist a-si Oxide Oxide SOI BOX BOX BOX Silicon Silicon Silicon Edge View Side View Side View Lower p-type electrode - l dd implant p-type - FET s & Ge lower electrode - 1E19/cm3 concentration. Finish FET implants - Thin oxide deposition - Salicide contact mask - Cobalt sputter - Salicide formation spike anneal Deposit & pattern si waveguide - Deposit 200nm oxide spacer - Deposit 200nm PECVD a-silicon - Resist pattern - Silicon removed in trench area Set Ge Trench Thicnkness - Deposit 200nm oxide spacer - Deposit 200nm PECVD a-silicon - Resist pattern - Silicon removed in trench area - PECVD Oxide deposition ~350nm - CMP to thickness 600nm - PECVD nitride dep 100nm - CMP to thickness

25 Butt Coupled SiGe Devices Using Vertically Coupled Si Multilevel Waveguides a-si a-si a-si Oxide Oxide 0.6um BOX Silicon Side View BOX Silicon Side View BOX Silicon Side View Tapered Vertical Couplers - Deposit 200nm oxide spacer - Deposit 200nm PECVD a-silicon - Resist pattern - Silicon removed in trench area - PECVD Oxide deposition ~350nm - CMP to thickness 600nm - PECVD nitride dep 100nm Trench Open - Deposit 200nm oxide spacer - Deposit 200nm PECVD a-silicon - Resist pattern - Silicon removed in trench area - PECVD Oxide deposition ~350nm - CMP to thickness 600nm - PECVD nitride dep 100nm - Ge trench mask - RIE oxide etch Selective Ge (Ge-Si) Trench Fill - Wet etch trench clean - Selective UHVCVD Ge (Ge-Si) EPI - Ge CMP, stop on SiN

26 Ge Vertical p-i-n Top Electrode Fabrication Implanted n-type PECVD-a-Si CVD-SiO 2 HDPCVD-SiO 2 AlCu M1 W Ge Ge n+ region Ge 1.0um SOI BOX Silicon SOI BOX Silicon BOX Silicon p+ region Edge View Edge View Edge View Upper n-type electrode -PECVD a-si 100nm -n-type ldd implant -1E19/cm3 concentration -(no mask required) -Top Ge electrode pattern -a-silicon etch Complete PMD -HDPCVD SiO2 -Oxide CMP Contacts & First Metal - Oxide Contact etch - W CVD film - W CVD - Metal One sputter - Metal One Etch All Fundamental Photonic Components have been defined within 600nm of the silicon surface

27 SOI Silicon Butt Coupled SiGe Photodetector ( % Si) Waveguide integration: - Transit time decoupled from RC Flat responsivity from nm - 80 µm-long Ge device High 1 A/W responsivity at full BW: - RC device = 12 ps Dark current: 0.2nA at full BW bias (1V) p+ Al/Cu W CT1 SOI SiGe a-si (n+) HDP Top Oxide BOX W CT2 Responsivity (A/W) Wavelength (nm) I (A) 10! 1! 100n 10n 1n 100p 10p Lengh=50 µm Width=0.6 µm Thickness=0.4 µm C = 8 ff 1p Voltage (V) RF Power (dbm) Detector bandwith>4.5ghz Roll off due to the limitation of TIA RF Frequency (GHz)

28 Detector-Waveguide Integration Overview Responsivity Top- coupled >1.0 A/W Bottom-coupled (SOI) 0.22 A/W Butt-coupled (SOI) 1.0 A/W Bandwidth 7.2 GHz 2.0 GHz >4.5 GHz Dark current at operation 60 Capacitance 14 ff 11 ff 8 ff Size 5x10 µm 2 2x20 µm 2 0.6x50 µm 2 Performance Good Top coupled SiN WG Poor Improved responsivity needed Best High power, Through coupling Flat response in broad wavelength range of nm

29 Silicon Micro-ring Modulator Width = 450nm Gap = 200nm Diameter = 12 μm Lowest power consumption reported to date. Less than 0.3V and µa current needed for complete modulation in DC. In AC, 3.3Vpp and 1mA current were used Gb/s recently reported 1.5 Gbit/s using RZ pattern M. Lipson, Cornell

30 EA Modulator: Franz-Keldysh Effect Linear Electro-Optic Effect for Ge on Si Δn(E), Δα(E) Ge-on-Si: comparable to InP Strong F-K Effect strain reduces separation between E g Γ and E g L F-K regime in low absorption background Large Bandwidth covers C-Band with little performance variations Working regime ϖ!"/"(0) 4.0!"="(100kV/cm)-"(10kV/cm) Wavelength (nm) 0.5% 0.6% 0.7% 0.75% 0.8% 0.9% 1.0% 1.1%

31 GeSi EA Modulator (Ge-0.8%Si) Relative Transmission Change Calculation 8 kv/cm Calculation 40 kv/cm Wavelength (nm) Modulation Depth (%) 100 Si GeSi Si Calculated Experimental, Lot 350 (old) Experimental, Lot 032 (new) Electric Field (kv/cm) a. ) FK Simulations b. ) EA Modulator measured response c. ) Modulation Depth Increased electric field will deepen FK oscillations and increase spacing between peaks 70% modulation depth achieved with 40kV/cm electric field at 1560nm - Modulation depth vs. electric field at 1560nm agrees with theoretical analysis. - Modulation depth limited by large series resistance from first processing run

32 Thermo-optic Phase Shifters Salicide M1 W SiGe SiGe SiGe p-i-n Device Filter & Waveguides SiGe p-i-n Device Filter & Waveguides Thermo Optic Phase Shifters - HDP CVD Oxide Deposition um overall height - Oxide CMP - Polysilicon deposition - Heater pattern - Cobalt sputter - Salicide formation BEOL Interconnect - Oxide spacer - Contact etch - W CVD fill - W CMP - BEOL POR

33 Narrow, Tunable Filter Channels in SOI R1 R2 R3 R4!=0.5 Fabricated in BAE Systems silicon CMOS foundry Transmittance (db) 4th Order Filter Passive output (as fabricated) Tuned output Frequency (THz) Transmittance (db) In!=0.5 0 f0-2.5 GHz f0 f0+2.5 GHz Frequency (THz) Demonstrated fully tunable, integrated optical filters with fine passband resolution (1 GHz) and excellent out of band rejection (>25 db) Single design can work for all channels!

34 LV New Process Steps for CMOS Front End Photonic Integration M3 M2 M1 Metal 3 Via 2 Metal 2 Via 1 Metal 1 Contacts Waveguide routing in SOI SOI BOX optical isolation Si wafer: Oxide filled trench optical isolation, extension of STI Planarized deposited waveguides & cladding Trench filled & planarized EPI SiGe growth n+ Top polysilicon electrode implant & patterning Thermally tunable elements SiGe n+ implant (ldd) Polysilicon top SiGe electrode SiGe Detector/Modulator Deposited Si waveguide p+ implant (ldd) SOI Waveguide SiGe p-i-n Device Filter & Waveguides

35 Outline Si CMOS Platform Photonic Materials - Silicon - Germanium Active photonic devices - Detectors - Modulators Chipscale Photonic Networks Summary

36 The Future of Multicore Number of cores will double every 18 months Academia Industry But, wait a minute Performance? Power Efficiency? Programming? 02 MIT RAW 6.8 GOPs at 425 MHz Anant Agarwal, MIT

37 Performance Challenge: The Interconnect Bus Multicore p c p c BUS p c p c Ring Multicore p c p c p c s s s s Processor architecture transistors are free memory is free can bandwidth be free? Anant Agarwal Mesh Multicore p p p c c c s s p p p c c c s s p c p c p c s s s s s Anant Agarwal, MIT 25

38 Photonic Intrachip Communications Tiles can directly communicate with any other tile Broadcasts require just one send No complicated routing on network required Tile resources only used when performing communication (unlike mesh approach)

39 Photonic Channel Architecture Transmission of 1 bit from one tile to another Transmission of words using 1-bit waveguides multi-wavelength source waveguide filter/ modulator data waveguide modulator driver filter transimpedance amplifier photodetector FIFO 32 FIFO 32 FIFO FIFO FIFO FIFO flip-flop sending tile flip-flop receiving tile Each tile sends data using a different wavelength no contention Data is sent once, any or all tiles can receive it efficient broadcast Transimpedance amplifier (TIA) is not needed beyond 65 nm process node Processor Core tile #1 Processor Core tile #3 Processor Core receiving tile 32-bit data words transmitted across several parallel waveguides Each tile contains a set of receive filters and a FIFO buffer for every sender Data is buffered at receiver until needed by the processing core Receiver can screen data by sender (i.e. wavelength) or message type

40 Communications Performance On-chip Optical Communications Network Bisection Bandwidth (BB): T BW = 2.5Tb/s (300fJ/bit) Receive-Weighted BB (bursts): R BW = 161Tb/s (5fJ/bit) Total Latency: 3ns (gate delay + propagation delay) Optical Performance Summary (64 cores, 1GHz) Electrical Mesh Network (64 core) (Four 64-bit (256-bit total), bidirectional networks, 1 GHz) Bisection bandwidth (BB): 64 bits x 2 x 64 x 1 GHz x 4 = T BW = 4 Tb/s Receive-Weighted BB: R BW = 4 Tb/s Total Latency: 1 ns (min), 8 ns (avg), 16 ns (max) Energy: 94 fj/bit (min), 752 fj/bit (avg), 1.5 pj/bit (max) Note: Modestly scalable and difficult to program p p c c s s p p c c s s Electrical bus (unscalable) 256-bit bus at 1GHz Bisection bandwidth (BB): 256 x 1GHz = 0.25 Tb/s Does not scale to more than 8 or 16 cores Optical has 4x better latency, 40x better (receive-weighted) bandwidth, 5x better energy Combine the best of electrical and optical technologies Electrical mesh network for short-distance, point-to-point communication Optical ANET for long-distance and broadcast/multicast communication Aggregate bisection bandwidth: 2.5 Tb/s + 4 Tb/s = 6.5 Tb/s Aggregate RWBB: 161 Tb/s + 4 Tb/s = 165 Tb/s

41 Chipscale Photonic Network Vision Broadcast Computing Vision communication-centric on-chip computing energy efficient on-chip computing fast, contention-free optical broadcasts high performance with easy programming scalable to 1000 s of cores Challenges monolithic, high density E-P integration optical power capacity core-to-network interface efficient new multicore programming model Optical Performance (64 to 4096 cores) 132 to 5000 Tb/s receive-weighted bisection bandwidth up to 45x faster computation up to 9x better power efficiency reduced off-chip memory accesses Optical BW : one send can replace 64 point-to-point messages I/O I/O DRAM OpNET 1 DRAM ENET OpNET DRAM DRAM 0 The Optical Processor Interconnect Core: contains a single processor with FPU Region: collection of 1-64 cores that share the same optical resources OpNET: Broadcast network: optical broadcastand-select network, low-latency, contention-free ENET: Mesh network: scalable electrical mesh network for short-distance, pt-to-pt comm. I/O I/O

42 Conquering the Last Centimeter The Philosophy Integration creates a circuit function. not customized perfect devices A microphotonic circuit contains replicated circuit elements on a standard platform. materials, processes, design and fab tools Silicon Microphotonics is the only option for continued exponential increase in chip performance. Has potential to provide the majority of low-cost photonic interconnects in the medium to long term

43 Thank You