FAN7930C Critical Conduction Mode PFC Controller

Transcription

1 FAN7930C Criical Conducion Mode PFC Conroller Feaures PFCReady Signal VINAbsen Deecion Maximum Sw iching Frequency Limiaion Inernal SofSar and Sarup w ihou Overshoo Inernal Toal Harmonic Disorion (THD) Opimizer Precise Adjusable Oupu OverVolage Proecion OpenFeedback Proecion and Disable Funcion ZeroCurren Deecor (ZCD) 150 μs Inernal Sarup Timer MOSFET OverCurren Proecion (OCP) UnderVolage Lockou w ih 3.5 V Hyseresis Low Sarup and Operaing Curren ToemPole Oupu w ih High Sae Clamp 500/800 ma Peak Gae Drive Curren 8Pin, Small Ouline Package (SOP) Applicaions Adaper Ballas LCD TV, CRT TV SMPS Descripion The FA N7930C is an acive pow er facor correcion (PFC) conroller for boos PFC applicaions ha operae in criical conducion mode ( CRM). I uses a volagemode PWM ha compares an inernal ramp signal w ih he error amplifier oupu o generae a MOSFET urnoff signal. Because he volagemode CRM PFC conroller does no need recified A C line volage informaion, i saves he pow er loss of an inpu volagesensing new ork necessary for a currenmode CRM PFC conroller. FA N7930C provides overvolage proecion (OV P), openfeedback proecion, overcurren proecion (OCP), inpuvolageabsen deecion, and undervolage lockou proecion (UVLO). The PFCready pin can be used o rigger oher pow er sages w hen PFC oupu volage reaches he proper level w ih hyseresis. The FAN7930C can be disabled if he INV pin volage is low er han 0.45 V and he operaing curren decreases o a very low level. Us ing a new variable onime conrol mehod, oal harmonic disorion (THD) is low er han in convenional CRM boos PFC ICs. Relaed Resources AN8035 Design Consideraion for Boundary Conducion Mode PFC Using FAN7930 Ordering Informaion Par Number Operaing Temperaure Range Top Mark Package Packing Mehod FAN7930CMXG 40 o 125 C FAN7930C 8Lead, Small Ouline Package (SOP) Tape & Reel 2010 Semiconducor Componens Indusries, LLC. Publicaion Order Number: November2017, Rev. 2 FAN7930C/D

2 Applicaion Diagram line filer AC INPUT Inernal Block Diagram PFC ready Vcc Figure 1. FAN7930C 8 VCC Ou 5 ZCD CS 3 COMP 2 INV RDY GND 6 Typical Boos PFC Applicaion DC OUTPUT VCC VREF VBIAS 2.5VREF Inernal Bias VCC H:open rese VZ 8 V CC ZCD 5 Clamp Circui VCC VTH(S/S) VTH(ZCD) Resar Timer fmax limi Gae Driver VO(MAX) 7 OUT THD Opimized Sawooh Generaor Conrol Range Compensaion S R Q Q INV 1 VREF VREF Sair Sep Sarup wihou Overshoo rese Clamp Circui VIN Absen VCS_LIM 8pF 40kW 4 CS 6 GND COMP 3 RDY 2 INV_open OVP UVLO disable VBIAS disable Thermal Shudown Figure 2. Funcional Block Diagram 2

3 Pin Configuraion Pin Definiions Pin # 1 INV 2 RDY 3 COMP 4 CS 5 ZCD 6 GND 7 OUT Name Descripion V CC OUT GND FAN7930C 8SOP ZCD INV RDY COMP CS Figure 3. Pin Configuraion (Top View ) This pin is he invering inpu of he error amplifier. The oupu volage of he boos PFC converer should be resisively divided o 2.5 V. This pin is used o deec PFC oupu volage reaching a predeermined value. When oupu volage reaches 89% of raed oupu volage, his pin is pulled HIGH, w hich is an (opendrain) oupu ype. This pin is he oupu of he ransconducance error amplifier. Componens for he oupu volage compensaion should be conneced bew een his pin and GND. This pin is he inpu of he overcurren proecion comparaor. The MOSFET curren is sensed using a sensing resisor and he resuling volage is applied o his pin. An inernal RC filer is included o filer sw iching noise. This pin is he inpu of he zerocurren deecion (ZCD) block. If he volage of his pin goes higher han 1.5 V, hen goes low er han 1.4 V, he MOSFET is urned on. This pin is used for he ground poenial of all he pins. For proper operaion, he signal ground and he pow er ground should be separaed. This pin is he gae drive oupu. The peak sourcing and sinking curren levels are 500 ma and 800 ma, respecively. For proper operaion, he sray inducance in he gae driving pah mus be minimized. 8 V CC This is he IC supply pin. IC curren and MOSFET drive curren are supplied using his pin. 3

4 Absolue Maximum Raings Sresses exceeding he absolue maximum raings may damage he device. The device may no funcion or be operable above he recommended operaing condiions and sressing he pars o hese levels is no recommended. In addiion, exended exposure o sresses above he recommended operaing condiions may affec device reliabiliy. The absolue maximum raings are sress raings only. Symbol Parameer Min. Max. Uni VCC Supply Volage VZ V IOH, IOL Peak Drive Oupu Curren ma I CLAMP Driver Oupu Clamping Diodes V O>V CC or V O<0.3 V ma I DET Deecor Clamping Diodes ma V IN RDY Pin ( 1 ) Error Amplifier Inpu, Oupu and ZCD ( 1 ) CS Inpu Volage ( 2 ) T J Operaing Juncion Temperaure 150 C T A Operaing Temperaure Range C T STG Sorage Temperaure Range C ESD Elecrosaic Discharge Capabiliy Human Body Model, JESD22A Charged Device Model, JESD22C Noes: 1. When his pin is supplied by exernal pow er sources by acciden, is maximum allow able curren is 50 ma. 2. In case of DC inpu, he accepable inpu range is 0.3 V~6 V: w ihin 100 ns 10 V~6 V is accepable, bu elecrical specificaions are no guaraneed during such a shor ime. VZ V kv Thermal Impedance Symbol Parameer Min. Max. Uni JA Thermal Resisance, JuncionoAmbien ( 3 ) 150 C/W Noe: 3. Regarding he es environmen and PCB ype, please refer o JESD512 and JESD

5 Elecrical Characerisics VCC = 14 V and TA = 40 C~125 C, unless oherw ise specified. Symbol Parameer Condiions Min. Typ. Max. Uni VCC Secion V START Sar Threshold Volage V CC Increasing V VSTOP Sop Threshold Volage VCC Decreasing V HY UVLO UVLO Hyseresis V VZ Zener Volage ICC=20 ma V VOP Recommended Operaing Range V Supply Curren Secion ISTART Sarup Supply Curren VCC=VSTART0.2 V µa IOP Operaing Supply Curren Oupu No Sw iching ma IDOP Dynamic Operaing Supply Curren 50 khz, CI=1 nf ma IOPDIS Operaing Curren a Disable VINV=0 V µa Error Amplifier Secion V REF1 Volage Feedback Inpu Threshold1 T A=25 C V VREF1 Line Regulaion VCC=14 V~20 V mv V REF2 Temperaure Sabiliy of V REF1 ( 4 ) 20 mv I EA,BS Inpu Bias Curren V INV=1 V~4 V µa IEAS,SR Oupu Source Curren VINV=VREF 0.1 V 12 µa I EAS,SK Oupu Sink Curren V INV=V REF 0.1 V 12 µa V EAH Oupu Upper Clamp Volage V INV=1 V, V CS=0 V V V EAZ ZeroDuy Cycle Oupu Volage V g m Transconducance ( 4 ) µmho Maximum OnTime Secion ON,MAX1 Maximum OnTime Programming 1 T A=25 C, V ZCD=1 V µs ON,MAX2 Maximum OnTime Programming 2 CurrenSense Secion VCS CurrenSense Inpu Threshold Volage Limi T A=25 C, I ZCD=0.469 ma µs V ICS,BS Inpu Bias Curren VCS=0 V~1 V µa (4) CS,D CurrenSense Delay o Oupu dv/d=1 V/100 ns, from 0 V o 5 V ns Coninued on he following page 5

6 Elecrical Characerisics V CC = 14 V and T A = 40 C~125 C, unless oherw ise specified. Symbol Parameer Condiions Min. Typ. Max. Uni ZeroCurren Deec Secion VZCD Inpu Volage Threshold ( 4 ) V HY ZCD Deec Hyseresis ( 4 ) V VCLAMPH Inpu High Clamp Volage IDET=3 ma V VCLAMPL Inpu Low Clamp Volage IDET= 3 ma V I ZCD,BS Inpu Bias Curren V ZCD=1 V~5 V µa IZCD,SR Source Curren Capabiliy ( 4 ) TA=25 C 4 ma I ZCD,SK Sink Curren Capabiliy ( 4 ) T A=25 C 10 ma ZCD,D Oupu Secion Maximum Delay From ZCD o Oupu TurnOn ( 4 ) dv/d=1 V/100 ns, from 5 V o 0 V ns V OH Oupu Volage High I O=100 ma, T A=25 C V V OL Oupu Volage Low I O=200 ma, T A=25 C V RISE Rising Time ( 4 ) CIN=1 nf ns FALL Falling Time ( 4 ) CIN=1 nf ns V O,MAX Maximum Oupu Volage V CC=20 V, I O=100 µa V V O,UVLO Oupu Volage w ih UVLO Acivaed V CC=5 V, I O=100 µa 1 V Resar / Maximum Sw iching Frequency Limi Secion RST Resar Timer Delay µs f MAX Maximum Sw iching Frequency ( 4 ) khz RDY Pin I RDY,SK Oupu Sink Curren ma VRDY,SAT Oupu Sauraion Volage IRDY,SK=2 ma mv I RDY,LK Oupu Leakage Curren Oupu High Impedance 1 µa SofSar Timer Secion SS Inernal SofSof ( 4 ) ms UVLO Secion V RDY Oupu Ready Volage V HY RDY Oupu Ready Hyseresis V Proecions V OVP OVP Threshold Volage T A=25 C V HY OVP OVP Hyseresis T A=25 C V V EN Enable Threshold Volage V HYEN Enable Hyseresis V T SD Thermal Shudow n Temperaure ( 4 ) C T HYS Hyseresis Temperaure of TSD ( 4 ) 60 C Noe: 4. These parameers, alhough guaraneed by design, are no producion esed. 6

7 Comparison of FAN7530 and FAN7930C Funcion FAN7530 FAN7930C FAN7930C Advanages PFC Ready Pin None Inegraed No Exernal Circui for PFC Oupu UVLO Reduce Pow er Loss and BOM Cos Caused by PFC Ou UVLO Circui Versaile OpenDrain Pin Abnormal CCM Operaion Prohibied Frequency Limi None Inegraed Abnormal Inducor Curren Accumulaion Can Be Prohibied Increase Sysem Reliabiliy by Tesing for Inpu V INAbsen Supply Volage None Inegraed Deecion Guaranee Sable Operaion a Shor Elecric Pow er Failure SofSar and Sarup w ihou Overshoo Conrol Range Compensaion None None Inegraed Inegraed Reduce Volage and Curren Sress a Sarup Eliminae Audible Noise due o Unw aned OVP Triggering Can Avoid Burs Operaion a Ligh Load and High Inpu Volage Reduce Probabiliy of Audible Noise Due o Burs Operaion THD Opimizer Exernal Inernal No Exernal Resisor Needed TSD None 140 C w ih 60 C Hyseresis Sable and Reliable TSD Operaion Converer Temperaure Range Limied Range Comparison of FAN7930C and FAN7930B Funcion FAN7930C FAN7930B Remark RDY Pin Inegraed None User Choice for he Use of Number #2 Pin OVP Pin None Inegraed 7

8 Typical Performance Characerisics Figure 4. Volage Feedback Inpu Threshold 1 (V REF1) vs. T A Figure 5. Sar Threshold Volage (V START) vs. T A Figure 6. Sop Threshold Volage (V STOP) vs. T A Figure 7. Sarup Supply Curren (I START) vs. T A Figure 8. Operaing Supply Curren (IOP) vs. TA Figure 9. Oupu Upper Clamp Volage (V EAH) vs. TA 8

9 Typical Performance Characerisics Figure 10. Zero Duy Cycle Oupu Volage (VEAZ) vs. T A Figure 11. Maximum OnTime Program 1 (ON,MAX1) vs. T A Figure 12. Maximum OnTime Program 2 ( ON,MAX2) vs. T A Figure 13. CurrenSense Inpu Threshold Volage Limi (V CS) vs. T A Figure 14. Inpu High Clamp Volage (V CLAMPH) vs. TA Figure 15. Inpu Low Clamp Volage (VCLAMPL) vs. TA 9

10 Typical Performance Characerisics Figure 16. Oupu Volage High (V OH) vs. T A Figure 17. Oupu Volage Low (V OL) vs. T A Figure 18. Resar Timer Delay ( RST) vs. T A Figure 19. Oupu Ready Volage (V RDY) vs. T A Figure 20. Oupu Sauraion Volage (V RDY,SAT) vs. TA Figure 21. OVP Threshold Volage (V OVP) vs. TA 10

11 Applicaions Informaion 1. Sarup: Normally, supply volage (V CC) of a PFC block is fed from he addiional pow er supply, w hich can be called sandby pow er. Wihou his sandby pow er, auxiliary w inding for zero curren deecion can be used as a supply source. Once he supply volage of he PFC block exceeds 12 V, inernal operaion is enabled unil he volage drops o 8.5 V. If V CC exceeds V Z, 20 ma curren is sinking from VCC. VREF VBIAS 2.5VREF Inernal Bias VIN PFC VCC H:open rese Figure 22. PFC Inducor Aux. Winding VZ VTH(S/S) 20mA VOUT PFC Exernal V CC circui when no sandby power exiss Sarup Circui V CC 8 VCC VOUT PFC 390Vdc 70V VINV 2.50V 0.45V high UVLO OVP INV open disable disable RDY COMP 2.240V/2.051V 2.675V/2.5V 0.45V/0.35V 2.5V INV 1 Figure 23. Circui Around INV Pin 413V 390V 349V 320V 2.65V 2.50V 2.24V 2.051V VOUT PFC disable 55V 0.35V VCC 2. INV Block: Scaleddow n volage from he oupu is he inpu for he INV pin. Many funcions are embedded based on he INV pin: ransconducance amplifier, oupu OV P comparaor, disable comparaor, and oupu UVLO comparaor. For he oupu volage conrol, a ransconducance amplifier is used insead of he convenional volage amplifier. The ransconducance amplifier (volageconrolled c urren source) aids he implemenaion of he OV P and disable funcions. The oupu curren of he amplifier changes according o he volage difference of he invering and noninvering inpu of he amplifier. To cancel dow n he line inpu volage effec on pow er facor correcion, he effecive conrol response of he PFC bloc k should be slow er han he line frequency and his conflics w ih he ransien response of conroller. Tw opole onezero ype compensaion can mee boh requiremens. The OV P comparaor shus dow n he oupu drive block when he volage of he INV pin is higher han V and here is V hyseresis. The disable comparaor disables operaion w hen he volage of he invering inpu is low er han 0.35 V and here is 100 mv hyseresis. An exernal smallsignal MOSFET can be used o disable he IC, as show n in Figure 23. The IC operaing curren decreases o reduce pow er consumpion if he IC is disabled. Figure 24 is he iming char of he inernal circui near he INV pin w hen raed PFC oupu volage is 390 VDC and VCC supply volage is 15 V. 2.0V IOUT COMP Disable VRDY OVP 15V Curren sourcing Vcc<2V, inernal logic is no alive. RDY pin is floaing, so pull up volage is shown. Inernal signals are unknown. Figure 24. I sinking Volage is decided by pullup volage. Curren sourcing Timing Char for INV Block 3. RDY Oupu: When he INV volage is higher han 2.24 V, RDY oupu is riggered HIGH and lass unil he INV volage is low er han V. When inpu AC volage is quie high, for example 240 V AC, PFC oupu volage is alw ays higher han RDY hreshold, regardless of boos converer operaion. In his case, he INV volage is already higher han 2.24 V before PFC V CC ouches VSTART; how ever, RDY oupu is no riggered o HIGH unil VCC ouches VSTART. Afer boos converer operaion sops, RDY is no pulled LOW because he INV volage is higher han he RDY hreshold. When V CC of he PFC drops below 5 V, RDY is pulled LOW even hough PFC oupu volage is higher han hreshold. The RDY pin oupu is open drain, so needs an exernal pullup resisor o supply he proper pow er source. The RDY pin oupu remains floaing unil V CC is higher han 2 V. 11

12 V START V STOP 5V V CC V INV (=V PFCOUT ) 2.500V 2.240V 2.051V V START V STOP 5V V RDY V CC V INV (=V PFCOUT ) 2.500V 2.240V 2.051V Figure 25. VSTART VSTOP V RDY 5V V CC PFC operaion PFC operaion Tw o Cases of RDY Triggered HIGH PFC operaion 4. Conrol Range Compensaion: On ime is conrolled by he oupu volage compensaor w ih FAN7930 C. Due o his w hen inpu volage is high and load is ligh, conrol range becomes narrow compared o w hen inpu volage is low. Tha conrol range decrease is inversely proporional o he double square of he inpu volage ( ). Thus a high line, unw aned burs operaion easily happens a ligh load and audible noise may be generaed from he boos inducor or inducor a inpu filer. Differen from he oher converers, burs operaion in PFC block is no needed because he PFC block iself is normally disabled during sandby mode. To reduce unw aned burs operaion a ligh load, an inernal conrol range compensaion funcion is implemened and show s no burs operaion unil 5% load a high line. 5. ZeroCurren Deecion: Zerocurren deecion (ZCD) generaes he urnon signal of he MOSFET when he boos inducor curren reaches zero using an auxiliary w inding coupled w ih he inducor. When he pow er sw ich urns on, negaive volage is induced a he auxiliary w inding due o he opposie w inding direcion (see Equaion 1). Posiive volage is induced (see Equaion 2) w hen he pow er swich urns off. T V AUX AUX VAC TIND T V AUX AUX VPFCOUT VAC (2) TIND w here: V AUX is he auxiliary w inding volage; T IND is boos inducor urns; T IND auxiliary w inding urns; V AC is inpu volage for PFC converer; and V OUT_PFC is oupu volage from he PFC converer. (1) V INV (=V PFCOUT ) 2.500V 2.240V 2.051V VIN PFC PFC Inducor Aux Winding VCC VOUT PFC RZCD Negaive Clamp Circui V RDY ZCD 5 VSTART VSTOP 5V V CC PFC operaion V INV (=V PFCOUT ) 2.500V 2.240V 2.051V Figure 26. V RDY Tw o Cases of RDY Triggered LOW CZCD opional Posiive Clamp Circui THD opimized Sawooh Generaor Figure 27. VTH(ZCD) S Resar Timer Circui Near ZCD R Q Q fmax limi gae driver Because aux iliary w inding volage can sw ing from negaiv e o posiive volage, he inernal bloc k in ZCD pin has boh pos iiv e and negaive volage c lamping circuis. When he auxiliary volage is negaive, an inernal circui clamps he negaiv e volage a he ZCD pin around 0.65 V by sourcing curren o he serial resisor bew een he ZCD pin and he auxiliary w inding. When he auxiliary volage is higher han 6.5 V, curren is sinked hrough a resisor from he auxiliary w inding o he ZCD pin. 12

13 ISW IMOSFET VAUX & VZCD VAUX IDIODE VZCD Figure 28. VACIN 6.2V 0.65V Auxiliary Volage Depends on MOSFET Sw iching The aux iliary w inding volage is used o check he boos inducor curren zero insance. When boos inducor curren becomes zero, here is a resonance bew een boos inducor and all capaciors a he MOSFET drain pin: inc luding COSS of he MOSFET; an exernal capacior a he DS pin o reduce he volage rising and falling slope of he MOSFET; a parasiic capacior a inducor; and so on o improve performance. Resonaed volage is refleced o he auxiliary w inding and can be used for deecing zero curren of boos inducor and valley posiion of MOSFET volage sress. For valley deecion, a minor delay by he resisor and capacior is needed. A capacior increases he noise immuniy a he ZCD pin. If ZCD volage is higher han 1.5 V, an inernal ZCD comparaor oupu becomes HIGH and LOW w hen he ZCD goes below 1.4 V. A he falling edge of comparaor oupu, inernal logic urns on he MOSFET V DS VOUT VIN VCC RESTART 150 s MOSFET gae ZCD afer COMPARATOR Figure 30. Resar Timer a Sarup Because he MOSFET urnon depends on he ZCD inpu, sw iching frequency may increase o higher han several megaherz due o he misriggering or noise on he nearby ZCD pin. If he sw iching frequency is higher han needed for criical conducion mode (CRM), operaion mode shifs o coninuous conducion mode (CCM). In CCM, unlike CRM w here he boos inducor curren is rese o zero a he nex sw ich on; inducor curren builds up a every sw iching cycle and can be raised o very high curren ha exceeds he curren raing of he pow er sw ich or diode. This can seriously damage he pow er sw ich. To avoid his, maximum sw iching frequency limiaion is embedded. If ZCD signal is applied again w ihin 3.3 μs afer he previous rising edge of gae signal, his signal is ignored inernally and FA N7930C w ais for anoher ZCD signal. This slighly degrades he pow er facor performance a ligh load and high inpu volage. VOUT PFC VIN ZCD afer COMPARATOR Ignores ZCD noise VOUT PFC VIN VIN MOSFET Gae Error occurs! I INDUCTOR Max. fsw Limi V ZCD IMOSFET IDIODE Figure 31. Inhibi Region Maximum Sw iching Frequency Limi Operaion MOSFET gae 1.5V 1.4V 150ns Delay 6. Conrol: The scaled oupu is compared w ih he inernal reference volage and sinking or sourcing curren is generaed from he COMP pin by he ransconducance amplifier. The error amplifier oupu is compared w ih he inernal saw ooh w aveform o give proper urnon ime based on he conroller. ON ON Figure 29. Auxiliary Volage Threshold When no ZCD signal is available, he PFC conroller canno urn on he MOSFET, so he conroller chec ks every swiching off ime and forces MOSFET urn on when he off ime is longer han 150 μs. This resar imer riggers MOSFET urnon a sarup and may be used a he inpu volage zerocross period. 13

14 C2 V OUT PFC INV COMP R1 C1 1 3 THDOpimized 1V Sawooh Generaor Sawooh MOSFET Off Figure V VREF Sair Sep Clamp Circui Conrol Circui Unlike a convenional volagemode PWM conroller, FA N7930C urns on he MOSFET a he falling edge of ZCD signal. The ON insan is deermined by he exernal signal and he urnon ime lass unil he error amplifier oupu (V COMP) and saw ooh w aveform mee. When load is heavy, oupu volage decreases, scaled oupu decreases, COMP volage increases o compensae low oupu, urnon ime lenghens o give more inducor urnon ime, and increased inducor curren raises he oupu volage. This is how a PFC negaive feedback conroller regulaes oupu. The maximum of V COMP is limied o 6.5 V, w hich dicaes he max imum urnon ime. Sw iching sops w hen VCOMP is low er han 1.0 V. For he ransconducance error amplifier side, gain changes based on differenial inpu. When he error is large, gain is large o suppress he oupu dip or peak quickly. When he error is small, low gain is used o improve pow er facor performance. I COMP Sourcing Sinking Powering 250 mho 2.4V 115 mho Figure V 2.6V Braking Gain Characerisic 7. SofSar: When V CC reaches V START, he inernal reference volage is increased like a sair sep for 5 ms. As a resul, V COMP is also raised gradually and MOSFET urnon ime increases smoohly. This reduces volage and curren sress on he pow er sw ich during sarup. VCC VSTART=12V ZCD afer COMPARATOR V COMP & Sawooh VREF SS 5ms VREF END =2.5V MOSFET gae V / s VINV=0.4V gm Figure 33. TurnOn Time Deerminaion The roles of PFC conroller are regulaing oupu volage and inpu curren shaping o increase pow er facor. Duy conrol based on he oupu volage should be fas enough o compensae oupu volage dip or overshoo. For he pow er facor, how ever, he conrol loop mus no reac o he flucuaing A C inpu volage. These w o requiremens conflic; herefore, w hen designing a feedback loop, he feedbac k loop should be leas en imes slow er han AC line frequency. Tha slow response is made by C1 a he compensaor. R1 makes gain boos around operaion region and C2 aenuaes gain a higher frequency. Boos gain by R1 helps raise he response ime and improves phase margin. Gain Figure 34. C1 Inegraor R1 Proporional gain HighFrequency Noise Filer C2 Freq. Compensaors Gain Curve 14 ISOURCE COMP (VREF SS VINV) gm=isource COMP VCOMP ISOURCE COMP RCOMP=VCOMP Figure 36. SofSar Sequence 8. Sarup w ihou Overshoo: Feedback conrol speed of PFC is quie slow. Due o he slow response, here is a gap bew een oupu volage and feedback conrol. Tha is w hy overvolage proecion (OV P) is criical a he PFC conroller and volage dip caused by fas load changes from ligh o heavy is diminished by a bulk capacior. OV P is riggered during sarup phase. Operaion on and off by OV P a sarup may cause audible noise and can increase volage sress a sarup,

15 which is normally higher han in normal operaion. This operaion is improved w hen sofsar ime is very long. How ever, oo much sarup ime enlarges he oupu volage building ime a ligh load. FA N7930C has overshoo proecion a sarup. During sarup, he feedback loop is conrolled by an inernal proporional gain conroller and, w hen he oupu volage reaches he raed value, i sw iches o an exernal compensaor afer a ransiion ime of 30 ms. This inernal proporional gain conroller eliminaes overshoo a sarup and an exernal convenional compensaor akes over successfully aferw ard. V OUT V COMP Sarup Overshoo Inernal Conroller Convenional Conroller Sarup Overshoo Conrol Conrol Transiion Depends on Load I IN I INDUCTOR V ZCD MOSFET gae Figure 38. I IN I INDUCTOR 1.4V IMOSFET 150ns ON 1.5V IDIODE INEGATIVE ON Inpu and Oupu Curren Near Inpu Volage Peak Figure 37. Sarup w ihou Overshoo V ZCD INEGATIVE 9. THD Opimizaion: Toal Harmonic Disorion (THD) is he facor ha dicaes how closely inpu curren shape maches sinusoidal form. The urnon ime of he PFC conroller is almos consan over one A C line period due o he exremely low feedback conrol response. The urnoff ime is deermined by he curren decrease slope of he boos inducor made by he inpu volage and oupu volage. Once inducor curren becomes zero, resonance bew een COSS and he boos inducor makes oscillaing w aveforms a he drain pin and auxiliary w inding. By checking he aux iliary w inding volage hrough he ZCD pin, he conroller can check he zero curren of boos inducor. A he same ime, a minor delay is insered o deermine he valley posiion of drain volage. The inpu and oupu volage difference is a is maximum a he zero cross poin of AC inpu volage. The curren decrease slope is seep near he zero cross region and more negaive inducor curren flow s during a drain volage valley deecion ime. Such a negaive inducor curren cancels dow n he posiive curren flow s and inpu curren becomes zero, called zerocross disorion in PFC. 1.5V MOSFET gae ON Figure V 150ns ON ON ON Inpu and Oupu Curren Near Inpu Volage Peak Zero Cross To improve his, lenghened urnon ime near he zero cross region is a w ellknow n echnique, hough he mehod may vary and may be proprieary. FA N7930C opimizes his by sourcing curren hrough he ZCD pin. Auxiliary w inding volage becomes negaive w hen he MOSFET urns on and is proporional o inpu volage. The negaive clamping circui of ZCD oupus he curren o mainain he ZCD volage a a fixed value. The sourcing curren from he ZCD is direcly proporional o he inpu volage. Some porion of his curren is applied o he inernal saw ooh generaor, ogeher w ih a fixedcurren source. Theoreically, he fixedcurren source and he capacior a saw ooh generaor deermine he maximum urnon ime w hen no curren is sourcing a ZCD c lamp circui and available urnon ime ges shorer proporional o he ZCD sourcing curren. 15

16 R ZCD V ZCD ON ZCD 5 V AUX Figure 40. THD Opimizer rese N 1 VREF Vcc IMOT CMOT ZeroCurren Deec Sawooh Generaor Circui of THD Opimizer ON is ypically consan over 1 AC line frequency, bu ON is changed by ZCD volage. VOUT VIN VAUX MOSFET gae VCOMP IDS V OUT V IN Figure 42. Though V IN is eliminaed, operaion of conroller is normal due o he large bypass capacior. fmin DMAX High drain curren! Wihou V INAbsen Circui Though V IN is eliminaed, operaion of conroller is normal due o he large bypass capacior. ON no shorer ON ge shorer V AUX Figure 41. V ZCD a FET on Effec of THD Opimizer By THD opimizer, urnon ime over one A C line period is proporionally changed, depending on inpu volage. Near zero cross, lenghened urnon ime improves THD performance. 10. VINAbsen Deecion: To save pow er loss caused by inpu volage sensing resisors and o opimize THD, he FA N7930C omis AC inpu volage deecion. Therefore, no informaion abou AC inpu is available from he inernal conroller. In many cases, he V CC of PFC conroller is supplied by an independen pow er source, like sandby pow er. In his scheme, some mis mach may ex is. For example, w hen he elecric pow er is suddenly inerruped during w o or hree AC line periods; VCC is sill live during ha ime, bu oupu volage drops because here is no inpu pow er source. Consequenly, he conrol loop ries o compensae for he oupu volage drop and V COMP reaches is maximum. This lass unil A C inpu volage is live again. When AC inpu volage is live again, high V COMP allows high sw iching curren and more sress is pu on he MOSFET and diode. To proec agains his, FA N7930C checks if he inpu A C volage ex iss. If inpu does no exis, sofsar is rese and w ais unil AC inpu is live again. Sofsar manages he urnon ime for smooh operaion w hen i deecs AC inpu is applied again and applies less volage and curren sress on sarup. MOSFET gae NewV COMP I DS D MAX f MIN Figure 43. f MIN D MIN V IN Absence Deeced Smooh SofSar Wih V INAbsen Circui 11. Curren Sense: The MOSFET curren is sensed using an exernal sensing resisor for overcurren proecion. If he CS pin volage is higher han 0.8 V, he overcurren proecion comparaor generaes a proecion signal. An inernal RC filer of 40 kω and 8 pf is included o filer sw iching noise. 12. Gae Driver Oupu: FAN7930C conains a single oempole oupu sage designed for a direc drive of he pow er MOSFET. The drive oupu is capable of up o 500 / 800 ma peak curren w ih a ypical rise and fall ime of 50 ns w ih 1 nf load. The oupu volage is clamped o 13 V o proec he MOSFET gae even if he V CC volage is higher han 13 V. 16

17 PCB Layou Guide PFC block normally handles high sw iching curren and he volage low energy signal pah can be affeced by he high energy pah. Cauious PCB layou is mandaory for sable operaion. 1. The gae drive pah should be as shor as possible. The closedloop ha sars from he gae driver, MOSFET gae, and MOSFET source o ground of PFC conroller should be as close as possible. This is also crossing poin bew een pow er ground and signal ground. Pow er ground pah from he bridge diode o he oupu bulk capacior should be shor and w ide. The sharing posiion bew een pow er ground and signal ground should be only a one posiion o avoid ground loop noise. Signal pah of he PFC conroller should be shor and w ide for exernal componens o conac. 2. The PFC oupu volage sensing resisor is normally high o reduce curren consumpion. This pah can be affeced by exernal noise. To reduce noise poenial a he INV pin, a shorer pah for oupu sensing is recommended. If a shorer pah is no possible, place some dividing resisors bew een PFC oupu and he INV pin closer o he INV pin is beer. Relaive high volage close o he INV pin can be helpful. 3. The ZCD pah is recommended close o auxiliary w inding from boos inducor and o he ZCD pin. If ha is difficul, place a s mall capac ior (below 50 pf) o reduce noise. 4. The sw iching curren sense pah should no share w ih anoher pah o avoid inerference. Some addiional componens may be needed o reduce he noise level applied o he CS pin. 5. A sabilizing capacior for V CC is recommended as close as possible o he VCC and ground pins. If i is difficul, place he SMD capacior as c lose o he corresponding pins as possible. Figure 44. Recommended PCB Layou 17

18 Typical Applicaion Circui Applicaion Device Inpu Volage Range Raed Oupu Power Oupu Volage (Maximum Curren) LCD TV Pow er Supply FAN7930C VAC 195 W 390 V (0.5 A) Feaures Average efficiency of 25%, 50%, 75%, and 100% load condiions is higher han 95% a universal inpu. Pow er facor a raed load is higher han 0.98 a universal inpu. Toal Harmonic Disorion (THD) a raed load is low er han 15% a universal inpu. Key Design Noes When auxiliary VCC supply is no available, VCC pow er can be supplied hrough Zero Curren Deec (ZCD) w inding. The pow er consumpion of R103 is quie high, so is pow er raing needs checking. Because he inpu bias curren of INV pin is almos zero, oupu volage sensing resisors (R112~R115) should be as high as possible. How ever, oohigh resisance makes he node suscepible o noise. Resisor values need o srike a balance bew een pow er consumpion and noise immuniy. Quick charge diode (D106) can be eliminaed if oupu diode inrush curren capabiliy is sufficien. Even w ihou D106, sysem operaion is normal due o he conroller s highly reliable proecion feaures. Schemaic Opional D V 3A 194µH, 39:5 D V 8A DC OUTPUT BD101, 600V,15A C102, 680nF C114,2.2n F C115,2.2n F R101,1M J TH101,5D15 LF101,23mH C101, 220nF C1030,68m F,630Vdc C107,33m F C105, 100nF R102, 330k R104, 30k D101,1N474 6 R107,10k C108, 220nF R103, 10k,1W C104, 12nF D102, UF VCC Ou 5 3 ZCD CS 2 Comp INV RDY GND C109,47n F VCC for anoher power sage 6 VAUX R110,10k LP101,EER3019N R R D103,1N414 8 D104,1N414 8 C112,470p F Q101 FCPF 20N60 R , 5W C110,1n F R M R M R M R115 75k C mF, 450V ZNR101,10D471 FS101, 250V,5 A Circui for VCC. If exernal VCC is used, his circui is no needed. Circui for VCC for anoher power sage hus componens srucure and values may vary. Figure 45. Demonsraion Circui 18

19 Transformer EER3019N 9,10 1,2 Naux N P 6,7 N 3,4 p Naux 9,10 6,7 1,2 3,4 Figure 46. Transformer Schemaic Diagram Winding Specificaion Posiion No Pin (S F) Wire Turns Winding Mehod Boom Np 3, 4 1, 2 0.1φ Solenoid Winding Insulaion: Polyeser Tape = 0.05mm, 3 Layers Top N AUX 9,10 6,7 0.3φ 5 Solenoid Winding Insulaion: Polyeser Tape = 0.05 mm, 4 Layers Elecrical Characerisics Pin Specificaion Remark Inducance 3, 4 1, H ±5% 100 khz, 1 V Core & Bobbin Core: EER3019, Samhw a (PL7) (Ae=137.0mm 2 ) Bobbin: EER

20 Bill of Maerials Par # Value Noe Par # Value Noe Resisor Sw ich R101 1 MΩ 1W Q101 FCPF20N60 20 A, 600 V, SuperFET R kω 1/2W Diode R kω 1W D101 1N W, 18 V, Zener Diode R kω 1/4W D102 UF A, 400 V Glass Passivaed HighEfficiency Recifier R kω 1/4W D103 1N A, 100 V SmallSignal Diode R kω 1/4W D104 1N A, 100 V SmallSignal Diode R kω 1/4W D105 R kω 1/4W D106 R kω 5W R112, 113, A, 600 V, GeneralPurpose Recifier 3 A, 600 V, GeneralPurpose Recifier 3.9 kω 1/4W IC101 FAN7930C CRM PFC Conroller R kω 1/4W Capacior C nf / 275 V AC Box Capacior FS101 5 A / 250 V Fuse C nf / 275 V AC Box Capacior NTC C µf / 630 V Box Capacior TH101 5D15 C nf / 50 V Ceramic Capacior Bridge Diode C nf / 50 V SMD (1206) BD A, 600 V C µf / 50 V Elecrolyic Capacior C nf / 50 V Ceramic Capacior LF mh Line Filer C nf / 50 V Ceramic Capacior Transformer C110 1 nf / 50 V Ceramic Capacior T1 EER3019 Ae=137.0 mm 2 C nf / 50 V Ceramic Capacior ZNR C µf / 450 V Elecrolyic Capacior C nf / 450 V Box Capacior C nf / 450 V Box Capacior ZNR101 10D471 20

21 Physical Dimensions PIN ONE INDICATOR (0.33) 1.75 MAX R R DETAIL A SCALE: 2: (1.04) A C B C B A x 45 GAGE PLANE 0.36 SEATING PLANE LAND PATTERN RECOMMENDATION SEE DETAIL A OPTION A BEVEL EDGE OPTION B NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED 5.60 A) THIS PACKAGE CONFORMS TO JEDEC MS012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X1758M. E) DRAWING FILENAME: M08Arev14 F) FAIRCHILD SEMICONDUCTOR. Figure 47. 8Lead, Small Ouline Package (SOP) Package drawings are provided as a service o cusomers considering ON Semiconducor componens. Drawings may change in any manner wihou noice. Please noe he revision and/or dae on he drawing and conac a ON Semiconducor represenaive o verify or obain he mos recen revision. Package specificaions do no expand he erms of ON Semiconducor s worldwide erms and condiions, specifically he warrany herein, which covers ON Semiconducor producs. 21

22 ON Semiconducor and he ON Semiconducor logo are rademarks of Semiconducor Componens Indusries, LLC dba ON Semiconducor or is subsidiaries in he Unied Saes and/or oher counries. ON Semiconducor owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of ON Semiconducor s produc/paen coverage may be accessed a /sie/pdf/paenmarking.pdf. ON Semiconducor reserves he righ o make changes wihou furher noice o any producs herein. ON Semiconducor makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does ON Semiconducor assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Buyer is responsible for is producs and applicaions using ON Semiconducor producs, including compliance wih all laws, regulaions and safey requiremens or sandards, regardless of any suppor or applicaions informaion provided by ON Semiconducor. Typical parameers which may be provided in ON Semiconducor daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. ON Semiconducor does no convey any license under is paen righs nor he righs of ohers. ON Semiconducor producs are no designed, inended, or auhorized for use as a criical componen in life suppor sysems or any FDA Class 3 medical devices or medical devices wih a same or similar classificaion in a foreign jurisdicion or any devices inended for implanaion in he human body. Should Buyer purchase or use ON Semiconducor producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold ON Semiconducor and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha ON Semiconducor was negligen regarding he design or manufacure of he par. ON Semiconducor is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor E. 32nd Pkwy, Aurora, Colorado USA Phone: or Toll Free USA/Canada Fax : or Toll Free USA/Canada orderli@onsemi.com N. Amer ic an Technical Suppor: Toll Free USA/Canada. Eur ope, Middle Eas and Afr ica Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semic onducor Websie: Or der Lieraure: hp:///orderli For addiional informaion, please conac your local Sales Represenaive 22