ISSCC-2004: Latest Trends in Technologies and Circuits for Wireless Communications

Transcription

1 ISSCC-2004: Latest Trends in Technologies and Circuits for Wireless Communications 18. March 2004

2 Outline ISSCC-2004 summary of major highlights AD/DA-Converters Wireless, RF and Technology-Directions Digital and Signal-Processing ISSCC-2004 (GIRAFE) Gigahertz Radio Front Ends Forum RF Power Amplifiers ISSCC-2004 (ATACC) Analog Telecom ASIC & Circuit Concepts Forum A/D D/A Building Blocks for Telecom Tranceiver Applications Comparison with current status and future developments at Infineon Circuits and technology (production process) trends Conclusions

3 AD/DA converters most significant results High-Speed A/D Converters bring 1 GSPS performance into the main stream 14-Bit D/A Converter pushes to 1.4GS/s, allowing direct synthesis of broadband/if signals Sigma-Delta Modulators extend signal bandwidths: 10MHZ to 12MHz More sophisticated calibration techniques enhance the accuracy of high resolution pipelined A/D converters A Digitally Enhanced 1.8V 15b 40MS/s CMOS Pipelined ADC [25.1] UC San Diego A 15-bit 20MS/s CMOS Pipelined ADC with Digital Background Calibration National Chiao-Tung University, Taiwan

4 Wireless, RF and Technology-Directions: most significant results Berkeley University Wireless Research Center explores basic elements for a 60GHz transceiver in standard low-cost 0.13µm CMOS IBM demonstrates direct-conversion transceiver circuits in 200GHz ft SiGe technology for 60GHz transmission Quad-band polar-loop transmitter provides 55% efficiency in GSM mode and 35% efficiency in EDGE mode Quad-Band GSM-GPRS Transmitter in 0.13µm CMOS A true single-chip Bluetooth IC with RF, baseband, memory and power-management functions Single-chip ISDB-T tuner for mobile cellular handsets. Ultrawideband amplifiers (3-10GHz) in SiGe and CMOS Oscillators and synthesizers above 10GHz

5 Digital and Signal-Processing: most significant results Integration of multiple independent processor cores on a single die New processors in 90nm technology Dynamic voltage and frequency control for power management Mixed body bias techniques for low-voltage operation A Highly-Integrated 3G CDMA2000 1X Cellular Baseband Chip With GSM/AMPS/GPS/Bluetooth Multimedia Capabilities and ZIF RF Support

6 ISSCC 2004: 16 pres. 90 nm CMOS Samsung Japan IBM Intel Infineon comm Intel comm TI comm

7 Mixed-signal/Ultra High-speed Digital

8 Active Device Comparison Matrix

9 Entwicklungsfortschritte ft & fmax bei Silizium Bipolar und CMOS als Enabler für neue Consumer Anwendungen Ft & fmax (GHz)

10 Infineon s HF BiCMOS Technologies and Applications

11 98 GHz Voltage Controlled Oscillator in SiGe:C Technology

12 Platform CMOS Technology Roadmap C10DE (180nm) (logic based) C10DD (170nm) (DRAM based) C11 (130nm) C11 FLASH C11 FLASH - R L90 (90nm) L65 (65nm) L45 (45nm) L32 (32nm)

13 $100,000,000,000 Design Cost of SOC-LP PDA Driver SOC Design Cost Model $10,000,000,000 $15,066,373 $342,417,579 $1,000,000,000 Total Design Cost (log scale) In-House P&R Tall Thin Engineer Small Block Reuse Large Block Reuse IC Implementation tools Intelligent Testbench ES Level Methodology $100,000,000 $10,000,000 RTL Methodology Only With all Future Improvements Year

14 IP Mix-and-Match Infineon IP Infineon IP Customer IP FIB FIB FIB Scheduler Switching Fabric FIB FIB FIB Customer IP 3 rd Party IP Open Arch. ISA Core PE Processing Element FIB Fabric Interface Block

15 Circuit techniques AD-Converter concepts and performance requirements Definitions D/A Converter Building blocks QAP SAM 15 Sigma Delta DECT HDSL2 Pipelined 2nd order SD ADSL N-step 13 Multi 4bit ADSL CT-SD Dig_ADC Audo1 SAR R1 VDSL 11 Pipelined N-step CT-SD Pipelined MC ADC SAR non bin SAR SAR R2 Folding 2step C10 9 SCTV100SNORC ABACUS MC ADC ADC SAR 2step DECT PIP 4SCTV100 Folding QPSK flash 7 M2TVTpro G1763 Folding Flash_CAL M676 5 Flash k k k M M M Bandwidth/f3dB G

16 Successive Approximation Non Binary SA-Converter Definitions D/A Converter Building blocks A/D Converters non binary SAR Other applications: Low Power Gatelength:0.12µm m 0.065mm 2 Gatelength 0.08µm m 0.032mm 2 Low Power version: 512*oversampling 12bit Analog Input: 0-8KHz0 1.2Volt 0.5mW 84dB SNR 0.065mm 2

17 Chip area / power consumption comparison BiCMOS CMOS BiCMOS (0.35µm) CMOS (0.13µm) Power consumption 100% 40% Chip area 100% 50% RF/Analog Adders: Add MIM Cap Add thick dielectric/metal Add MOS varactor Add Models and Device Level Design Kit

18 Supply Voltage Trends in Transceivers and PAs V supply 5.5V 5V 3.3V 3.3V 3.5V What s going to happen here? 2.5V 2.5V Power Amplifier Radio / Transceiver Baseband / Others 1.8V 1.8V 1.2V 1.3V 1.0V t There is a growing disparity between the supply of the PA and rest of the system, due to process scaling in silicon ICs A lower voltage PA is an inevitability and just a matter of time Battery technology developments

19 Personal Trusted Device - PTD There will be a strong demand for "Personal Trusted Devices" (PTD) which are providing Platform Integrity (e.g. TCPA* compliance, ) Communication Security Bulk encryption Security protocols (e.g. IP Sec, IEEE 802.1x, SSL/TLS, ) Generic Security Platform for E-Commerce applications Downloading of signed content (e.g. Java applications) Security-support for applications through API extensions Secure log-in to PC / network DRM (Digital Right Management) Secure Security founded on secure silicon, the MobileCrypt* will be the answer. * TCPA = Trusted Computing Platfrom Alliance founded by Compaq, HP, IBM, Intel, and Microsoft ** TCPA compliant Trusted Platform Module for Mobile Devices

20 xdsl Fiber Optics Fiber-to-the-home Optical Networking LAN/WAN/MAN Car Electronics: Powertrain Safety Mgmt. Comfort Mgmt. Infotainment Power Conversion: Power Supplies Drives Secure Mobile Applications Communications Payment Computing Entertainment Wide / Local / Personal Area Wireless, GPS SDR + DDR DRAM Mobile RAM CellularRAM Graphics RAM RLDRAM MRAM/FRAM Flash Infineon's Target Applications Infineon's Core Competencies Broadband / Access Secure Mobile Solutions Automotive & Industrial Memory

21 Infineon World-wide R&D Network in Europe Ulm RF ICs for GSM Dublin Security Software Duisburg Automotive Solutions Düsseldorf DataCom Cordless Bluetooth Base Band RF Devices Warstein High Power Salzgitter Mobile Phones Software Horten Tire pressure sensors Aalborg Wireless Systems Kista Wireless syst. Communic. Linkoeping Wireless Hamburg Bristol High Perform. Cores Hannover Wireless Karlsruhe Emulators for Microcontr. Corbeil- Essonnes Nuremberg GSM software Porto Memories Memory Security Technology Design Flow Automotive Power Wireless Discretes IP-Cores Mixed Signal Braunschweig Berlin Fiber Optics Dresden DRAM fabs & cell / Flash Chemnitz Wireless Applications Erlangen Memories Augsburg Security Software Sophia Antipolis Libraries Wireless ASICs Munich Mixed Signal Cores Autom. Power Regensburg Interconnect. Packaging Padova Automotive & Indust. Power Graz Security Autom. Sense&Control RFID Solutions Villach Mixed Signal Cores Telecom Linz UMTS/GSM/ GPRS/EDGE Wireless Contr. Vienna UMTS Baseb. DSP Firmware

22 Infineon World-wide R&D Network (excluding Europe) Longmont ICs / Opto for Disk Drives Princeton RF ICs For CDMA Burlington DRAM Product dev. Netanya Telecom. Flash Memory Xi'an Super Design Fab Tempe RF Power Devices Shanghai Wireless Systems Tokyo Software Development for Mobile phones San Jose Comp. Periph. Datacom 32bit TriCore Taipei Broadband CPE System development Morgan Hill RF Power Transistors Cary DRAM Product dev. East Fishkill Logic 130nm MRAM 90nm Bangalore Software Development Singapore 8/32 bit µc Telecom Network & Computer Storage

23 CONCLUSIONS Very interesting, but no revolutionary new developments were presented at ISSCC-2004 Evolutionary further development Enabler is Technology (Mr. Moore) it is all about technology System space is naturally growing in importance SoC Future innovations in: Technology, Circuits (Analog, RF, Digital, SoC) and Methodology are very important

24 Back-up

25 Highly-integrated a/b/g Transceivers A Single-Chip CMOS Transceiver for a/b/g WLANs [5.2] Spirea A Dual-Band a/b/g Radio in 0.18µm CMOS [5.3] NewLogic, France A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE a/b/g CMOS [5.4] Atheros Communications, IRF Semiconductor and Stanford University PRESENT STATE OF THE ART (THE PROBLEM) The growth in wireless LAN connectivity is enabled by multi-mode multi-band highperformance wireless transceivers. Existing transceivers consist of two or more ICs with numerous off-chip components. NOVEL CONTRIBUTIONS The first fully-integrated a/b/g transceivers [5.2, 5.3, 5.4] Increasing levels of integration, including integrated synthesizer loop filter, and improved performance [5.2, 5.3, 5.4] CURRENT AND PROJECTED SIGNIFICANCE Highly-integrated low-cost multi-band multi-mode transceivers have immediate significance, enabling high-volume low-cost WLANs [5.2, 5.3, 5.4] Multi-mode will enable seamless universal connectivity [5.2, 5.3, 5.4]

26 Cellular Systems and Building Blocks A 1.5V 28mA Fully-Integrated Fast-Locking Quad-Band GSM-GPRS Transmitter with Digital Auto-Calibration in 0.13µm CMOS [10.4] University of Washington and Texas Instruments, Inc. Quad-Band GSM/GPRS/EDGE Polar Loop Transmitter [10.3] Skyworks PRESENT STATE OF THE ART (THE PROBLEM) Low efficiency in EDGE transmit mode External power-amplifier filtering and many external components Separate Transmitters for each GSM band NOVEL CONTRIBUTIONS Quad-band polar-loop transmitter provides 55% efficiency in GSM mode and 35% efficiency in EDGE mode [10.3] Quad-band GSM transmitter with no external components, and 8X less power dissipation [10.4] Single VCO covers the four GSM transmit frequencies [10.3] CURRENT AND PROJECTED SIGNIFICANCE Extended talk time for cellular phones [10.3] Reduced size for cellular phones [10.4]

27 Wireless Consumer ICs Break New Ground in Power Consumption and Size A Discrete-Time Bluetooth Receiver in a 0.13µm Digital CMOS Process [15.1] Texas Instruments All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13µm CMOS [15.3] Texas Instruments and University of Texas at Dallas A Digital Terrestrial Television (ISDB-T) Tuner for Mobile Applications [15.6] Sharp PRESENT STATE OF THE ART (THE PROBLEM) Hand-held devices are incorporating more functions, while becoming increasingly smaller. New functions that are being integrated into personal digital assistants (PDAs) and cellular-telephone handsets include short-range wireless connectivity for synchronizing portable-device data with the desktop as in electronic address books, as well as television reception capability for portable television viewing. Thus, it is important to find ways to build chips with ever-higher integration, with lower power consumption, and with fewer external components. Current chips for these portable applications use less-integrated architectures with many discrete components, all based on traditional RF and analog design methods.

28 Wireless Consumer ICs Break New Ground in Power Consumption and Size (continued) NOVEL CONTRIBUTIONS A true single chip Bluetooth IC with RF, baseband, memory and power management functions. [15.1, 15.3] The Bluetooth IC departs from traditional RF design methods by using discrete time sampling and all-digital methods previously reserved for digital chips and much lower frequency analog chips. [15.1, 15.3] Conventional TV tuners are large, high power metal tin can modules built from hundreds of discrete components. This single-chip TV tuner designed for the new Japanese digital TV system, is much more highly integrated than the old tin cans. So it can be much smaller in size. It also consumes much less power than traditional tuner modules. [15.6] CURRENT AND PROJECTED SIGNIFICANCE Cellphones and other very small handheld devices will be able to exchange information over a short range while using very little power and having ultra-long battery life. [15.1, 15.3] Cellphones and other very small handheld devices will be able to receive television signals including new interactive services combining the best of broadcast television with the interconnectedness of the internet while still maintaining very long battery lifetimes. [15.6]

29 RF Potpourri A Fully-Integrated 13GHz Σ Fractional-N PLL in 0.13µm CMOS [21.5] Infineon Technologies A 17.1 to 17.3GHz Image-Reject Down Converter with Phase-Tunable LO Using 3x Subharmonic Injection Locking [21.6] University of Toronto, Delft University, IBM Microelectronics PRESENT STATE OF THE ART (THE PROBLEM) Most current WLAN systems operate in 2.4GHz and 5GHz bands Assumption of future spectrum constraints motivates exploration of WLAN systems in the 17GHz ISM band NOVEL CONTRIBUTIONS Fully integrated 13GHz, 60mW PLL in CMOS [21.5] Image-rejecting SiGe BiCMOS 17GHz, 62.5mW downconverter with subharmoniclocked LO [21.6] CURRENT AND PROJECTED SIGNIFICANCE Performance and integration achieved with conventional silicon technologies assures continuing improvements in size, cost, power consumption, accessible carrier frequencies, and data rates [21.5, 21.6]

30 Integration of Channel Filter into Delta-Sigma Modulators A 2mW 89dB DR Continuous-Time Sigma-Delta ADC with Increased Wide-Band Interference Immunity [4.8] Philips Research, The Netherlands and Unversidad de Sevilla, Spain PRESENT STATE OF THE ART (THE PROBLEM) To avoid overload of ADC in the presence of an interferer a channel filter is needed An external filter has noise and distortion implications insufficient filtering can allow a strong interferer to use up all the dynamic range of the converter NOVEL CONTRIBUTIONS Filters integrated inside the feedback loop [4.8] New architecture that merges receiver functions [4.8] CURRENT AND PROJECTED SIGNIFICANCE Filter incorporation relieves noise and distortion concerns, and allows the presence of large interference signals that exceed the full-scale of the ADC [4.8] Enhances the usable dynamic range of the converter in real world applications [4.8] Development represents part of the trend to reduce circuit complexity in communication receivers [4.8]

31 High-Speed A/D Converters A 1.8V 1.6GS/s 8b Self-Calibrating Folding ADC with 7.26 Effective Bits at Nyquist [14.1] National Semiconductor, Germany An 8b 600MS/s 200mW CMOS Folding ADC using Amplifier Preset [14.2] Philips, The Netherlands PRESENT STATE OF THE ART Previous individual 8-bit ADC designs have been limited to 250MS/s Interleaved designs have achieved higher speeds with extensive externalcalibration hardware. NOVEL CONTRIBUTIONS Designs extend the state-of-the art by a factor of 2 or 3 in sampling rate [14.1, 14.2] Time interleaving by a factor of 2, without requiring calibration of gain or timing [14.1] Best-reported accuracy for a CMOS ADC above 1GS/s [14.1] CURRENT AND PROJECTED SIGNIFICANCE Increased pixel frequency and refresh rates in video processing systems [14.2] Faster communication systems [14.1, 14.2]

32 Digital-to-Analog Converters A 14b 1.4GS/s 3V CMOS DAC for Multi-Carrier Applications [20.1] Analog Devices PRESENT STATE OF THE ART (THE PROBLEM) Evolving digital-radio architectures require synthesis of very wideband signals and/or direct synthesis of signals at IF frequencies of 250MHz and above. Advanced modulation schemes and multi-carrier radio platforms demand dynamic range in excess of 12 bits NOVEL CONTRIBUTIONS Circuit techniques applied to the DAC switches realize both speed and dynamic range at reasonable power cost in conventional CMOS process technology [20.1] CURRENT AND PROJECTED SIGNIFICANCE Enables direct synthesis of multi-carrier signals at higher IF frequencies [20.1] Another important step towards software radio [20.1]

33 High Resolution Nyquist ADCs A Digitally Enhanced 1.8V 15b 40MS/s CMOS Pipelined ADC [25.1] UC San Diego A 15-bit 20MS/s CMOS Pipelined ADC with Digital Background Calibration [25.2] National Chiao-Tung University, Taiwan PRESENT STATE OF THE ART (THE PROBLEM) High-performance broadband and wireless communication systems demand high-speed high-resolution ADCs. Calibration techniques for compensating both the static and dynamic errors are critical to realizing the best-possible performance. NOVEL CONTRIBUTIONS Sophisticated background-calibration schemes that continuously measure and correct static and dynamic errors, set new benchmarks in SNR and SFDR for Nyquist converters at 10 to 50MS/s conversion rate [25.1, 25.2] CURRENT AND PROJECTED SIGNIFICANCE Implementations in 0.18µm CMOS is common [25.1, 25.2, 25.4,25.7] Implementation in 0.13µm CMOS of low-voltage and low- power ADCs extends dataacquisition techniques available for state-of-the- art SoCs [25.6]

34 ISSCC 2004: GIGAHERTZ RADIO FRONT ENDS FORUM (GIRAFE) RF Power Amplfiers Power Amplifiers in Cellular Phones Rob McMorrow and Shuyun Zhang, Analog Devices RF Power Amplifiers Pieter Lok, Philips, The Netherlands Design strategies for fully integrated Bluetooth power amplifiers Koen Mertens and Michiel Steyaert, KU Leuven, Belgium Fully-Integrated Watt-Level CMOS Power Amplifiers: No Longer an Oxymoron Ali Hajimiri, Caltech SiGe/CMOS Power Amplifiers for Wireless Terminals Noriharu Suematsu, Mitsubishi, Japan Case Study: CMOS RF Power Amplifiers: Nonlinear, Linear, Lineariized David Su, Atheros

35 Most relevant technologies for PA Two key hurdles for PA Technology: Power Added Efficiency Robustness over operating conditions Most prevalent technologies for PA: AIGAs HBT InGaP HBT LDMOS PHEMT MESFET SiGe CMOS GaAs GaAs Silicon GaAs GaAs Silicon Silicon } 73 % Market Share 20 %

36 Trends in PA Technology Higher PAE Explore new process technologies E-PHEMT DHBT InP Cost Reduction Improve silicon technology SiGeBJT CMOS There is much more to PA module product than just a PA The module must be viewed as a system The level of integration is advancing at a rapid pace

37 ISSCC 2004: ATACC Forum Analog Telecom Asics & Circuit Concepts 25 years of A/D & D/A in Telecom Chang Zhong Yuan, IDT-Newave Technology, Shanghai, China Sigma-Delta A/D Converter Technology for Cellular Handsets Robert van Velthoven, Philips Eindhoven, The Netherlands A/D and D/A converters for Broadband on DSL and Cable Sumant Ranganathan, Broadcom, San Jose Challenges for Re-use and Design Efficiency in A/D & D/A Carlos Leme, Chipidea, Portugal A/D & D/A Converter Requirements and Implementation for W-CDMA Base Stations Manfred Punzenberger, Infineon, Villach, Austria Pipelined A/D Converters Steve Lewis, UC Davis, CA Impact of jitter and phase noise on converter performance in telecom Asad Abidi, UCLA, CA