IR1176 SYNCHRONOUS RECTIFIER DRIVER. Features. Product Summary

Transcription

1 Preliminary Data Sheet PD6085-C Features Provides constant and proper gate drive to power MOSFETs regardless of transformer output Minimizes loss due to power MOSFET body drain diode conduction Stand alone operation - no ties to primary side Schmitt trigger input with double pulse suppression allows operation in noisy environments High peak current drive capability - 4A High speed operation - 2MHz Adaptable to multiple topologies SYNCHRONOUS RECTIFIER DRIVER Product Summary Vdd IO+/- (peak) Fmax 5Vdc 4A/4A 2MHz Max lead time 500nsec IR76 Description The IR76 is a high speed CMOS controller designed to drive N-channel power MOSFETs used as synchronous rectifiers in high current, high frequency forward converters with output voltages equal or below 5VDC. Schmitt trigger inputs with double pulse suppression allow the controller to operate in noisy environments. The circuit does not require any ties to the primary side and derives its operating power directly from the secondary. The circuit functions by anticipating transformer output transitions, then turns the power MOSFETs on or off before the transitions of the transformer to minimize body drain diode conduction and reduce associated losses. Turn on/off lead time can be adjusted to accommodate a variety of power MOSFET sizes and circuit conditions. The IR76 also provides gate drive overlap/dead-time control via external components to further minimize diode conduction by nulling effects of secondary loop and device package inductance. Packages IR76S 20 Lead Surface Mount (SSOP-20) IR76SS 20 Lead SOIC (MS-03AC) IR76 20 Lead PDIP (MS-00AD)

2 IR76 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. Symbol Definition Min. Max. Units V dd Supply voltage 7 V DC I in Input clamp current +/- 0 ma DC P D Power dissipation (SSOP-20) 400 mw (SOIC) (PDIP) Rth JC Thermal resistance (SSOP-20) junction-to-case 28.5 (SOIC) junction-to-case 20 (PDIP) junction-to-case 28. Rth JA Thermal resistance (SSOP-20) junction-to-ambient 90.5 (SOIC) junction-to-ambient 45 (PDIP) junction-to-ambient 62.4 T J Junction temperature 50 T S Storage temperature T L Lead temperature (soldering, 0 seconds) 300 C/W C Recommended Operating Conditions Symbol Definition Min. Typ. Max. Units Vdd Supply voltage operating range 5 V DC T A Ambient temperature C Freq Operating frequency KHz Rbias Required bias resistor (+/- %) 34.0 KΩ UV Voltage at UVSET pin V DC Xin Maximum voltage at X and X2 inputs 5.6 V DC Cd/Cd2 Capacitance at pins DTIN and DTIN2 00 pf 2

3 IR76 Dynamic Electrical Characteristics Vdd=5V, T A = 25 o C, Rbias = 34.0K unless otherwise specified. Symbol Definition Min. Typ. Max. Units Vdd Supply voltage operating range V DC Iqdd Vdd quiescent current (x = x2 = 0V or 5V, Iout = 0) 4 5 A Freq Operating frequency KHz UVSET+ UVSET positive going threshold.0.4 V UVSET- UVSET negative going threshold 0.8. V Vxth+ X/X2 Input positive going threshold.4 V DC Vxth- X/X2 Input negative going threshold.0 V DC Tadv Externally adjustable lead time (advance) 500 nsec Td Externally adjustable dead-time for Q and Q2 20 nsec Isink Q,Q2 output sink current (Vdd=5.0V, 4 (peak) pulsed, 0 usec) Isource Q,Q2 output source current (Vdd=5.0V, 4 A (peak) pulsed, 0 usec) VOH Q, Q2 High level voltage (Iout = 20mA) Vdd V VOL Q, Q2 Low level voltage (Iout = 20mA) 0.0 tio Input to output delay (PLL bypassed, cross coupled 20 nsec mode) tr Gate turn-on rise time (C=000pf, Vdd=5V) 20 nsec tf Gate turn-off fall time (C=000pf, Vdd=5V) 20 nsec Vtr Cross-over voltage (Vdd=5Vdc, DTIN shorted to 2.5 V DC DTOUT, C=000pf) Fig. 3 Rbias Required bias resistor (%) 34.0 KΩ Vbias Voltage at Rbias pin.25 V DC Tjitter Phase-lock loop output jitter nsec Ichgpump Charge pump output current (at VFLTR pin) 50 µa DC Vchgpump Charge pump output voltage (at VFLTR pin) V DC Kvco_dc PLL Vco DC gain (per design) 62 KHz/ Volt 3

4 IR76 Lead Definitions and Assignments Symbol Description AVDD Q DTOUT DTIN RADV VFLTR RVCO X VDD Power V DC to MOSFET drivers Output - gate drive for Q power MOSFET Output - sets dead time for Q output - used with DTIN Input - sets dead time for Q - used with DTOUT Output - sets lead time (advance) for Q Output - PLL loop filter for Q output Output - sets PLL center frequency for Q output Input - transformer input for Q Power - +5 Vdc for internal logic UVSET Input - sets UVLO+ If this pin is pulled below.25vdc externally, then both Q and Q2 RBIAS AVSS X2 RVCO2 VFLTR2 RADV2 DTIN2 DTOUT2 VSS Q2 outputs will be at Vss (disabled) Output - connected to 34.0K +/- % resistor - sets operating current Ground for MOSFET driver supply (VDD) Input - transformer input for Q2 Output - sets PLL center frequency for Q2 output Output - PLL loop filter for Q2 Output - sets lead time (advance) for Q2 Input - sets dead time for Q2 - used with DTOUT2 Output - sets dead time for Q2 - used with DTIN2 Ground for logic supply (AVDD) Output - gate drive for Q2 power MOSFET *VDD Q DTOUT2 DTIN2 RADV VFLTRI RVCO X AVDD UVSET Q2 VSS DTOUT DTIN RADV2 VFLTR2 RVCO2 X2 AVSS RBIAS IR76S (SSOP-20) *VDD Q DTOUT2 DTIN2 RADV VFLTRI RVCO X AVDD UVSET Q2 VSS DTOUT DTIN RADV2 VFLTR2 RVCO2 X2 AVSS RBIAS IR76SS SOIC (wide body) 2 Q X 9 0 *VDD DTOUT2 DTIN2 RADV VFLTRI RVCO AVDD UVSET VSS DTOUT DTIN RADV2 VFLTR2 RVCO2 IR76 PDIP Q2 X2 AVSS RBIAS

5 IR76 Fig. Typical application circuit when supply Vout < 5.0 V DC Fig. 2 Typical application circuit when supply Vout = 5.0 V DC 5

6 IR76 Fig. 3 Gate drive characteristics and definitions Phase Lock Loop Design Equations: - Resistor to set VCO Ceter Frequency: Rvco (KΩ) = [E2 x Vchgpump(V DC ) / fvco(khz)] x Kvco _ dc(khz/volt) Example (A): Choose Vchgpump =.5V, desired frequency (fvco) = 300KHz 2 - Small Signal gain for VCO: Rvco = [E2 x.5 /300] x 62 Hz = 3 KΩ Kvco_ac (KHz/Volt) = E2 x Kvco_dc (KHz/Volt)/Rvco(KΩ) Example (B): Choosing same conditions as in example A: Kvco_ac = E2 x 62 / 3 = 200 KHz/volt 6

7 IR PLL Natural frequency: wn =2pfn(KHz)= Ichpump(uA) x Kvco_ac(KHz/V) / C(nF) Choose Cf such that Cf=C/6 4 - PLL Damping factor calculations: P = pe-3 x Rf (KOhms) x C(nF) x fn(khz) Typical value for P is (Critically damped) 5 - Advance timing: Tadv(nsec) = RADV (KOhms)* Where RADV is resistance from RADV or RADV2 to ground. Example C: RADV=0Kohms wil result in Tadv=0* =06 =90 nsec.. 6- Dead time calculations: Td(nsec)=0.69*Cdt(pF)*(Rdt(KΩ)+0.5) Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For (For Vdd=5 Vdd=5V) V) Where Rdt is resistance between pins DTIN and DTOUT or DTIN2 and DTOUT2. Cdt is capacitance from DTIN or DTIN2 to ground. Example D: Rd=2KW and Cdt=00pF will result in Td=48.35nsec. Fig. 4 PLL loop filter component definitions 7

8 IR76 IR76 Fig. 5 IR76 Block Diagram 8

9 IR time time T_DT T_DT T_DT K 4K 6K 8K 0K resistance Response at 25 o C T_DT vs R_DT, C = 00pF temperature Temperature Response T_DT vs R_DT, C = 00pF time time T_ADV (ns)r=5k T_ADV (ns)r=0k T_ADV (ns)r=20k T_ADV (ns)r=45k K 20K 30K 40K 50K resistance Response at 25 o C T_ADV vs R_ADV temperature Temperature Response T_ADV vs R_ADV 9

10 IR76 Case Outline 20 Lead Surface Mount (SSOP-20) (MS03AC) 0

11 IR76 Case Outline 20 Lead SOIC (MS03AC)

12 IR76 Case Outline 20 Lead PDIP (MS00AD) WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California Tel: (30) Data and specifications subject to change without notice. /7/