IPS021S FULLY PROTECTED POWER MOSFET SWITCH

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Caitlin Copeland
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1 Data Sheet No.PD 648-K IPS(S) FULLY PROTECTED POWER MOSFET SWITCH Features Over temperature shutdown Over current shutdown Active clamp Low current & logic level input E.S.D protection Product Summary R ds(on) 5mΩ (max) V clamp 5V Description The IPS/IPSS are fully protected three terminal SMART POWER MOSFETs that feature over-current, over-temperature, ESD protection and drain to source active clamp.these devices combine a HEXFET POWER MOSFET and a gate driver. They offer full protection and high reliability required in harsh environments. The driver allows short switching times and provides efficient protection by turning OFF the power MOSFET when the temperature exceeds 65 o C or when the drain current reaches 5A. These devices restart once the input is cycled. The avalanche capability is significantly enhanced by the active clamp and covers most inductive load demagnetizations. I shutdown T on/ T off Packages 5A.5µs 3-Lead D Pak IPSS Typical Connection 3-Lead TO- IPS Load R in series (if needed) IN control ƒ D S Logic signal (Refer to lead assignment for correct pin configuration)

2 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are referenced to SOURCE lead. (TAmbient = 5 o C unless otherwise specified). PCB mounting uses the standard footprint with 7 µm copper thickness. Symbol Parameter Min. Max. Units Test Conditions V ds Maximum drain to source voltage 47 V in Maximum input voltage Iin, max Maximum IN current - + ma Isd cont. Diode max. continous current () (rth=6 o C/W) IPS.8 (rth= o C/W) IPS 8 (rth=8 o C/W) IPSS. Isd pulsed Diode max. pulsed current () A Pd Maximum power dissipation () (rth=6 o C/W) IPS (rth=8 o C/W) IPSS.56 ESD Electrostatic discharge voltage (Human Body) 4 C=pF, R=5Ω, ESD Electrostatic discharge voltage (Machine Model).5 kv C=pF, R=Ω, L=µH T stor. Max. storage temperature Tj max. Max. junction temperature Tlead Lead temperature (soldering, seconds) 3 Thermal Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Rth Thermal resistance free air 6 Rth Thermal resistance junction to case 5 Rth Thermal resistance with standard footprint 8 Rth Thermal resistance with " square footprint 5 Rth 3 Thermal resistance junction to case 5 () Limited by junction temperature (pulsed current limited also by internal wiring) () Operations at higher switching frequencies is possible. See Appl. Notes. V A W o C o C/W TO- D PAK (SMD) Recommended Operating Conditions These values are given for a quick design. For operation outside these conditions, please consult the application notes. Symbol Parameter Min. Max. Units Vds (max) Continuous drain to source voltage 35 VIH High level input voltage 4 6 V VIL Low level input voltage.5 Ids Continuous drain current.8 A Tamb=85 o C (TAmbient = 85 o C, IN = 5V, rth = 6 o C/W, Tj = 5 o C) Rin Recommended resistor in series with IN pin.5 5 kω Tr-in (max) Max recommended rise time for IN signal (see fig. ) µs Fr-Isc () Max. frequency in short circuit condition (Vcc = 4V) khz

3 Static Electrical Characteristics Standard footprint 7 µm copper thickness. Tj = 5 o C (unless otherwise specified.) Symbol Parameter Min. Typ. Max. Units Test Conditions Rds(on) ON state resistance Tj = 5 o C 3 5 Tj = 5 o mω Vin = 5V, Ids = A C 8 Idss Drain to source leakage current. 5 Vcc = 4V, Tj = 5 o C µa Idss Drain to source leakage current. 5 Vcc = 4V, Tj = 5 o C V clamp Drain to source clamp voltage Id = ma (see Fig.3 & 4) V clamp Drain to source clamp voltage Id=Ishutdown (see Fig.3 & 4) V Vin clamp IN to source clamp voltage Iin = ma Vth IN threshold voltage.5 Id = 5mA, V ds = 4V Iin, -on ON state IN positive current 5 9 Vin = 5V Iin, -off ON state IN positive current µa Vin = 5V over-current triggered Switching Electrical Characteristics Vcc = 4V, Resistive Load = Ω, Rinput = 5Ω, µs pulse, T j = 5 o C, (unless otherwise specified). Symbol Parameter Min. Typ. Max. Units Test Conditions Ton Turn-on delay time.5.5 Tr Rise time.4.9 See figure Trf Time to (final Rds(on).3) 6 µs Toff Turn-off delay time See figure Tf Fall time Qin Total gate charge 3.3 nc Vin = 5V Protection Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Tsd Over temperature threshold 65 o C See fig. Isd Over current threshold A See fig. V reset IN protection reset threshold V Treset Time to reset protection 4 µs Vin = V, Tj = 5 o C EOI_OT Short circuit energy (see application note) 4 µj Vcc = 4V 3

4 Functional Block Diagram All values are typical DRAIN 47 V Ω k Ω IN S Q 8. V 8 µ A R Q T > 65 c I sense I > Isd SOURCE Lead Assignments (D) (D) 3 In D S 3 In D S TO- IPS Part Number D PAK (SMD) IPSS 4

5 Vin 5 V V Vin 9 % % Tr-in Ids Isd I shutdown t < T reset t > T reset Ids 9 % % Td on tr Td off tf T Tsd (65 c) T shutdown Vds Figure - Timing diagram Figure - IN rise time & switching time definitions T clamp Vin L V load Ids Vds Vds clamp ( Vcc ) Rem : V load is negative during demagnetization 5 v v Vin IN R D S Vds Ids + 4 V - ( see Appl. Notes to evaluate power dissipation ) Figure 3 - Active clamp waveforms Figure 4 - Active clamp test circuit 5

6 All curves are typical values with standard footprints. Operating in the shaded area is not recommended Tj = 5 o C Tj = 5 o C % 8% 6% 4% % % 8% 6% 4% % % Figure 5 - Rds ON (mω) Vs Input Voltage (V) Figure 6 - Normalized Rds(on) (%) Vs Tj ( o C) ton delay rise time 3% rdson toff delay fall time Figure 7 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) (us) Vs Input Voltage (V) Figure 8 - Turn-OFF Delay Time & Fall Time (us) Vs Input Voltage (V) 6

7 delay on rise time 3% rdson delay off fall time. Figure 9 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) (us) Vs IN Resistor (Ω). Figure - Turn-OFF Delay Time & Fall Time (us) Vs IN Resistor (Ω) Isd 5 C Ilim 5 C Figure - Current Iim. & I shutdown (A) Vs Vin (V) Figure - I shutdown (A) Vs Temperature ( o C) 7

8 8 7 6 rth = 5 C/W rth = 5 C/W " footprint 35 C/W std. footprint 6 C/W T=5 C Std. footprint T= C Std. footprint Current path capability should be above this curve Load characteristic should be below this curve Figure 3 - Max.Cont. Ids (A) Vs Amb. Temperature ( o C) IPS/IPSS Figure 4 - Ids (A) Vs Protection Resp. Time (s) IPS & IPSS single pulse max. current Hz rth=6 C/W dt=5 C khz rth=6 C/W dt=5 C single pulse Hz rth=6 C/W dt=5 C khz rth=6 C/W dt=5 C. Vbat = 4 V Tjini = T sd.. Figure 5a - Iclamp (A) Vs Inductive Load (mh) IPS. Vbat = 4 V Tjini = T sd.. Figure 5b - Max. Iclamp (A) Vs Inductive Load (mh) IPSS 8

9 .. Single pulse Iin,on Iin,off Figure 6 - Transient Thermal Imped. ( o C/W) Vs Time (s) Figure 7 - Input Current (ua) Vs Junction Temperature ( o C) Treset rise time fall time % 5% % 5% % 95% % Vds Isd 85% Vin ma 8% Figure 8 - Rise Time, Fall Time and Treset (µs) Vs Tj ( o C) Figure 9 -Vin clamp and Vds clamp (%) Vs Tj ( o C) 9

10 Case Outline NOTES: X 3-Lead TO-AB -64 IRGB -36 (TO-AB) 3-Lead D PAK (TO-63AB)

11 Tape & Reel - D PAK (SMD) -37 IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 945 Tel: (3) 5-75 Data and specifications subject to change without notice. 6//

12 Note: For the most current drawings please refer to the IR website at:

IPS031S FULLY PROTECTED POWER MOSFET SWITCH. Product Summary

IPS031S FULLY PROTECTED POWER MOSFET SWITCH. Product Summary Data Sheet No.PD 65-J FULLY PROTECTED POWER MOSFET SWITCH Features Over temperature shutdown Over current shutdown Active clamp Low current & logic level input E.S.D protection Description The IPS3/IPS3S