MC33363A. MARKING DIAGRAMS. Features PIN CONNECTIONS

Transcription

1 High Voltage Switching egulator The MA is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 24 Vac line source. This integrated circuit features an on chip V /.5 A SENSEFET power switch, 5 V active off line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle by cycle current limiting, input undervoltage lockout with hysteresis, output overvoltage protection, and thermal shutdown. This device is available in a lead dual in line and wide body surface mount packages. Features Enhanced Power apability Over M On hip V,.5 A SENSEFET Power Switch ectified 24 Vac Line Source Operation On hip 5 V Active Off Line Startup FET Latching PWM for Double Pulse Suppression ycle By ycle urrent Limiting Input Undervoltage Lockout with Hysteresis Output Overvoltage Protection omparator Trimmed Internal Bandgap eference Internal Thermal Shutdown These are Pb Free Devices* A Input egulator Output T T Mirror OS PWM Thermal eg Startup PWM Latch S Q I pk Startup Input Driver LEB V Overvoltage Protection Input EA Voltage Feedback GND 4, 5, 2, Input This device contains 22 active transistors. Figure. Simplified Application UVLO OVP Power Switch Drain ompensation 9 D Output Startup Input GND SO W DW SUFFIX ASE 5N A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package V T T egulator Output PIN ONNETIONS 4 5 MAKING DIAGAMS MADW AWLYYWWG Power Switch Drain GND 2 Overvoltage Protection Input Voltage Feedback Input 9 ompensation (Top View) ODEING INFOMATION See detailed ordering and shipping information on page of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. Semiconductor omponents Industries, LL, 25 February, 25 ev. Publication Order Number: MA/D

2 MAXIMUM ATINGS (Note ) ating Symbol Value Unit Power Switch (Pin ) Drain Voltage Á V DS Drain urrent I DS V.5 A Startup Input Voltage (Pin ) V in 5 V Power Supply Voltage (Pin ) V 4 V Input Voltage ange V Voltage Feedback Input (Pin ) Á I. to V reg V ompensation (Pin 9) Overvoltage Protection Input (Pin ) T (Pin ) T (Pin ) Thermal haracteristics P Suffix, Dual In Line ase 4E /W Thermal esistance, Junction to Air Thermal esistance, Junction to ase (Pins 4, 5, 2, ) Á JA J 5 DW Suffix, Surface Mount ase 5N Thermal esistance, Junction to Air Thermal esistance, Junction to ase Á JA 95 J 5 (Pins 4, 5, 2, ) efer to Figures and for additional thermal information. ÁÁ Operating Junction Temperature T J 25 to +5 ÁÁ Storage Temperature 55 to +5 Stresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. This device series contains ESD protection and exceeds the following tests: Human Body Model 2 V per JEDE Standard JESD22, Method A4E. Machine Model Method 5 V per JEDE Standard JESD22, Method A5A. T stg ELETIAL HAATEISTIS (V = 2 V, T = k, T = 9 pf, Pin =. F, for typical values T J = 25, for min/max values T J is the operating junction temperature range that applies (Note 2), unless otherwise noted) haracteristic Symbol Min Typ Max Unit EGULATO (Pin ) Output Voltage (I O = ma, T J = 25 ) V reg Á Á.5 V Line egulation (V = 2 V to 4 V) eg line Á Á 5 mv Load egulation (I O = ma to ma) eg load Á 44 Á 2 mv Total Output Variation over Line, Load, and Temperature V reg Á 5. Á. V OSILLATO (Pin ) Frequency f OS Á khz T = 9 pf T J = 25 (V = 2 V) 2 25Á T J = T low to T high (V = 2 V to 4 V) T = 2. nf T J = 25 (V = 2 V).5Á 5 T J = T low to T high (V = 2 V to 4 V) 59 Á Á Frequency hange with Voltage (V = 2 V to 4 V) f OS / V. Á 2. khz EO AMPLIFIE (Pins 9, ) Á Voltage Feedback Input Threshold V FB Á 2. V Á Line egulation (V = 2 V to 4 V, T J = 25 ) eg line. Á 5. mv Á Input Bias urrent (V FB = 2. V) I IB 2 Á 5 na Á Open Loop Voltage Gain (T J = 25 ) 2 Á db Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2. Tested junction temperature range for the MA: T low = 25 T high = +25 A VOL 2

3 ELETIAL HAATEISTIS (V = 2 V, T = k, T = 9 pf, Pin =. F, for typical values T J = 25, for min/max values T J is the operating junction temperature range that applies (Note 2), unless otherwise noted) haracteristic Symbol EO AMPLIFIE (Pins 9, ) Gain Bandwidth Product (f = khz, T J = 25 ) GBW Á. Á MHz Output Voltage Swing V High State (I Source = A, V FB < 2. V) V Low State (I Sink = A, V FB >. V) OH 4. V OL Á 5..2 Á.5 OVEVOLTAGE DETETION (Pin ) Input Threshold Voltage Á 2. V Input Bias urrent (V in = 2. V) I IB Á Á 5 na PWM OMPAATO (Pins, 9) Duty ycle % Maximum (V FB = V) D Minimum (V FB = 2. V) (max) 4 D (min) Á 5 52 Á POWE SWITH (Pin ) Drain Source On State esistance (I D = 2 ma) V th DS(on) T J = 25.5 Á 9. T J = T low to T high 2 Drain Source Off State Leakage urrent (V DS = 5 V) I T J = 25 D(off) A Á.25Á. T J = T low to T high 5 ise Time t r Á 5 Á ns Fall Time t f Á 5 Á ns OVEUENT OMPAATO (Pin ) urrent Limit Threshold ( T = k) I lim Á..9 Á. A STATUP ONTOL (Pin ) Peak Startup urrent (V in = 5 V) (T J = 25 to ) V I start Á ma = V 2. V = (V th(on).2 V) Á. Off State Leakage urrent (V in = 5 V, V = 2 V) I D(off) Á 4 Á 2 A UNDEVOLTAGE LOKOUT (Pin ) Startup Threshold (V Increasing) V th(on) Á 4.9Á V Minimum Operating Voltage After Turn On V (min) Á Á.5 V TOTAL DEVIE (Pin ) Power Supply urrent I Á ma Startup (V = V, Pin Open).2.5 Operating.4 Á 5. Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2. Tested junction temperature range for the MA: T low = 25 T high = +25 Min Typ Max Unit

4 f OS, OSILLATO FEQUENY (Hz). M T = pf 5 k T = 2 pf 2 k T = 5 pf k T =. nf 5 k T = 2. nf 2 k T = 5. nf V = 2 V T = nf k T, TIMING ESISTO (k ) I PK, POWE SWITH PEAK DAIN UENT (A) V = 2 V T =. F.2 Inductor supply voltage and inductance value are adjusted so that I pk turn-off is achieved at 5. s T, TIMING ESISTO (k ) Figure 2. Oscillator Frequency versus Timing esistor Figure. Power Switch Peak Drain urrent versus Timing esistor I chg /I dscg, OSILLATO HAGE/DISHAGE UENT (ma) V = 2 V D max, MAXIMUM OUTPUT DUTY YLE (%) 4 / T atio harge esistor Pin to V reg T, TIMING ESISTO (k ) TIMING ESISTO ATIO Figure 4. Oscillator harge/discharge urrent versus Timing esistor 5 D / T atio Discharge esistor Pin to GND V = 2 V T = 2. nf Figure 5. Maximum Output Duty ycle versus Timing esistor atio A VOL, OPEN LOOP VOLTAGE GAIN (db) Phase Gain f, FEQUENY (Hz) V = 2 V V O =. to 4. V L = 5. M L = 2. pf 9 2 θ, EXESS PHASE (DEGEES) V sat, OUTPUT SATUATION VOLTAGE (V) Source Saturation (Load to Ground) Sink Saturation V = 2 V (Load to V ref ) 5. GND. k k k. M M V ref I O, OUTPUT LOAD UENT (ma) Figure. Error Amp Open Loop Gain and Phase versus Frequency Figure. Error Amp Output Saturation Voltage versus Load urrent 4

5 . V V = 2 V A V = -. L = pf. V V = 2 V A V = -. L = pf.5 V 2 mv/div.5 V.5 V/DIV. V.5 V. s/div. s/div Figure. Error Amplifier Small Signal Transient esponse Figure 9. Error Amplifier Large Signal Transient esponse V reg, EGULATO VOLTAGE HANGE (mv) Δ V = 2 V T = k I reg, EGULATO SOUE UENT (ma) I start, STATUP UENT (ma) V Pin = 5 V V, SUPPLY VOLTAGE (V) Figure. egulator Output Voltage hange versus Source urrent Figure. Peak Startup urrent versus Power Supply Voltage I start, STATUP UENT (ma) V = V V = 4 V V Pin, STATUP PIN VOLTAGE (V) Figure 2. Peak Startup urrent versus Startup Input Voltage 5

6 DS(on), DAIN-SOUE ON-ESISTANE ( Ω ) I D = 2 ma OSS, DAIN-SOUE APAITANE (pf) Pulse tested at 5. ms with <.% duty cycle so that T J is as close to T A as possible. OSS measured at. MHz with 5 mvpp T A, AMBIENT TEMPEATUE ( ) Figure. Power Switch Drain Source On esistance versus Temperature 2 4 V DS, DAIN-SOUE VOLTAGE (V) V = 2 V Figure 4. Power Switch Drain Source apacitance versus Voltage I, SUPPLY UENT (ma) T = 9 pf T = 2. nf V, SUPPLY VOLTAGE (V) T = k Pin = Open Pin 4, 5,,, 2, = GND Figure 5. Supply urrent versus Supply Voltage θ JA, THEMAL ESISTANE JUNTION-TO-AI ( /W) L = 2. mm of 2. oz. copper. efer to Figures and... t, TIME (s) Figure. DW and P Suffix Transient Thermal esistance θ JA, THEMAL ESISTANE JUNTION-TO-AI ( /W) JA P D(max) for T A = L, LENGTH OF OPPE (mm) Printed circuit board heatsink example ÎÎÎ 2. oz ÎÎ L opper L. mm Graphs represent symmetrical layout P D, MAXIMUM POWE DISSIPATION (W) θja, THEMAL ESISTANE JUNTION-TO-AI ( /W) 4 2 Printed circuit board heatsink example L ÎÎ 2. oz ÎÎÎ opper JA L. mm Graphs represent symmetrical layout P D(max) for T A = L, LENGTH OF OPPE (mm) P D, MAXIMUM POWE DISSIPATION (W) Figure. DW Suffix (SOP L) Thermal esistance and Maximum Power Dissipation versus P..B. opper Length Figure. P Suffix (DIP ) Thermal esistance and Maximum Power Dissipation versus P..B. opper Length

7 PIN FUNTION DESIPTION Pin Function Description Á Startup Input This pin connects directly to the rectified ac line voltage source. Internally Pin is tied to the drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges an external capacitor that connects from the V pin to ground. 2 This pin has been omitted for increased spacing between the rectified ac line voltage on Pin and the V potential on Pin. Á V This is the positive supply voltage input. During startup, power is supplied to this input from Pin. When V reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied from an auxiliary transformer winding. 4, 5, 2, Á GND These pins are the control circuit grounds. They are part of the I lead frame and provide a thermal path from the die to the printed circuit board. Á T esistor T connects from this pin to ground. The value selected will program the urrent Limit omparator threshold and affect the Oscillator frequency. T apacitor T connects from this pin to ground. The value selected, in conjunction with resistor T, programs the Oscillator frequency. Á egulator Output This.5 V output is available for biasing external circuitry. It requires an external bypass capacitor of at least. F for stability. 9 ompensation This pin is the Error Amplifier output and is made available for loop compensation. It can be used as an input to directly control the PWM omparator. Voltage Feedback This is the inverting input of the Error Amplifier. It has a 2. V threshold and normally connects Input through a resistor divider to the converter output, or to a voltage that represents the converter output. Overvoltage This input provides runaway output voltage protection due to an external component or Protection Input connection failure in the control loop feedback signal path. It has a 2. V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output. Á 4, 5 These pins have been omitted for increased spacing between the high voltages present on the Power Switch Drain, and the ground potential on Pins 2 and. Á Power Switch This pin is designed to directly drive the converter transformer and is capable of switching a Drain maximum of V and. A. ODEING INFOMATION MADWG MADW2G Device Package Shipping SOI WB (Pb Free) SOI WB (Pb Free) 4 Units / ail / Tape & eel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, BD/D.

8 A Input Startup Input egulator Output.5 V T T I urrent Mirror 4 I Oscillator PWM omparator Thermal Shutdown 2.25 I Band Gap egulator PWM Latch urrent Limit omparator S Q 45 Startup ontrol UVLO OVP Driver Leading Edge Blanking 4.5 V/ 9.5 V 2. V. V Overvoltage Protection Input Power Switch Drain ompensation 9 D Output Gnd 4, 5, 2, 2 μa Error Amplifier 2. V Voltage Feedback Input Figure 9. epresentative Block Diagram apacitor T ompensation 2. V. V Oscillator Output PWM omparator Output PWM Latch Q Output Power Switch Gate Drive Leading Edge Blanking Input (Power Switch Drain urrent) urrent Limit Propagation Delay urrent Limit Threshold Normal PWM Operating ange Output Overload Figure 2. Timing Diagram

9 OPEATING DESIPTION Introduction The MA represents a new higher level of integration by providing all the active high voltage power, control, and protection circuitry required for implementation of a flyback or forward converter on a single monolithic chip. This device is designed for direct operation from a rectified 24 Vac line source and requires a minimum number of external components to implement a complete converter. A description of each of the functional blocks is given below, and the representative block and timing diagrams are shown in Figures 9 and 2. Oscillator and urrent Mirror The oscillator frequency is controlled by the values selected for the timing components T and T. esistor T programs the oscillator charge/discharge current via the urrent Mirror 4 I output, Figure 4. apacitor T is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 5% duty cycle waveform at Pin, with a peak and valley threshold of 2. V and. V respectively. During the discharge of T, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below. MHz. The maximum Power Switch duty cycle at Pin can be modified from the internal 5% limit by providing an additional charge or discharge current path to T, Figure 2. In order to increase the maximum duty cycle, a discharge current resistor D is connected from Pin to ground. To decrease the maximum duty cycle, a charge current resistor is connected from Pin to the egulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either or D with respect to T. D egulator Output. T T I urrent Mirror PWM omparator 2.25 I Figure 2. Maximum Duty ycle Modification 4 I Oscillator urrent Limit eference Blanking Pulse The formula for the charge/discharge current along with the oscillator frequency are given below. The frequency formula is a first order approximation and is accurate for T values greater than 5 pf. For smaller values of T, refer to Figure 2. Note that resistor T also programs the urrent Limit omparator threshold. I chg dscg 5.4 T f I chg dscg 4 T PWM omparator and Latch The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while T is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When T charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp up period. This PWM omparator/latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 2 illustrates the Power Switch duty cycle behavior versus the ompensation voltage. urrent Limit omparator and Power Switch The MA uses cycle by cycle current limiting as a means of protecting the output switch transistor from overstress. Each on cycle is treated as a separate situation. urrent limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 29 cells, of which 5 are connected to a. ground referenced sense resistor. The urrent Sense omparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the urrent Mirror. This current causes a reference voltage to appear across the 45 resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor T. Therefore when selecting the values for T and T, T must be chosen first to set the Power Switch peak drain current, while T is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus T is shown in Figure with the related formula below. I 5.95 pk T.4 The Power Switch is designed to directly drive the converter transformer and is capable of switching a 9

10 maximum of V and. A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn on transition is completed. The current limit propagation delay time is typically ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn off. Error Amplifier An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 9. It features a typical dc voltage gain of 2 db, and a unity gain bandwidth of. MHz with degrees of phase margin, Figure. The noninverting input is internally biased at 2. V ±.% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM omparator. The output was designed with a limited sink current capability of 2 A, allowing it to be easily overridden with a pull up resistor. This is desirable in applications that require secondary side voltage sensing, Figure 22. In this application, the Voltage Feedback Input is connected to the egulator Output. This disables the Error Amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the PWM omparator. Overvoltage Protection An Overvoltage Protection omparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side V voltage. When the 2. V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout An Undervoltage Lockout (UVLO) comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the V voltage at Pin and when it exceeds 4.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5. V of hysteresis is provided. Startup ontrol An internal Startup ontrol circuit with a high voltage enhancement mode MOSFET is included within the MA. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off line converters that utilize a U42 type of controller. ectified ac line voltage is applied to the Startup Input, Pin. This causes the MOSFET to enhance and supply internal bias as well as charge current to the V bypass capacitor that connects from Pin to ground. When V reaches the UVLO upper threshold of 5.2 V, the I commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. egulator A low current.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to ma and has short circuit protection. This output requires an external bypass capacitor of at least. F for stability. Thermal Shutdown and Package Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 55, the Latch is forced into a reset state, disabling the Power Switch. The Latch is allowed to set when the Power Switch temperature falls below 45. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MA is contained in a heatsinkable plastic dual in line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures and show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single sided board with two ounce per square foot of copper. Figure 2 shows a practical example of a printed circuit board layout that utilizes the copper foil as a heat dissipater. Note that a jumper was added to the layout from Pins to in order to enhance the copper area near the device for improved thermal conductivity. The application circuit requires two ounce copper foil in order to obtain. W of continuous output power at room temperature.

11 92 to 2 Vac Input 4. k 2 pf F. A D4 D2 D N4 D Mirror Osc PWM Thermal eg 4 PWM Latch S Q ILimit Startup Driver LEB UVLO 4.5 V/ 9.5 V OVP 2. V 5 4. nf k. W D5 MU E k. k pf 2.2 k. W D MU 2 T D MB 5 9 I2 MO I TL4B 2 2 L 5. μh 5.5 V/. A D Output k nf 2.4 k μa EA 2. V k 4, 5, 2, I MA Figure W Off Line onverter Table. ONVETE TEST DATA Test onditions esults Line egulation V in = 92 Vac to 2 Vac, I O. A =. mv Load egulation V in = 5 Vac, I O =.5 A to. A = 5. mv V in = 2 Vac, I O =.5 A to. A = 5. mv Output ipple V in = 5 Vac, I O =. A Triangular = 2. mvpp, Spike = 2 mvpp V in = 2 Vac, I O =. A Efficiency V in = 5 Vac, I O =. A.%* V in = 2 Vac, I O =. A.% Triangular = 2. mvpp, Spike = 4 mvpp This data was taken with the components listed below mounted on the printed circuit board shown in Figure 2. *With MB255TL,.% efficiency. PB layout modification is required to use this rectifier. For high efficiency and small circuit board size, the Sanyo Os on capacitors are recommended for, 9, and., 9, = Sanyo Os on #SAM, F. V. = Sanyo Os on #SA22M, 22 F V. L = oilcraft S5 A, 5. H,.. T = oilcraft U5 A Primary: turns of # 2 AWG, Pin = start, Pin = finish. Two layers.2 Mylar tape. Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish. Two layers.2 Mylar tape. Auxiliary: turns of # 2 AWG wound in center of bobbin, Pin 2 = start, Pin = finish. Two layers.2 Mylar tape. Gap:. total for a primary inductance (L P ) of 2 H. ore and Bobbin: oilcraft PT95, E, F material.

12 aution! High Voltages D 4 2 J I2 I 9 D Output 2 D2 F I A Line Input 2 D 5 4 L D D4 D5 T 9 5 (Top View) 2.5" MA 2.25 D (Bottom View) Figure 2. Printed ircuit Board and omponent Layout (ircuit of Figure 22) 2

13 PAKAGE DIMENSIONS T A SO W DW SUFFIX ASE 5N ISSUE O 9 X D 9X G B. (.25) M T A S B S S K P T SEATING PLANE. (.25) M J F M B M X 45 NOTES:. DIMENSIONING AND TOLEANING PE ANSI Y4.5M, ONTOLLING DIMENSION: MILLIMETE.. DIMENSIONS A AND B DO NOT INLUDE MOLD POTUSION. 4. MAXIMUM MOLD POTUSION.5 (.) PE SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE. (.5) TOTAL IN EXESS OF D DIMENSION AT MAXIMUM MATEIAL ONDITION. MILLIMETES INHES DIM MIN MAX MIN MAX A B D F G.2 BS.5 BS J K M P S 2.54 BS. BS T. BS.5 BS SENSEFET is a registered trademark of Semiconductor omponents Industries, LL (SILL). ON Semiconductor and the are registered trademarks of Semiconductor omponents Industries, LL (SILL) or its subsidiaries in the United States and/or other countries. SILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ODEING INFOMATION LITEATUE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 5, Denver, olorado 2 USA Phone: 5 25 or 44 Toll Free USA/anada Fax: 5 2 or 44 Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: 5 5 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative MA/D