LM358S, LM2904S. Single Supply Dual Operational Amplifiers

Transcription

1 , LM904S Single Supply Dual Operational Amplifiers Utilizing the circuit designs perfected for Quad Operational Amplifiers, these dual operational amplifiers feature low power drain, a common mode input voltage range extending to ground/v EE, and single supply or split supply operation. The and LM904S are half of the LM34S and LM90S, respectively. These amplifiers have several distinct advantages over standard operational amplifier types in single supply applications. The common mode input range includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage. Features Short ircuit Protected Outputs True Differential Input Stage Single Supply Operation: 3.0 V to 3 V Low Input Bias urrents Internally ompensated ommon Mode ange Extends to Negative Supply Single and Split Supply Operation These Devices are Pb Free, Halogen Free/BF Free and are ohs ompliant PDIP 8 N SUFFIX ASE 66 MAKING DIAGAMS LMxxxx = Specific Device ode A, AL = Assembly Location WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package N AWL YYWWG LM904SN AWL YYWWG PIN ONNETIONS Output A 8 7 Output B Inputs A 3 6 Inputs B V EE /GND 4 5 (Top View) ODEING INFOMATION See detailed ordering and shipping information on page 8 of this data sheet. Semiconductor omponents Industries, LL, 04 October, 04 ev. 0 Publication Order Number: /D

2 , LM904S 3.0 V to (max).5 V to (max).5 V to V EE(max) V EE /GND Single Supply Figure. V EE Split Supplies Output Bias ircuitry ommon to Both Amplifiers Q6 Q5 Q4 Q3 Q Q9 40 k 5.0 pf Q 5 Q3 Q4 Q8 Q0 Inputs Q Q7 Q3 Q4 Q Q5 Q6 Q6 Q7 Q8 Q9 Q Q0 Q.0 k Q5.4 k V EE /GND Figure. epresentative Schematic Diagram (One Half of ircuit Shown)

3 , LM904S MAXIMUM ATINGS (T A = 5, unless otherwise noted.) ating Symbol Value Unit Power Supply Voltages Single Supply Split Supplies 3, V EE ±6 Vdc Input Differential Voltage ange (Note ) V ID ±3 Vdc Input ommon Mode Voltage ange (Note ) V I 0.3 to 3 Vdc Output Short ircuit Duration t S ontinuous Junction Temperature T J 50 Thermal esistance, Junction to Air (Note 3) ase 66 JA 6 /W Storage Temperature ange T stg 65 to 50 Operating Ambient Temperature ange LM904S T A 0 to to 05 Stresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Split Power Supplies.. For supply voltages less than 3 V the absolute maximum input voltage is equal to the supply voltage. 3. All JA measurements made on evaluation board with oz. copper traces of minimum pad size. All device outputs were active. 3

4 , LM904S ELETIAL HAATEISTIS ( = 5.0 V, V EE = GND, T A = 5, unless otherwise noted.) haracteristic Input Offset Voltage = 5.0 V to 30 V, V I = 0 V to.7 V, V O.4 V, S = 0 Symbol V IO Min Typ Max T A = T A = T high (Note 4) 9.0 T A = T low (Note 4) 9.0 Average Temperature oefficient of Input Offset Voltage V IO / T 7.0 V/ T A = T high to T low (Note 4) Input Offset urrent I IO na T A = T high to T low (Note 4) 50 Input Bias urrent I IB na T A = T high to T low (Note 4) Average Temperature oefficient of Input Offset urrent I IO / T 0 pa/ T A = T high to T low (Note 4) Input ommon Mode Voltage ange (Note 5), = 30 V V I V = 30 V, T A = T high to T low 0 8 Differential Input Voltage ange V ID V Large Signal Open Loop Voltage Gain A VOL V/mV L =.0 k, = 5 V, For Large V O Swing, 5 00 T A = T high to T low (Note 4) 5 hannel Separation.0 khz f 0 khz, Input eferenced ommon Mode ejection S 0 k Unit mv S 0 db M db Power Supply ejection PS db Output Voltage High Limit V OH V = 5.0 V, L =.0 k, T A = = 30 V, L =.0 k, T A = T high to T low (Note 4) 6 = 30 V, L = 0 k, T A = T high to T low (Note 4) 7 8 Output Voltage Low Limit = 5.0 V, L = 0 k, T A = T high to T low (Note 4) V OL mv Output Source urrent I O ma Output Sink urrent V ID =.0 V, = 5 V 0 45 V ID =.0 V, = 5 V 0 30 ma V ID =.0 V, V O = 00 mv 40 A Output Short ircuit to Ground (Note 6) I S ma Power Supply urrent (Total Device) I ma T A = T high to T low (Note 4) = 30 V, V O = 0 V, L = = 5 V, V O = 0 V, L = 0.3. Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 4. : T low = 0, T high = 70 LM904S: T low = 40, T high = The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common mode voltage range is.7 V. 6. Short circuits from the output to can cause excessive heating and eventual destruction. Destructive dissipation can result from simultaneous shorts on all amplifiers. I O 4

5 , LM904S ELETIAL HAATEISTIS ( = 5.0 V, V EE = GND, T A = 5, unless otherwise noted.) haracteristic Input Offset Voltage = 5.0 V to 30 V, V I = 0 V to.7 V, V O.4 V, S = 0 Symbol V IO LM904S Min Typ Max T A = T A = T high (Note 7) 0 T A = T low (Note 7) 0 Average Temperature oefficient of Input Offset Voltage T A = T high to T low (Note 7) Unit mv V IO / T 7.0 V/ Input Offset urrent I IO na T A = T high to T low (Note 7) Input Bias urrent I IB na T A = T high to T low (Note 7) Average Temperature oefficient of Input Offset urrent T A = T high to T low (Note 7) Input ommon Mode Voltage ange (Note 8), = 30 V I IO / T 0 pa/ V I = 30 V, T A = T high to T low 0 8 Differential Input Voltage ange V ID V Large Signal Open Loop Voltage Gain A VOL V/mV L =.0 k, = 5 V, For Large V O Swing, 5 00 T A = T high to T low (Note 7) 5 hannel Separation.0 khz f 0 khz, Input eferenced ommon Mode ejection S 0 k S 0 db M db Power Supply ejection PS db Output Voltage High Limit V OH V = 5.0 V, L =.0 k, T A = = 30 V, L =.0 k, T A = T high to T low (Note 7) 6 = 30 V, L = 0 k, T A = T high to T low (Note 7) 7 8 Output Voltage Low Limit = 5.0 V, L = 0 k, T A = T high to T low (Note 7) Output Source urrent V ID =.0 V, = 5 V Output Sink urrent V OL mv I O 0 45 ma V ID =.0 V, = 5 V 0 30 ma V ID =.0 V, V O = 00 mv A Output Short ircuit to Ground (Note 9) I S ma Power Supply urrent (Total Device) I ma T A = T high to T low (Note 7) = 30 V, V O = 0 V, L = = 5 V, V O = 0 V, L = 0.3. Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 7. : T low = 0, T high = 70 LM904S: T low = 40, T high = The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common mode voltage range is.7 V. 9. Short circuits from the output to can cause excessive heating and eventual destruction. Destructive dissipation can result from simultaneous shorts on all amplifiers. I O V 5

6 , LM904S IUIT DESIPTION The and LM904S are made using two internally compensated, two stage operational amplifiers. The first stage of each consists of differential input devices Q0 and Q8 with input buffer transistors Q and Q7 and the differential to single ended converter Q3 and Q4. The first stage performs not only the first stage gain function but also performs the level shifting and transconductance reduction functions. By reducing the transconductance, a smaller compensation capacitor (only 5.0 pf) can be employed, thus saving chip area. The transconductance reduction is accomplished by splitting the collectors of Q0 and Q8. Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to single ended converter. The second stage consists of a standard current source load amplifier stage. Each amplifier is biased from an internal voltage regulator which has a low temperature coefficient thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. 6

7 , LM904S 50 k M403.5 V V O =.5 V ( ) V O = V 0 k 5.0 k V V O f o = For: f o =.0 khz = 6 k = 0.0 F Figure 3. Voltage eference Figure 4. Wien Bridge Oscillator e V OH Hysteresis e a b e o V in V O V O V OL V inl = (V OL ) V inh = (V OH ) V inl V inh e o = ( a b) (e e ) H = (V OH V OL ) Figure 5. High Impedance Differential Amplifier Figure 6. omparator with Hysteresis V in 00 k 00 k V ref Bandpass 3 Output Where: For: f o = = Q = T BP 3 = T N = 0 Notch Output T BP = enter Frequency Gain T N = Passband Notch Gain f o =.0 khz Q = 0 T BP = T N = = = 60 k = 0.00 F =.6 M =.6 M 3 =.6 M Figure 7. Bi Quad Filter 7

8 , LM904S 3 V in V O O O = 0 = Given: f o = center frequency A(f o ) = gain at center frequency hoose value f o, = Triangle Wave Output f 3 75 k 00 k 300 k Square Wave Output Then: 3 = Q f o 3 = A(fo ) 3 = 4Q 3 For less than 0% error from operational amplifier. Where f o and BW are expressed in Hz. Q o f o BW < 0. f = 4 f if, 3 = If source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. Figure 8. Function Generator Figure 9. Multiple Feedback Bandpass Filter ODEING INFOMATION Device Operating Temperature ange Package Shipping NG 0 to 70 PDIP 8 (Pb Free) LM904SNG 40 to 05 PDIP 8 (Pb Free) 50 Units / ail 50 Units / ail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, BD80/D. 8

9 , LM904S PAKAGE DIMENSIONS PDIP 8 ASE ISSUE N NOTE 8 A D D b TOP VIEW e/ e SIDE VIEW A E B A A NOTE 3 L SEATING PLANE H eb 8X b END VIEW 0.00 M A M B M NOTE 6 E c END VIEW WITH LEADS ONSTAINED M NOTE 5 NOTES:. DIMENSIONING AND TOLEANING PE ASME Y4.5M, ONTOLLING DIMENSION: INHES. 3. DIMENSIONS A, A AND L AE MEASUED WITH THE PAK AGE SEATED IN JEDE SEATING PLANE GAUGE GS DIMENSIONS D, D AND E DO NOT INLUDE MOLD FLASH O POTUSIONS. MOLD FLASH O POTUSIONS AE NOT TO EXEED 0.0 INH. 5. DIMENSION E IS MEASUED AT A POINT 0.05 BELOW DATUM PLANE H WITH THE LEADS ONSTAINED PEPENDIULA TO DATUM. 6. DIMENSION E3 IS MEASUED AT THE LEAD TIPS WITH THE LEADS UNONSTAINED. 7. DATUM PLANE H IS OINIDENT WITH THE BOTTOM OF THE LEADS, WHEE THE LEADS EXIT THE BODY. 8. PAKAGE ONTOU IS OPTIONAL (OUNDED O SQUAE ONES). INHES MILLIMETES DIM MIN MAX MIN MAX A A A b b TYP.5 TYP D D E E e 0.00 BS.54 BS eb L M 0 0 ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ODEING INFOMATION LITEATUE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 807 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative /D