MC3403, MC3303. Single Supply Quad Operational Amplifiers

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1 , M0 Single Supply Quad Operational Amplifiers The is a low cost, quad operational amplifier with true differential inputs. The device has electrical characteristics similar to the popular M7. However, the has several distinct advantages over standard operational amplifier types in single supply applications. The quad amplifier can operate at supply voltages as low as.0 V or as high as 6 V with quiescent currents about one third of those associated with the M7 (on a per amplifier basis). The common mode input range includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage. Features Short ircuit Protected Outputs lass AB Output Stage for Minimal rossover Distortion True Differential Input Stage Single Supply Operation:.0 V to 6 V Split Supply Operation: ±.5 V to ±8 V Low Input Bias urrents: 500 na Max Four Amplifiers Per Package Internally ompensated Similar Performance to Popular M7 Industry Standard Pinouts ESD Diodes Added for Increased uggedness PbFree Packages are Available SOI D SUFFIX ASE 75A PDIP P SUFFIX ASE 66 x = or A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = PbFree Package MAKING DIAGAMS Mx0DG AWLYWW Mx0P AWLYYWWG PIN ONNETIONS Single Supply.0 V to 6 V V EE, GND Split Supplies.5 V to 8 V.5 V to 8 V V EE Out Inputs Inputs Out Inputs V EE /GND Inputs Out 7 8 Out (Top View) ODEING INFOMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor omponents Industries, LL, 0 January, 0 ev. Publication Order Number: /D

2 , M0 ODEING INFOMATION M0D M0DG Device Package Shipping SOI SOI (PbFree) 55 Units / ail M0D M0DG M0P M0PG D DG D DG SOI SOI (PbFree) PDIP PDIP (PbFree) SOI SOI (PbFree) SOI SOI (PbFree) 500 Tape & eel 5 Units / ail 55 Units / ail 500 Tape & eel P PG PDIP PDIP (PbFree) 5 Units / ail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, BD80/D. MAXIMUM ATINGS ating Symbol Value Unit Power Supply Voltages Single Supply Split Supplies 6, V EE ±8 Vdc Input Differential Voltage ange (Note ) V ID ±6 Vdc Input ommon Mode Voltage ange (Notes and ) V I ±8 Vdc Storage Temperature ange T stg 55 to 5 Operating Ambient Temperature ange M0 T A 0 to 85 0 to 70 Junction Temperature T J 50 Stresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating onditions is not implied. Extended exposure to stresses above the ecommended Operating onditions may affect device reliability.. Split power supplies.. For supply voltages less than ±8 V, the absolute maximum input voltage is equal to the supply voltage.

3 , M0 ELETIAL HAATEISTIS ( = 5 V, V EE = 5 V for ; = V, V EE = GND for M0 T A = 5, unless otherwise noted.) M0 haracteristic Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage T A = T high to T low (Note ) V IO mv Input Offset urrent I IO T A = T high to T low na Large Signal Open Loop Voltage Gain = ±0 V, L =.0 k T A = T high to T low A VOL V/mV Input Bias urrent I IB T A = T high to T low na Output Impedance f = 0 Hz z o Input Impedance f = 0 Hz z i M Output Voltage ange L = 0 k L =.0 k L =.0 k, T A = T high to T low ± ±0 ±0 Input ommon Mode Voltage ange V I V V EE ±.5 ± 0 0 V V V EE V EE.5 V.5 V V V EE ommon Mode ejection S 0 k M db Power Supply urrent ( = 0) L = I, I EE ma Individual Output Shortircuit urrent (Note ) I S ±0 ±0 ±5 ±0 ±0 ±5 ma Positive Power Supply ejection atio PS V/V Negative Power Supply ejection atio PS V/V Average Temperature oefficient of Input Offset urrent T A = T high to T low Average Temperature oefficient of Input Offset Voltage T A = T high to T low Power Bandwidth A V =, L = 0 k = 0 V(pp), THD = 5% SmallSignal Bandwidth A V =, L = 0 k = 50 mv I IO / T pa/ V IO / T 0 0 V/ BWp khz BW.0.0 MHz Slew ate A V =, V i = 0 V to 0 V S V/ s ise Time A V =, L = 0 k = 50 mv t TLH s Fall Time A V =, L = 0 k = 50 mv t TLH s Overshoot A V =, L = 0 k = 50 mv os 0 0 % Phase Margin A V =, L =.0 k, = 00 pf m rossover Distortion (V in = 0 mvpp,v out =.0 Vpp, f = 0 khz). M0: T low = 0, T high = 85, : T low = 0, T high = 70. Not to exceed maximum package power dissipation..0.0 %

4 , M0 ELETIAL HAATEISTIS ( = 5.0 V, V EE = GND, T A = 5, unless otherwise noted.) haracteristic Symbol M0 Min Typ Max Min Typ Max Input Offset Voltage V IO mv Input Offset urrent I IO na Input Bias urrent I IB na Large Signal Open Loop Voltage Gain L =.0 k Unit A VOL V/mV Power Supply ejection atio PS V/V Output Voltage ange (Note 5) V pp L = 0 k, = 5.0 V L = 0 k, V Power Supply urrent I ma hannel Separation f =.0 khz to 0 khz (Input eferenced) 5. Output will swing to ground with a 0 k pull down resistor. S 0 0 db Output Bias ircuitry ommon to Four Amplifiers Q0 Q9 Q8 Q7 Q6 Q7 Q 5.0 pf k 0 k Q8 Q9 Q Q5 Inputs Q Q.0 k Q9 Q 5 Q Q5 Q6 7 k Q Q Q0 Q Q Q Q5 60 k Q7 Q8 Q0. k V EE (GND) Figure. epresentative Schematic Diagram (/ of ircuit Shown)

5 , M0 IUIT DESIPTION 5.0 V/DIV 0 s/div Figure. Inverter Pulse esponse The /0 is made using four internally compensated, twostage operational amplifiers. The first stage of each consists of differential input device Q and Q with input buffer transistors Q5 and Q and the differential to single ended converter Q and Q. The first stage performs not only the first stage gain function but also performs the level shifting and Transconductance reduction functions. By reducing the Transconductance, a smaller compensation capacitor (only 5.0 pf) can be employed, thus saving chip area. The Transconductance reduction is accomplished by splitting the collectors of Q and Q. Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to singleended converter. The second stage consists of a standard current source load amplifier stage. The output stage is unique because it allows the output to swing to ground in single supply operation and yet does not exhibit any crossover distortion in split supply operation. This is possible because lass AB operation is utilized. Each amplifier is biased from an internal voltage regulator which has a low temperature coefficient, thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. 50 mv/div 0.5 V/DIV A V = 00 *Note lass A B output stage produces distortion less sinewave. 50 s/div A VOL, LAGE SIGNAL OPEN LOOP VOLTAGE GAIN (db) = 5 V V EE = 5 V T A = k 0 k 00 k.0 M f, FEQUENY (Hz) Figure. Sine Wave esponse Figure. Open Loop Frequency esponse, OUTPUT VOLTAGE (V pp ) T A = k 0 k 00 k.0 M f, FEQUENY (Hz) 5 V 5 V 0 k, OUTPUT VOLTAGE ANGE (V pp) T A = AND (V EE ), POWE SUPPLY VOLTAGES (V) Figure 5. Power Bandwidth Figure 6. Output Swing versus Supply Voltage 5

6 , M0 IIB, INPUT BIAS UENT (na) = 5 V V EE = 5 V T A = 5 I IB, INPUT BIAS UENT (na) T, TEMPEATUE ( ) Figure 7. Input Bias urrent versus Temperature AND (V EE ), POWE SUPPLY VOLTAGES (V) Figure 8. Input Bias urrent versus Supply Voltage 0 k 0 k / = = 0 k 50 k 5.0 k N9 / f = V o = N9 For: f o =.0 khz = 6 k = 0.0 F Figure 9. Voltage eference Figure 0. Wien Bridge Oscillator e e / a b / e o = ( a b) (e e ) / e o V in V inl = V inh = V h = / (L ) (H ) (H L ) Hysteresis H L V inl V inh Figure. High Impedance Differential Amplifier Figure. omparator with Hysteresis 6

7 , M0 00 k f o = V in / / 00 k / = Q = T BP = T N = 0 = = 60 k = 0.00 F =.6 M =.6 M =.6 M For: f oq T BP T N =.0 khz = 0 = = Where: T BP T N Bandpass Output = center frequency gain = passband notch gain / Figure. BiQuad Filter Notch Output = Triangle Wave Output 00 k / 75 k / 00 k V ref f = f f if = Figure. Function Generator Square Wave Output V in / Given: f o = center frequency A(f o ) = gain at center frequency hoose value f o, = Then: = Q = = f o A(f o ) Figure 5. Multiple Feedback Bandpass Filter O O = 0 5 Q 5 O For less than 0% error from operational amplifier o f o < 0. BW where f o and BW are expressed in Hz. If source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. 7

8 , M0 PAKAGE DIMENSIONS SOI ASE 75A0 ISSUE H T SEATING PLANE G A 8 D PL 7 B K P 7 PL 0.5 (0.00) M T B S A S 0.5 (0.00) M B M NOTES:. DIMENSIONING AND TOLEANING PE ANSI Y.5M, 98.. ONTOLLING DIMENSION: MILLIMETE.. DIMENSIONS A AND B DO NOT INLUDE MOLD POTUSION.. MAXIMUM MOLD POTUSION 0.5 (0.006) PE SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE 0.7 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATEIAL ONDITION. MILLIMETES INHES X 5 F DIM MIN MAX MIN MAX A B D M J F G.7 BS BS J K M P SOLDEING FOOTPINT* X X 7.0 X.5.7 PITH DIMENSIONS: MILLIMETES *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. 8

9 , M0 PAKAGE DIMENSIONS PDIP ASE 6606 ISSUE P 8 7 B NOTES:. DIMENSIONING AND TOLEANING PE ANSI Y.5M, 98.. ONTOLLING DIMENSION: INH.. DIMENSION L TO ENTE OF LEADS WHEN FOMED PAALLEL.. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. OUNDED ONES OPTIONAL. T N SEATING PLANE A INHES MILLIMETES DIM MIN MAX MIN MAX A B F L D F G 0.00 BS.5 BS H J K K J L M 0 0 H G D PL M N (0.005) M ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ODEING INFOMATION LITEATUE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 56, Denver, olorado 807 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative /D

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