RANGE ( C) PACKAGE ISL95810

Transcription

1 DSHEE ISL9581 Single Digitally ontrolled Potentiometer (XDP ) Low Noise, Low Power I 2 Bus, 256 aps FN89 Rev 2. he ISL9581 integrates a digitally controlled potentiometer (XDP) on a monolithic MOS integrated circuit. he digitally controlled potentiometer is implemented with a combination of resistor elements and MOS switches. he position of the wiper is controlled by the user through the I 2 bus interface. he potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. he content of the WR controls the position of the wiper. t power-up the device recalls the contents of the DP s IVR to the WR. he DP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Ordering Information PR NUMBER PR MRING R OL (k ) EMP RNGE ( ) PGE ISL9581WIU8* IU 1-4 to Ld MSOP ISL9581WIU8Z (Note) ISL9581WIR8Z* (Note) PN -4 to Ld MSOP (Pb-free) PO -4 to Ld 3 x 3 DFN (Pb-free) ISL9581UIU8* I 5-4 to Ld MSOP Features 256 resistor taps -.4% resolution I 2 serial interface Wiper resistance: 7 3.3V Non-volatile storage of wiper position Standby current 5µ max Power supply: 2.7V to 5.5V 5k, 1k total resistance High reliability - Endurance: 2, data changes per bit per register - Register data retention: Ld MSOP and 8 Ld DFN packaging Pb-free plus anneal available (RoHS compliant) Pinouts WP SL SD GND ISL9581 (8 LD MSOP) OP VIEW V RH RL RW ISL9581UIU8Z* (Note) O -4 to Ld MSOP (Pb-free) ISL9581UIR8 I -4 to Ld 3 x 3 DFN ISL9581UIR8Z* (Note) PP -4 to Ld 3 x 3 DFN (Pb-free) ISL9581 (8 LD DFN) OP VIEW *dd - suffix for tape and reel. NOE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD-2. WP SL SD GND V RH RL RW FN89 Rev 2. Page 1 of 13

2 Block Diagram V RH SD WIPER REGISER SL WP I 2 ND ONROL NON-VOLILE REGISER RW RL GND Pin Descriptions SSOP PIN SYMBOL DESRIPION 1 WP Hardware write protection. ctive low. Prevents any Write operation of the I 2 interface. 2 SL I 2 interface clock 3 SD Serial data I/O for the I 2 interface 4 GND Ground 5 RW Wiper terminal of the DP 6 RL Low terminal of the DP 7 RH High terminal of the DP 8 V Power supply FN89 Rev 2. Page 2 of 13

3 bsolute Maximum Ratings Storage emperature to +15 Voltage at ny Digital Interface Pin with Respect to V SS V to V +.3 V V to +6V Voltage at ny DP Pin with Respect to V SS V to V Lead emperature (Soldering, 1s) I W (1s) ±6m Recommended Operating onditions Industrial to +85 V V to 5.5V Power Rating of Each DP mW Wiper urrent of Each DP ±3.m UION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. his is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. nalog Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PRMEER ES ONDIIONS MIN YP (Note 1) MX UNI R OL R H to R L Resistance W, U versions respectively 1, 5 k R H to R L Resistance olerance % R W Wiper Resistance V = +25 Wiper current = V /R OL 7 2 H / L / W Potentiometer apacitance (Note 13) 1/1/25 pf I LkgDP Leakage on DP Pins (Note 13) Voltage at pin from GND to V.1 1 µ VOLGE DIVIDER MODE RL; RH; measured at RW, unloaded) INL (Note 6) Integral Non-Linearity -1 1 LSB (Note 2) DNL (Note 5) Differential Non-Linearity Monotonic over all tap positions W option LSB (Note 2) U option LSB (Note 2) ZSerror (Note 3) Zero-Scale Error W option 1 7 LSB (Note 2) U option.5 2 FSerror (Note 4) Full-Scale Error W option -7-1 LSB (Note 2) U option V (Note 7, 13) Ratiometric emperature oefficient DP Register set to 8 hex ±4 ppm/ RESISOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) Integral Non-Linearity DP register set between 2 hex and FF hex. Monotonic over all tap positions -1 1 MI (Note 8) RDNL (Note 5) Differential Non-Linearity DP register set between 2 hex W option MI (Note 8) and FF hex. Monotonic over all tap positions U option MI (Note 8) Roffset (Note 9) Offset W option 1 7 MI (Note 8) U option.5 2 MI (Note 8) R (Note 12, 13) Resistance emperature oefficient DP register set between 2 hex and FF hex ±45 ppm/ Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PRMEER ES ONDIIONS MIN I 1 (Note 15) V Supply urrent f SL = 4kHz; SD = Open; (for I 2, ctive, (Volatile write/read) Read and Volatile Write States only) I 2 (Note 15) V Supply urrent (Nonvolatile Write) f SL = 4kHz; SD = Open; (for I 2, ctive, Nonvolatile Write State only) YP (Note 1) MX UNIS 1 m 3 m I SB (Note 15) V urrent (Standby) V = +5.5V, I 2 Interface in Standby State 5 µ V = +3.6V, I 2 Interface in Standby State 2 µ FN89 Rev 2. Page 3 of 13

4 Operating Specifications YP SYMBOL PRMEER ES ONDIIONS MIN (Note 1) MX UNIS I LkgDig Leakage urrent, at Pins SD, SL, Voltage at pin from GND to V -1 1 µ and WP Pins t DP (Note 13) DP Wiper Response ime SL falling edge of last bit of DP Data Byte to wiper change 1 µs Vpor Power-On Recall Voltage Minimum V at which memory recall occurs V V Ramp V Ramp Rate.2 V/ms t D (Note 13) Power-Up Delay V above Vpor, to DP Initial Value Register recall completed, and I 2 Interface in standby state 3 ms EEPROM SPEIFIIONS EEPROM Endurance 2, ycles EEPROM Retention emperature 75 5 Years SERIL INERFE SPEIFIIONS V IL WP, SD, and SL Input Buffer LOW Voltage -.3.3*V V V IH WP, SD, and SL Input Buffer HIGH Voltage.7*V V +.3 V Hysteresis (Note 13) SD and SL Input Buffer Hysteresis.5*V V V OL (Note 13) SD Output Buffer LOW Voltage, Sinking 4m.4 V pin (Note 13) WP, SD, and SL Pin apacitance 1 pf f SL SL Frequency 4 khz t IN (Note 13) Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed. 5 ns t (Note 13) t BUF (Note 13) SL Falling Edge to SD Output Data Valid ime the Bus Must be Free Before the Start of a New ransmission SL falling edge crossing 3% of V, until SD exits the 3% to 7% of V window. SD crossing 7% of V during a SOP condition, to SD crossing 7% of V during the following SR condition. 9 ns 13 ns t LOW lock LOW ime Measured at the 3% of V crossing. 13 ns t HIGH lock HIGH ime Measured at the 7% of V crossing. 6 ns t SU:S SR ondition Setup ime SL rising edge to SD falling edge. Both crossing 7% of V. 6 ns t HD:S SR ondition Hold ime From SD falling edge crossing 3% of V to SL falling edge crossing 7% of V. 6 ns t SU:D Input Data Setup ime From SD exiting the 3% to 7% of V window, to SL rising edge crossing 3% of V 1 ns t HD:D Input Data Hold ime From SL rising edge crossing 7% of V to SD entering the 3% to 7% of V window. t SU:SO SOP ondition Setup ime From SL rising edge crossing 7% of V, to SD rising edge crossing 3% of V. t HD:SO t HD:SO:NV Over the recommended operating conditions unless otherwise specified. (ontinued) SOP ondition Hold ime for Read, or Volatile Only Write SOP ondition Hold ime for Non- Volatile Write From SD rising edge to SL falling edge. Both crossing 7% of V. From SD rising edge to SL falling edge. Both crossing 7% of V. t DH (Note 13) Output Data Hold ime From SL falling edge crossing 3% of V, until SD enters the 3% to 7% of V window. t R (Note 13) SD and SL Rise ime From 3% to 7% of V * b t F (Note 13) SD and SL Fall ime From 7% to 3% of V * b ns 6 ns 6 ns 2 µs ns 25 ns 25 ns b (Note 13) apacitive Loading of SD or SL otal on-chip and off-chip 1 4 pf FN89 Rev 2. Page 4 of 13

5 Operating Specifications Over the recommended operating conditions unless otherwise specified. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN Rpu (Note 13) SD and SL Bus Pull-Up Resistor Off-hip 1 k Maximum is determined by t R and t F. For b = 4pF, max is about 2~2.5k. For b = 4pF, max is about 15~2k YP (Note 1) MX UNIS t WP (Notes 13, 14) Non-Volatile Write ycle ime 12 2 ms t SU:WP WP Setup ime Before SR condition 6 ns t HD:WP WP Hold ime fter SOP condition 6 ns SD vs SL iming t F t HIGH t LOW t R SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) WP Pin iming SR SOP SL L 1 t HD:SO t HD:SO:NV SD IN t SU:WP t HD:WP WP NOES: 1. ypical values are for = +25 and 3.3V supply voltage. 2. LSB: [V(RW) 255 V(RW) ]/255. V(RW) 255 and V(RW) are V(RW) for the DP register set to FF hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = V(RW) /LSB. 4. FS error = [V(RW) 255 V ]/LSB. 5. DNL = [V(RW) i V(RW) i-1 ]/LSB-1, for i = 1 to 255. i is the DP register setting. 6. INL = [V(RW) i (i LSB V(RW) )]/LSB for i = 1 to 255. Max V RW i Min V RW i 1 7. V = for i = 16 to 24 decimal, = -4 to +85. Max( ) is the maximum value of the wiper Max V RW i + Min V RW i voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = R 255 R /255. R 255 and R are the measured resistances for the DP register set to FF hex and hex respectively. Roffset = R /MI, when measuring between RW and RL. 9. Roffset = R 255 /MI, when measuring between RW and RH. 1. RDNL = (R i R i-1 )/MI, for i = 32 to RINL = [R i (MI i) R ]/MI, for i = 32 to 255. Max Ri Min Ri R = for i = 32 to 255, = -4 to +85. Max( ) is the maximum value of the resistance and Min ( ) is the Max Ri + Min Ri minimum value of the resistance over the temperature range. 13. his parameter is not 1% tested. 14. t W is the minimum cycle time to be allowed for any non-volatile Write by the user, unless cknowledge Polling is used. It is the time from a valid SOP condition at the end of a Write sequence of a I 2 serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. V IL = V, V IH = V FN89 Rev 2. Page 5 of 13

6 ypical Performance urves WIPER RESISNE ( ) V = 2.7, = 85 V = 2.7, = -4 V = 2.7, = 25 2 V = 5.5, = -4 V = 5.5, = 85 V = 5.5, = P POSIION (DEIML) FIGURE 1. WIPER RESISNE vs P POSIION [ I(RW) = V / R OL ] for 5k (U) SNDBY I (µ) V (V) FIGURE 2. SNDBY I vs V.2.15 V = 5.5, = -4 V = 2.7, = 25 V = 2.7, = V = 2.7, = -4 V = 5.5, = -4 V = 5.5, = 85 DNL (LSB) V = 5.5, = 25 INL (LSB) V = 2.7, = 25 V = 2.7, = 85 V = 5.5, = V = 2.7, = 85 V = 5.5, = P POSIION (DEIML) FIGURE 3. DNL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W) P POSIION (DEIML) FIGURE 4. INL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W) ZSerror (LSB) V V EMPERURE ( ) FIGURE 5. ZSerror vs EMPERURE FSerror (LSB) V = 5.5V V = 2.7V EMPERURE ( ) FIGURE 6. FSerror vs EMPERURE FN89 Rev 2. Page 6 of 13

7 ypical Performance urves (ontinued) DNL (LSB) V = 5.5, = 25 V = 2.7, = 25 V = 5.5, = 85 V V = 2.7, = -4 = 2.7, = 85 V = 5.5, = P POSIION (DEIML) FIGURE 7. DNL vs P POSIION IN RHEOS MODE FOR 5k (U) INL (LSB) V = 2.7, = 25 V = 5.5, = -4 V = 5.5, = V = 2.7, = V = 5.5, = 25 V = 2.7, = P POSIION (DEIML) FIGURE 8. INL vs P POSIION IN RHEOS MODE FOR 5k (U) END O END R OL HNGE (%) V 2.7V EMPERURE ( ) FIGURE 9. END O END R OL % HNGE vs EMPERURE (ppm/ ) P POSIION (DEIML) FIGURE 1. FOR VOLGE DIVIDER MODE IN ppm INPU (ppm/ ) OUPU P POSIION (DEIML) FIGURE 11. FOR RHEOS MODE IN ppm ap Position = Mid Point R OL = 9.4 FIGURE 12. FREQUENY RESPONSE (2.2MHz) FN89 Rev 2. Page 7 of 13

8 ypical Performance urves (ontinued) Signal at Wiper (Wiper Unloaded) SL Signal at Wiper (Wiper Unloaded Movement From ffh to h) Wiper Movement Mid Point From 8h to 7fh FIGURE 13. MIDSLE GLIH, ODE 8h to 7Fh (WIPER ) FIGURE 14. LRGE SIGNL SELING IME Principles of Operation he ISL9581 is an integrated circuit incorporating one DP with its associated registers, non-volatile memory, and a I 2 serial interface providing direct communication between a host and the potentiometer and memory. DP Description he DP is implemented with a combination of resistor elements and MOS switches. he physical ends of the DP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). he RW pin of the DP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. he position of the wiper terminal within the DP is controlled by an 8-bit volatile Wiper Register (WR). he DP has its own WR. When the WR of the DP contains all zeroes (WR<7:>: h), its wiper terminal (RW) is closest to its Low terminal (RL). When the WR of the DP contains all ones (WR<7:>: FFh), its wiper terminal (RW) is closest to its High terminal (RH). s the value of the WR increases from all zeroes (h) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. t the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL9581 is being powered up, he WR is reset to 8h (128 decimal), which locates RW roughly at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading, the ISL9581 reads the value stored in non-volatile Initial Value Registers (IVRs) and loads it into the WR. he WR and IVR can be read or written directly using the I 2 serial interface as described in the following sections. Memory Description he ISL9581 volatile and non-volatile registers are accessed by I 2 interface operations at addresses and 2 decimal. he non-volatile byte at addresses contains the initial value loaded at power-up into the volatile Wiper Register (WR) of the DP. he byte at address 1 is reserved; the user should not write to it, and its value should be ignored if read. he volatile WR, and the non-volatile Initial Value Register (IVR) of the DP are accessed with the same ddress Byte, set to hex in both cases. volatile byte at address 2 decimal, controls what byte is read or written when accessing DP registers: the WR, the IVR, or both. When the byte at address 2 is all zeroes, which is the default at power-up: read operation to addresses outputs the value of the non-volatile IVR. write operation to addresses writes the same value to the WR and IVR of the corresponding DP. When the byte at address 2 is 8h (128 decimal): read operation to addresses outputs the value of the volatile WR. write operation to addresses only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. h and 8h are the only values that should be written to address 2. ll other values are reserved and must not be written to address 2. FN89 Rev 2. Page 8 of 13

9 he ISL9581 is pre-programed with 8h in the IVR. WR: Wiper Register, IVR: Initial value Register. I 2 Serial Interface he ISL9581 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master always initiates data transfers and provides the clock for both transmit and receive operations. herefore, the ISL9581 operates as a slave device in all applications. ll communication over the I 2 interface is conducted by sending the MSB of each byte of data first. Protocol onventions BLE 1. MEMORY MP DDRESS NON-VOLILE VOLILE 2 - ccess ontrol 1 Reserved IVR WR Data states on the SD line can change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating SR and SOP conditions (See Figure 15). On power-up of the ISL9581 the SD pin is in the input mode. ll I 2 interface operations must begin with a SR condition, which is a HIGH to LOW transition of SD while SL is HIGH. he ISL9581 continuously monitors the SD and SL lines for the SR condition and does not respond to any command until this condition is met (See Figure 15). SR condition is ignored during the powerup sequence and during internal non-volatile write cycles. ll I 2 interface operations must be terminated by a SOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (See Figure 15). SOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. SOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. he device enters its standby state when the internal non-volatile write cycle is completed. n, cknowledge, is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the SD bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the eight bits of data (See Figure 16). he ISL9581 responds with an after recognition of a SR condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. he ISL9581 also responds with an after receiving a Data Byte of a write operation. he master must respond with an after receiving a Data Byte of a read operation. valid Identification Byte contains 11 as the seven MSBs. he LSB in the Read/Write bit. Its value is 1 for a Read operation, and for a Write operation (See able 2). BLE 2. IDENIFIION BYE FORM 1 1 R/W (MSB) (LSB) SL SD SR D D D SOP SBLE HNGE SBLE FIGURE 15. VLID D HNGES, SR, ND SOP ONDIIONS FN89 Rev 2. Page 9 of 13

10 SL FROM MSER SD OUPU FROM RNSMIER HIGH IMPEDNE SD OUPU FROM REEIVER HIGH IMPEDNE SR FIGURE 16. NOWLEDGE RESPONSE FROM REEIVER WRIE SIGNLS FROM HE MSER S R IDENIFIION BYE DDRESS BYE D BYE S O P SIGNL SD 1 1 SIGNLS FROM HE ISL9581 FIGURE 17. BYE WRIE SEQUENE SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W= DDRESS BYE S R IDENIFIION BYE WIH R/W=1 S O P SIGNL SD SIGNLS FROM HE SLVE FIRS RED D BYE LS RED D BYE FIGURE 18. RED SEQUENE FN89 Rev 2. Page 1 of 13

11 Write Operation Write operation requires a SR condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a SOP condition. fter each of the three bytes, the ISL9581 responds with an. t this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to nonvolatile memory, the ISL9581 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SD and SL pins, and the SD output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL9581 enters its standby state (See Figure 17). he byte at address 2h determines if the Data Byte is to be written to volatile and/or non-volatile memory (See Memory Description on page 8). Read Operation Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). he master initiates the operation issuing the following sequence: a SR, the Identification byte with the R/W bit set to, an ddress Byte, a second SR, and a second Identification byte with the R/W bit set to 1. fter each of the three bytes, the ISL9581 responds with an. hen the ISL9581 then transmits the Data Byte. he master then terminates the read operation (issuing a SOP condition) following the last bit of the Data Byte (See Figure 18). he byte at address 2h determines if the Data Bytes being read are from volatile or non-volatile memory (See Memory Description on page 8.) Data Protection he WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW) the device ignores Data Bytes of a Write Operation, does not respond to the Data Bytes with an, and instead, goes to its standby state waiting for a new SR condition. SOP condition also acts as a protection of non-volatile memory. valid Identification Byte, ddress Byte, and total number of SL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the ddress Byte is or 2, the Data Byte is transferred to the Wiper Register (WR) or to the ccess ontrol Register respectively, at the falling edge of the SL pulse that loads the last bit (LSB) of the Data Byte. If the ddress Byte is, and the ccess ontrol Register is all zeros (default), then the SOP condition initiates the internal write cycle to non-volatile memory. opyright Intersil mericas LL ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN89 Rev 2. Page 11 of 13

12 Mini Small Outline Plastic Packages (MSOP) INDEX RE 1 2 N 1 2 OP VIEW e D b SIDE VIEW E1 GUGE PLNE SEING PLNE.25 (.1) 4X 4X NOES: 1. hese package dimensions are within allowable dimensions of JEDE MO-187B. 2. Dimensioning and tolerancing per NSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed.15mm (.6 inch) per side. 5. Formed leads shall be planar with respect to one another within.1mm (.4) at seating Plane. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. erminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. llowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch). 1. Datums - - and - B - to be determined at Datum plane - H ontrolling dimension: MILLIMEER. onverted inch dimensions are for reference only. E.2 (.8) B.1 (.4).2 (.8) a SEING PLNE.2 (.8) D L1 L E 1 R1 R L END VIEW -- -B- -- -H- -B- M8.118 (JEDE MO-187) 8 LED MINI SMLL OULINE PLSI PGE INHES MILLIMEERS SYMBOL MIN MX MIN MX NOES b c D E e.26 BS.65 BS - E L L1.37 REF.95 REF - N R R o 15 o 5 o 15 o - o 6 o o 6 o - Rev. 2 1/3 FN89 Rev 2. Page 12 of 13

13 hin Dual Flat No-Lead Plastic Package (DFN) 6 INDEX RE (DUM ) 6 INDEX RE (DUM B) NX L 8 SEING PLNE 1 2 N D OP VIEW SIDE VIEW N-1 e D2 D2/2 (Nd-1)Xe REF. BOOM VIEW 7 2X.15 L E B E2 E2/2 NX b.1 2X.15 B NX k //.1.8 M B L8.3x3B 8 LED HIN DUL FL NO-LED PLSI PGE MILLIMEERS SYMBOL MIN NOMINL MX NOES REF - b , 8 D 3. BS - D , 8 E 3. BS - E , 8 e.65 BS - k L N 8 2 Nd 4 3 Rev. 6/4 NOES: 1. Dimensioning and tolerancing conform to SME Y N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. ll dimensions are in millimeters. ngles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. 6. he configuration of the pin #1 identifier is optional, but must be located within the zone indicated. he pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil echnical Brief B389. NX (b) 5 (1) L SEION "-" ERMINL IP e FOR EVEN ERMINL/SIDE FN89 Rev 2. Page 13 of 13