Features TEMP. RANGE ( C) R TOTAL (k )

Transcription

1 NO REOMMENDED FOR NEW DESIGNS REOMMENDED REPLEMEN: ISL9581 I 2 Bus, 256 aps, 5 Bytes General Purpose Memory, Low Noise, Low Power DSHEE FN6759 Rev 1. Single Digitally ontrolled Potentiometer (XDP ) he ISL95811 integrates a digitally controlled potentiometer (XDP) and non-volatile memory on a monolithic MOS integrated circuit. he digitally controlled potentiometer is implemented with a combination of resistor elements and MOS switches. he position of the wiper is controlled by the user through the I 2 bus interface. he potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. he content of the WR controls the position of the wiper. t power-up the device recalls the contents of the DP s IVR to the WR. he DP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing. Pinouts ISL95811 (8 LD MSOP) OP VIEW ISL95811 (8 LD DFN) OP VIEW Features 256 Resistor aps -.4% Resolution I 2 Serial Interface 5 General Purpose Non-Volatile Bytes Non-volatile Storage of Wiper Position Write Protection Wiper Resistance: 7 V = 3.3V Standby urrent 1µ Max Power Supply: 2.7V to 5.5V 5k, 1k otal Resistance High Reliability - Endurance: 1,, Data hanges per Bit per Register - Register Data Retention: Ld MSOP and 8 Ld DFN Packaging Pb-Free (RoHS compliant) WP SL SD GND V RH RL RW WP SL SD GND V RH RL RW Ordering Information PR NUMBER (Note) PR MRING R OL (k ) EMP. RNGE ( ) PGE (Pb-Free) PG. DWG. # ISL95811WFUZ 5811W 1-4 to Ld MSOP MDP43 ISL95811WFUZ-* 5811W 1-4 to Ld MSOP MDP43 ISL95811WFUZ-* 5811W 1-4 to Ld MSOP MDP43 ISL95811WFRZ 811W 1-4 to Ld 3x3 DFN L8.3x3 ISL95811WFRZ-* 811W 1-4 to Ld 3x3 DFN L8.3x3 ISL95811UFUZ 5811U 5-4 to Ld MSOP MDP43 ISL95811UFUZ-* 5811U 5-4 to Ld MSOP MDP43 ISL95811UFUZ-* 5811U 5-4 to Ld MSOP MDP43 ISL95811UFRZ 811U 5-4 to Ld 3x3 DFN L8.3x3 ISL95811UFRZ-* 811U 5-4 to Ld 3x3 DFN L8.3x3 *Please refer to B347 for details on reel specifications NOE: hese Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 1% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD-2. FN6759 Rev 1. Page 1 of 14

2 Block Diagram V RH SD WIPER REGISER SL WP I 2 ND ONROL NON-VOLILE REGISER RW RL GND Pin Descriptions MSOP PIN NUMBER DFN PIN NUMBER SYMBOL DESRIPION 1 1 WP Hardware write protection. ctive low. Prevents any Write operation of the I 2 interface. 2 2 SL I 2 interface input clock 3 3 SD Open Drain Serial Data I/O for the I 2 interface 4 4 GND Ground 5 5 RW Wiper terminal of the DP 6 6 RL Low terminal of the DP 7 7 RH High terminal of the DP 8 8 V Power supply EPD* Exposed Die Pad internally connected to GND *NOE: PB thermal land for QFN/DFN EPD should be connected to GND plane or left floating. For more information refer to FN6759 Rev 1. Page 2 of 14

3 bsolute Maximum Ratings Voltage at any Digital Interface Pin with respect to GND V to V +.3V V V to +6.V Voltage at any DP Pin with respect to GND V to V I W (1s) ±6m ESD Rating Human Body Model kV hermal Information hermal Resistance (ypical) J ( /W) J ( /W) 8 Ld DFN (Notes 1, 2) Ld MSOP (Note 1) N/ Maximum Junction emperature (Plastic Package) Storage emperature to +15 Latchup (Note 3) lass II, Level +125 Pb-Free Reflow Profile see link below Recommended Operating onditions emperature Range (Extended Industrial) to +125 V V to 5.5V Power Rating mW Wiper urrent ±3.m UION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOES: 1. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See ech Brief B379 for details. 2. For J, the case temp location is the center of the exposed metal pad on the package underside. 3. Jedec lass II pulse conditions and failure criterion used. Level B exceptions is using a max positive pulse of 6.5V on the WP pin. nalog Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PRMEER ES ONDIIONS MIN (Note 18) YP (Note 4) MX (Note 18) UNI R OL R H to R L Resistance R OL = (V RH - V RL )/I DP W option 1 k U option 5 k R H to R L Resistance olerance % R W Wiper Resistance V = +25 Wiper current = V /R OL 7 2 R Wnoise (Note 16) Noise Level Wiper at the middle scale, 1kHz 1V RMS input to RH pin -11 dbv H / L / W (Note 16) Potentiometer apacitance 1/1/25 pf I LkgDP Leakage on DP Pins Voltage at pin from GND to V.1 1 µ VOLGE DIVIDER MODE RL; RH; measured at RW, unloaded) INL (Note 9) Integral Non-Linearity DP register set between 1 hex and FFhex. Monotonic over all tap positions. W and U options -1 1 LSB (Note 5) DNL (Note 8) Differential Non-Linearity DP register set between 1 hex and FF hex. Monotonic over all tap positions W option LSB U option (Note 5) ZSerror (Note 6) Zero-Scale Error W option 1 5 LSB U option.5 2 (Note 5) FSerror (Note 7) Full-Scale Error W option -5-1 LSB U option (Note 5) V (Note 1, 16) Ratiometric emperature oefficient DP Register set to 8 hex ±4 ppm/ f UOFF (Note 16) 3dB ut-off Frequency Wiper at the middle scale W option 125 khz U option 25 khz FN6759 Rev 1. Page 3 of 14

4 nalog Specifications Over recommended operating conditions unless otherwise stated. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN (Note 18) YP (Note 4) MX (Note 18) UNI RESISOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) Integral Non-Linearity DP register set between 1 hex and FF hex. Monotonic over all tap positions. RDNL (Note 13) Differential Non-Linearity DP register set between 1 hex and FF hex. Monotonic over all tap positions W option -3 3 MI (Note 11) U option -1 1 MI (Note 11) W option MI (Note 11) U option MI (Note 11) R offset (Note 12) Offset W option 1 5 MI (Note 11) U option.5 2 MI (Note 11) R (Note 15, 16) Resistance emperature oefficient DP register set between 2 hex and FF hex ±45 ppm/ Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PRMEER ES ONDIIONS MIN (Note 18) YP (Note 4) MX (Note 18) UNIS I 1 V Supply urrent (Volatile Write/Read) f SL = 4kHz; SD = Open; (for I 2, ctive, Read and Volatile Write States only) 1 µ I 2 V Supply urrent (Non-volatile Write) f SL = 4kHz; SD = Open; (for I 2, ctive, Non-volatile Write State only) 2 m I SB V urrent (Standby) V = +5.5V, I 2 Interface in Standby State 1 µ V = +3.6V, I 2 Interface in Standby State 5 µ I LkgDig Leakage urrent, at Pins SD, SL, and WP Pins Voltage at pin from GND to V -1 1 µ t DP DP Wiper Response ime SL falling edge of last bit of DP Data Byte to wiper change 1 µs Vpor Power-On Recall Voltage Minimum V at which memory recall occurs V V Ramp V Ramp Rate.2 V/ms t D Power-Up Delay V above V POR, to DP Initial Value Register recall completed, and I 2 Interface in standby state 3 ms EEPROM SPEIFIIONS EEPROM Endurance 1,, ycles EEPROM Retention emperature 55 5 Years SERIL INERFE SPEIFIIONS V IL WP, SD, and SL Input Buffer LOW Voltage -.3.3*V V V IH WP, SD, and SL Input Buffer HIGH Voltage.7*V V +.3 V Hysteresis (Note 16) SD and SL Input Buffer Hysteresis.5*V V V OL SD Output Buffer LOW Voltage, Sinking 4m.4 V pin (Note 16) WP, SD, and SL Pin apacitance 1 pf FN6759 Rev 1. Page 4 of 14

5 Operating Specifications Over the recommended operating conditions unless otherwise specified. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN (Note 18) YP (Note 4) MX (Note 18) UNIS f SL SL Frequency 4 khz t IN Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed. 5 ns t SL Falling Edge to SD Output Data Valid SL falling edge crossing 3% of V, until SD exits the 3% to 7% of V window. 9 ns t BUF ime the Bus Must be Free Before the Start of a New ransmission SD crossing 7% of V during a SOP condition, to SD crossing 7% of V during the following SR condition. 13 ns t LOW lock LOW ime Measured at the 3% of V crossing. 13 ns t HIGH lock HIGH ime Measured at the 7% of V crossing. 6 ns t SU:S SR ondition Setup ime SL rising edge to SD falling edge. Both crossing 7% of V. t HD:S SR ondition Hold ime From SD falling edge crossing 3% of V to SL falling edge crossing 7% of V. t SU:D Input Data Setup ime From SD exiting the 3% to 7% of V window, to SL rising edge crossing 3% of V t HD:D Input Data Hold ime From SL rising edge crossing 7% of V to SD entering the 3% to 7% of V window. t SU:SO SOP ondition Setup ime From SL rising edge crossing 7% of V, to SD rising edge crossing 3% of V. 6 ns 6 ns 1 ns ns 6 ns t HD:SO SOP ondition Hold ime for Read, or Volatile Only Write From SD rising edge to SL falling edge. Both crossing 7% of V. 6 ns t HD:SO:NV SOP ondition Hold ime for Non- Volatile Write From SD rising edge to SL falling edge. Both crossing 7% of V. 2 µs t DH Output Data Hold ime From SL falling edge crossing 3% of V, until SD enters the 3% to 7% of V window. ns t R (Note 16) SD and SL Rise ime From 3% to 7% of V * b t F (Note 16) SD and SL Fall ime From 7% to 3% of V * b 25 ns 25 ns b (Note 16) apacitive Loading of SD or SL otal on-chip and off-chip 1 4 pf Rpu (Note 16) SD and SL Bus Pull-Up Resistor Off-hip Maximum is determined by t R and t F. For b = 4pF, max is about 2k ~2.5k. For b = 4pF, max is about 15k ~2k 1 k t W (Note 17) Non-Volatile Write ycle ime 12 2 ms t SU:WP WP Setup ime Before SR condition 6 ns t HD:WP WP Hold ime fter SOP condition 6 ns NOES: 4. ypical values are for = +25 and 3.3V supply voltage. 5. LSB: [V(RW) 255 V(RW) ]/255. V(RW) 255 and V(RW) are V(RW) for the DP register set to FF hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW) /LSB. 7. FS error = [V(RW) 255 V ]/LSB. 8. DNL = [V(RW) i V(RW) i-1 ]/LSB-1, for i = 1 to 255. i is the DP register setting. FN6759 Rev 1. Page 5 of 14

6 NOES: (continued) 9. INL = [V(RW) i (i LSB V(RW) )]/LSB for i = 1 to 255. Max V RW i Min V RW i 1 1. V = for i = 16 to 24 decimal, = -4 to Max( ) is the maximum value of the wiper Max V RW i + Min V RW i voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = R 255 R /255. R 255 and R are the measured resistances for the DP register set to FF hex and hex respectively. R offset = R /MI, when measuring between RW and RL. 12. R offset = R 255 /MI, when measuring between RW and RH. 13. RDNL = (R i R i-1 )/MI, for i = 16 to RINL = [R i (MI i) R ]/MI, for i = 16 to 255. Max Ri Min Ri R = for i = 32 to 255, = -4 to Max( ) is the maximum value of the resistance and Min ( ) is Max Ri + Min Ri the minimum value of the resistance over the temperature range. 16. Limits established by characterization and are not production tested. 17. t W is the time from a valid SOP condition at the end of a Write sequence of a I 2 serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. he cknowledge Polling method can be used to determine the end of the non-volatile write cycle. 18. Parameters with MIN and/or MX limits are 1% tested at +25, unless otherwise specified. emperature limits established by characterization and are not production tested. SD vs SL iming t F t HIGH t LOW t R tw SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) WP Pin iming SR SOP SL L 1 t HD:SO t HD:SO:NV SD IN t SU:WP t HD:WP WP FN6759 Rev 1. Page 6 of 14

7 ypical Performance urves WIPER RESISNE ( ) = -4 = +25 = = -4 = +25 = P POSIION (DEIML) FIGURE 1. WIPER RESISNE vs P POSIION [I(RW) = V /R OL ] FOR 1k (W) SNDBY I (µ) = +25 = SUPPLY VOLGE (V) FIGURE 2. SNDBY I vs V = -4.5 = = DNL (LSB) INL (LSB) P POSIION (DEIML) FIGURE 3. DNL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W) P POSIION (DEIML) FIGURE 4. INL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W).5.25 = = +25 RDNL (MI) RINL (MI) P POSIION (DEIML) FIGURE 5. RDNL vs P POSIION IN RHEOS MODE FOR 1k (W) P POSIION (DEIML) FIGURE 6. RINL vs P POSIION IN RHEOS MODE FOR 1k (W) FN6759 Rev 1. Page 7 of 14

8 ypical Performance urves (ontinued) 2. ZERO SLE ERROR (LSB) FULL SLE ERROR (LSB) EMPERURE ( ) FIGURE 7. ZSerror vs EMPERURE EMPERURE ( ) FIGURE 8. FSerror vs EMPERURE.2.1 = = +25 DNL (LSB) -.1 INL (LSB) P POSIION (DEIML) FIGURE 9. DNL vs P POSIION IN RHEOS MODE FOR 5k (U) P POSIION (DEIML) FIGURE 1. INL vs P POSIION IN RHEOS MODE FOR 5k (U).2 = = RDNL (MI) RINL (MI) P POSIION (DEIML) FIGURE 11. RDNL vs P POSIION IN RHEOS MODE FOR 5k (U) P POSIION (DEIML) FIGURE 12. RINL vs P POSIION IN RHEOS MODE FOR 5k (U) FN6759 Rev 1. Page 8 of 14

9 ypical Performance urves (ontinued) = -4 O = -4 O +125 r (ppm/ ) 15 1 v (ppm/ ) P POSIION (DEIML) FIGURE 13. r FOR RHEOS MODE 1k (W) IN ppm P POSIION (DEIML) FIGURE 14. v FOR VOLGE DIVIDER MODE 1k (W) IN ppm END-O-END R OL HNGE (%) EMPERURE ( ) FIGURE 15. END-O-END R OL % HNGE vs EMPERURE, 1k (W) END-O-END R OL HNGE (%) EMPERURE ( ) FIGURE 16. END-O-END R OL % HNGE vs EMPERURE, 5k (U) Pin Description Potentiometers Pins RH ND RL he high (RH) and low (RL) terminals of the ISL95811 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to, the wiper is closest to RL. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. he position of the wiper within the array is determined by the WR register. Bus Interface Pins SERIL D INPU/OUPU (SD) he SD is a bidirectional serial data input/output pin for I 2 interface. It receives device address, operation code, wiper address and data from an I 2 external master device at the rising edge of the serial clock SL, and it shifts out data after each falling edge of the serial clock. SD requires an external pull-up resistor, since it is an open drain input/output. SERIL LO (SL) his input is the serial clock of the I 2 serial interface. SL requires an external pull-up resistor. WRIE PROE (WP) When this pin is kept LOW, the data is written to the device will be ignored. his pin protects the non-volatile memory from being overwritten. Principles of Operation he ISL95811 is an integrated circuit incorporating one DP with its associated registers, non-volatile memory and an I 2 serial interface providing direct communication between a host and the potentiometer and memory. he resistor array is comprised of individual resistors connected in series. t FN6759 Rev 1. Page 9 of 14

10 either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. he electronic switches on the device operate in a make before break mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR are recalled and loaded into the WR to set the wiper to the initial value. DP Description he DP is implemented with a combination of resistor elements and MOS switches. he physical ends of each DP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). he RW pin of the DP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. he position of the wiper terminal within the DP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DP contains all zeroes (WR[7:] = h), its wiper terminal (RW) is closest to its Low terminal (RL). When the WR register of a DP contains all ones (WR[7:] = FFh), its wiper terminal (RW) is closest to its High terminal (RH). s the value of the WR increases from all zeroes () to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. t the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95811 is being powered up, the WR is reset to 8h (128 decimal), which locates RW roughly at the center between RL and RH. fter the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reloaded with the value stored in a non-volatile Initial Value Register (IVR). he WR and IVR can be read or written to directly using the I 2 serial interface, as described in the following sections. Memory Description he ISL95811 contains one non-volatile 8-bit Initial Value Register (IVR), five General Purpose non-volatile 8-bit registers and two volatile 8-bit registers: Wiper Register (WR) and ccess ontrol Register (R). he Memory map of the ISL95811 is shown in able 1. he non-volatile register (IVR) at address contains the initial wiper position and the volatile register (WR) contains the current wiper position. he ISL95811 is pre-programed with 8h in the IVR. he non-volatile IVR and volatile WR registers are accessible with the same address. he ccess ontrol Register (R) contains information and control bits described in able 2. he VOL bit (R[7]) determines whether the access to wiper registers WR or initial value registers IVR. If VOL bit is, the non-volatile IVR register and General Purpose registers are accessible. If VOL bit is 1, only the volatile WR is accessible. Note: Value written to the IVR register is also written to the WR. he default value of this bit is. he Device ID register is read only and it contains chip revision information, as shown in able 3. I 2 Serial Interface BLE 1. MEMORY MP DDRESS (hex) NON-VOLILE VOLILE 8 N R 7 Reserved 6 General Purpose N/ 5 General Purpose N/ 4 General Purpose N/ 3 General Purpose N/ 2 General Purpose N/ 1 Device ID (read only) N/ IVR WR BLE 2. ESS ONROL REGISER (R) BI # NME VOL BLE 3. DEVIE ID REGISER BI # VLUE 1 he ISL95811 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master always initiates data transfers and provides the clock for both transmit and receive operations. herefore, the ISL95811 operates as a slave device in all applications. ll communication over the I 2 interface is conducted by sending the MSB of each byte of data first. FN6759 Rev 1. Page 1 of 14

11 Protocol onventions Data states on the SD line can change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating SR and SOP conditions (see Figure 17). On power-up of the ISL95811, the SD pin is in the input mode. ll I 2 interface operations must begin with a SR condition, which is a HIGH to LOW transition of SD while SL is HIGH. he ISL95811 continuously monitors the SD and SL lines for the SR condition and does not respond to any command until this condition is met (see Figure 17). SR condition is ignored during the power-up sequence and during internal non-volatile write cycles. ll I 2 interface operations must be terminated by a SOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (see Figure 17). SOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. SOP condition during a write operation to a non-volatile byte initiates an internal non-volatile write cycle. he device enters its standby state when the internal non-volatile write cycle is completed. n, cknowledge, is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the SD bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the 8 bits of data (see Figure 18). he ISL95811 responds with an after recognition of a SR condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. he ISL95811 also responds with an after receiving a Data Byte of a write operation. he master must respond with an after receiving a Data Byte of a read operation. valid Identification Byte contains 11 as the seven MSBs. he LSB is the Read/Write bit. Its value is 1 for a Read operation and for a Write operation (see able 4). BLE 4. IDENIFIION BYE FORM 1 1 R/W (MSB) (LSB) SL SD SR D D D SOP SBLE HNGE SBLE FIGURE 17. VLID D HNGES, SR, ND SOP ONDIIONS SL FROM MSER SD OUPU FROM RNSMIER HIGH IMPEDNE SD OUPU FROM REEIVER HIGH IMPEDNE SR FIGURE 18. NOWLEDGE RESPONSE FROM REEIVER FN6759 Rev 1. Page 11 of 14

12 WRIE SIGNLS FROM HE MSER S R IDENIFIION BYE DDRESS BYE D BYE S O P SIGNL SD 1 1 SIGNLS FROM HE ISL95811 FIGURE 19. BYE WRIE SEQUENE SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W = DDRESS BYE S R IDENIFIION BYE WIH R/W = 1 S O P SIGNL SD SIGNLS FROM HE SLVE FIRS RED D BYE LS RED D BYE FIGURE 2. RED SEQUENE Write Operation Write operation requires a SR condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a SOP condition. fter each of the three bytes, the ISL95811 responds with an. t this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to nonvolatile memory, the ISL95811 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SD and SL pins, and the SD output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95811 enters its standby state (see Figure 19). he byte at address 8h determines if the Data Byte is to be written to volatile and/or non-volatile memory (see Memory Description on page 1). Data Protection he WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW), the device ignores Data Bytes of a Write Operation and does not respond to the Data Bytes with an ; rather it goes into standby state waiting for a new SR condition. ddress Byte is or 8, the Data Byte is transferred to the Wiper Register (WR) or to the ccess ontrol Register respectively, at the falling edge of the SL pulse that loads the last bit (LSB) of the Data Byte. If the ddress Byte is, and the ccess ontrol Register is all zeros (default), then the SOP condition initiates the internal write cycle to non-volatile memory. Read Operation Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 2). he master initiates the operation issuing the following sequence: a SR, the Identification byte with the R/W bit set to, an ddress Byte, a second SR, and a second Identification byte with the R/W bit set to 1. fter each of the three bytes, the ISL95811 responds with an. he ISL95811 then transmits the Data Byte and the master then terminates the read operation (issuing a SOP condition) following the last bit of the Data Byte. he byte at address 8h determines if the Data Bytes being read are from volatile or non-volatile memory (see Memory Description on page 1). SOP condition also acts as a protection of non-volatile memory. valid Identification Byte, ddress Byte, and total number of SL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the FN6759 Rev 1. Page 12 of 14

13 Mini SO Package Family (MSOP).25 M B D (N/2)+1 N MDP43 MINI SO PGE FMILY MILLIMEERS SYMBOL MSOP8 MSOP1 OLERNE NOES Max ±.5 - E E1 PIN #1 I.D ±.9 - b /-.8 - c ±.5 - B 1 (N/2) D ±.1 1, 3 E ±.15 - E ±.1 2, 3 e H e.65.5 Basic - L ±.15 - SEING PLNE.1 N LEDS c L1 b SEE DEIL "X".8 M B L Basic - N 8 1 Reference - Rev. D 2/7 NOES: 1. Plastic or metal protrusions of.15mm maximum per side are not included. 2. Plastic interlead protrusions of.25mm maximum per side are not included. 3. Dimensions D and E1 are measured at Datum Plane H. 4. Dimensioning and tolerancing per SME Y14.5M GUGE PLNE.25 1 L DEIL X 3 ±3 FN6759 Rev 1. Page 13 of 14

14 hin Dual Flat No-Lead Plastic Package (DFN) NX (b) 5 6 INDEX RE (DUM ) 6 INDEX RE (DUM B) NX L 8 SEING PLNE N (1) 1 2 D OP VIEW SIDE VIEW N-1 e D2 D2/2 (Nd-1)Xe REF. BOOM VIEW 7 L 2X E B E2 E2/2 NX b.1 2X.15 B NX k //.1.8 M B L1 1 L L8.3x3 8 LED HIN DUL FL NO-LED PLSI PGE MILLIMEERS SYMBOL MIN NOMINL MX NOES REF - b , 8 D 3. BS - D , 8, 9 E 3. BS - E , 8, 9 e.65 BS - k L N 8 2 Nd 4 3 Rev. 3 11/4 NOES: 1. Dimensioning and tolerancing conform to SME Y N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. ll dimensions are in millimeters. ngles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. 6. he configuration of the pin #1 identifier is optional, but must be located within the zone indicated. he pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PB Land Pattern Design efforts, see Intersil echnical Brief B ompliant to JEDE MO-WEE-2 except for the L min dimension. SEION "-" ERMINL IP e FOR EVEN ERMINL/SIDE opyright Intersil mericas LL 28. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN6759 Rev 1. Page 14 of 14