DATASHEET ISL Features. Applications. Temperature Characteristics Curve. Pinout. Pin Descriptions

Transcription

1 DSHEE ISL21400 Programmable emperature Slope Voltage Reference FN8091 Rev 3.00 he ISL21400 features a precision voltage reference combined with a temperature sensor whose output voltage varies linearly with temperature. he precision 1.20V reference has a very low temperature coefficient (tempco), and its output voltage is scaled by an internal D (V REF ) to produce a temperature stable output voltage that is programmable from 0V to 1.20V. he output voltage from the temperature sensor (V S ) is summed with V REF to produce a temperature dependent output voltage. he slope of the V S portion of the output voltage can be programmed to be positive or negative in the range -2.1mV/ to +2.1mV/. programmable gain amplifier (PG) sums the V S and the V REF voltages and provides gains of 1x, 2x, and 4x to scale the output up to 4.8V and the slope to ±8.4mV/. he V REF and V S terms are programmable with 8 bits of resolution via an I 2 bus and the values are stored in non-volatile registers. he PG gain is also set via the I 2 bus and the value is stored in a non-volatile register. Non-volatile memory storage assures the programmed settings are retained on power-down, eliminating the need for software initialization at device power-up. emperature haracteristics urve V REF (V) S = 0 S = 0 V = 2 S = 127 V = 1 S = S = 127 S = Features Programmable reference voltage Programmable temperature slope Programmable Gain mplifier Non-volatile storage of programming registers I 2 serial interface 2% total accuracy over temperature and V range 200µ typical active supply current Operating temperature range = -40 to Ld MSOP package Pb-free (RoHS compliant) pplications RF power amplifier bias compensation LD bias compensation Laser diode bias compensation Sensor bias and linearization Data acquisition systems Variable D reference mplifier biasing Pinout ISL21400 (8 LD MSOP) OP VIEW 8 7 V V OU EMPERURE ( ) 0 V SS SD SL Pin Descriptions MSOP SYMBOL DESRIPION 1 2 Hardwire slave address pin for I 2 serial bus 2 1 Hardwire slave address pin for I 2 serial bus 3 0 Hardwire slave address pin for I 2 serial bus 4 V SS Ground pin 5 SL Serial bus clock input 6 SD Serial bus data input/output 7 VOU Output voltage 8 V Device power supply FN8091 Rev 3.00 Page 1 of 17

2 Ordering Information PR NUMBER (Note 3) PR MRING V DD RNGE (V) EMP RNGE ( ) PGE (Pb-free) PG. DWG. # ISL21400IU8Z (Note 2) DEW 2.7 to to Ld MSOP (3.0mm), green mtl M8.118 ISL21400IU8Z- (Notes 1, 2) DEW 2.7 to to Ld MSOP (3.0mm), green mtl M8.118 ISL21400USB-EVLZ Evaluation Board 1. Please refer to B347 for details on reel specifications. 2. hese Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD For Moisture Sensitivity Level (MSL), please see device information page for ISL For more information on MSL please see techbrief B363. Block Diagram V EMP SENSE V S (n) D V REF (m) S V OU V REF D GIN SELE V = 1, 2, 4 BIS n = 0 to m = 0 to EEPROM 5 BYES OMMUNIIONS ND REGISERS SL SD VSS FN8091 Rev 3.00 Page 2 of 17

3 bsolute Maximum Ratings Supply Voltage Range V to 6.5V Voltage on V OU Pin V to V Voltage on ll Other Pins V to V +0.3V ESD Rating Human Body Model kV Machine Model V hermal Information hermal Resistance (ypical) J ( / W) 8 Ld MSOP Package (Note 4) Moisture Sensitivity for MSOP Package (See echnical Brief B363) Level 2 Maximum Junction emperature (Plastic Package) Storage emperature Range to +150 Pb-free reflow profile see link below Recommended Operating onditions emperature to +85 Supply Voltage V to 5.5V UION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOE: 4. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See ech Bried B379 for details. nalog Specifications V = 5.5V, = +25 to +85, Unless Otherwise Noted. SYMBOL PRMEER ES ONDIIONS MIN YP (Note 6) MX UNIS POWER SUPPLY V Supply Voltage Range V I Q Supply V = 2.7V Standby, SD = SL = V µ V = 5.5V Standby, SD = SL = V µ I Q(NV) Non-Volatile Supply V = 2.7V Nonvolatile write µ V = 5.5V Nonvolatile write m Vpor Power-on Recall Voltage Minimum V at which memory recall occurs V V Ramp V Ramp Rate 0.2 V/ms t D Power-Up Delay V above Vpor, time delay to Register recall, and I 2 Interface in standby state 3 ms OUPU VOLGE PERFORMNE SPEIFIIONS G E1 Gain Error V = 2 (Notes 5, 6, 15) % G E2 Gain Error V = 4 (Notes 5, 6, 15) % emperature Sensor oefficient (Notes 5, 12) mv/ bsolute Output Voltage (Swing) Range bsolute Output Voltage (Swing) Range Unloaded, = +25 V GND V Loaded, I OU = ±500µ V GND V S1 emperature Sensor Slope V = 1, n =, m = (Notes 5, 9) -2.1 mv/ S2 emperature Sensor Slope V = 2, n =, m = (Notes 5, 9) -4.2 mv/ S3 emperature Sensor Slope V = 4, n =, m = (Notes 5, 9) -8.4 mv/ FN8091 Rev 3.00 Page 3 of 17

4 nalog Specifications V = 5.5V, = +25 to +85, Unless Otherwise Noted. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN S4 Incremental emperature Sensor Slope V = 1, n =, m = 0 to (Notes 5, 13) SNL emperature Slope Non-Linearity n =, m = 0 to, = -40 to +85 (Notes 5, 14) YP (Note 6) MX UNIS 8.2 µv/ per ode ±0.5 ±1.0 % DNL INL D Relative Linearity (V = 2.7 to 5.5V) D bsolute Linearity (V = 2.7 to 5.5V) V REF and emp Sense; V = 1 (Note 17) LSB V REF and emp Sense; V = 1 (Note 17) LSB V OU(E) otal Error for V OU (Notes 5, 11, 12) ±1 ±2 % V OU1 Output Voltage V REF, Gain = 1 V = 1, n =, m = 128, = +25, V =5.5V V OU2 Output Voltage V REF, Gain = 2 V = 2, n =, m = 128, = +25, V =5.5V V OU3 Output Voltage V REF, Gain = 4 V = 4, n =, m = 128, = +25, V =5.5V V OU4 Output Voltage V REF + S V = 1, n =, m = 0, = +85 V OU5 Output Voltage V REF + S V = 1, n =, m = 128, = +85 V OU6 Output Voltage V REF + S V = 1, n =, m =, = +85 V OU7 Output Voltage V REF + S V = 1, n =, m = 0, =-40, V OU8 Output Voltage V REF + S V = 1, n =, m = 128, = -40, V OU9 Output Voltage V REF + S V = 1, n =, m =, = -40, V V V V V V V V V OUPU VOLGE D SPEIFIIONS PSRR Power Supply Rejection Ratio V = 1, n =, m = 128, (Note 10) db R OU Output Impedance (load regulation) Given by R OU = (V OU /I OU ), = +25, I OU = ±500µ 2 5 I S Short ircuit, Sourcing V = 5.5V, V OU = 0V 5 9 m Short ircuit, Sinking V = 5.5V, V OU = 5.5V 6 9 m L Load apacitance Reference output stable for all L up to specifications 5 nf OUPU VOLGE SPEIFIIONS V N Output Voltage Noise 0.1Hz to 10Hz, V =1 90 µv P-P 10Hz to 10kHz, L = 0, V = 1 BD mv RMS Power-On Response 1% Settling 500 µs Line Ripple Rejection V = 5V ±100mV, f = 120Hz 60 db FN8091 Rev 3.00 Page 4 of 17

5 Serial Interface Specification for SL, SD, 0, 1, 2 Unless Otherwise Noted. SYMBOL PRMEER ES ONDIIONS MIN YP (Note 2) MX UNIS I LI Input Leakage V IN = GND to V 1 V V IL Input LOW Voltage x V V V IH Input HIGH Voltage 0.7 x V V V Hysteresis SD and SL Input Buffer 0.05 x V V Hysteresis V OL SD Output Buffer LOW Voltage I OL = 3m V pin Pin apacitance 10 pf f SL SL Frequency 400 khz t sp Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed 50 ns t t BUF SL Falling Edge to SD Output Data Valid ime the Bus Must be Free Before the Start of a New ransmission SL falling edge crossing 30% of V, until SD exits the 30% to 70% of V window SD crossing 70% of V during a SOP condition, to SD crossing 70% of V during the following SR condition t LOW lock LOW ime Measured at the 30% of V crossing t HIGH lock HIGH ime Measured at the 70% of V crossing t SU:S SR ondition Set-up ime SL rising edge to SD falling edge; both crossing 70% of V t HD:S SR ondition Hold ime From SD falling edge crossing 30% of V to SL falling edge crossing 70% of V t SU:D Input Data Set-up ime From SD exiting the 30% to 70% of V window, to SL rising edge crossing 30% of V t HD:D Input Data Hold ime From SL rising edge crossing 70% of V to SD entering the 30% to 70% of V window t SU:SO SOP ondition Set-up ime From SL rising edge crossing 70% of V, to SD rising edge crossing 30% of V t HD:SO SOP ondition Hold ime for Read, or Volatile Only Write From SD rising edge to SL falling edge; both crossing 70% of V t DH Output Data Hold ime From SL falling edge crossing 30% of V, until SD enters the 30% to 70% of V window t R SD and SL Rise ime From 30% to 70% of V 900 ns 1300 ns 1300 ns 600 ns 600 ns 600 ns 100 ns 0 ns 600 ns 1300 ns 0 ns x b 250 ns FN8091 Rev 3.00 Page 5 of 17

6 Serial Interface Specification for SL, SD, 0, 1, 2 Unless Otherwise Noted. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN t F SD and SL Fall ime From 70% to 30% of V b apacitive Loading of SD or SL otal on-chip and off-chip Rpu SD and SL Bus Pull-up Resistor Off-chip Maximum is determined by t R and t F For b = 400pF, max is about 2k~2.5k For b = 40pF, max is about 15k~20k x b 250 ns pf 1 k I LO Output Leakage urrent (SD only) V OU = GND to V 1 µ V IL 1, 0, SHDN, SD, and SL Input -0.3 V x 0.3 V Buffer LOW Voltage V IH 1, 0, SHDN, SD, and SL Input Buffer HIGH Voltage V OL SD Output Buffer LOW Voltage I OL = 100µ, at 3m sink L apacitive Loading of SD or SL otal on-chip and off-chip t W (Note 18) V x 0.7 V V V pf EEPROM Endurance 1,000,000 ycles EEPROM Retention emperature Years Non-Volatile Write ycle ime ms NOES: 5. Equation 1 governs the output voltage and is stated as follows: 6. ypical values are for = +25 and V = 5.5V. 7. his parameter is not 100% tested. 8. b = total capacitance of one bus line in pf. 9. t W is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user. 10. Over the specified temperature range. emperature slope (S) is measured by the box method whereby the change in V OU is divided by the temperature range; in this case, -40 to +85 = S 1, S 2, S 3 = 11. Given by PSRR (db) = 20 * log 10 (Vout/V ) at D. 12. est +25 and +85 only. 13. otal error of Equation V = 1, = -2.1mV/, V REF = 1.20V, m =, n = to 0, V = 3.0V. YP (Note 2) MX UNIS n V OU V V REF m = n = 0 to, m = 0 to, = -2.1mV/(typ), 0 = +25 V OU min V OU max S = min max V OU E = V OU measured V OU Equation x100% V OU Equation1 14. Over the specified temperature range. emperature slope (S) is measured by the box method whereby the change in V OU is divided by the temperature range. Incremental S is the temperature slope at m = minus the temperature slope at m = 0 divided by with V = 1, n = V OU min V OU max V S OU min V OU max = min max m = min max m = 0 FN8091 Rev 3.00 Page 6 of 17

7 Serial Interface Specification for SL, SD, 0, 1, 2 Unless Otherwise Noted. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN YP (Note 2) MX UNIS NOES:(ontinued) 15. emperature Slope Non- linearity is measured over the specified temperature range. he actual change in output voltage is subtracted from the expected change in output voltage, and then divided by the expected change to normalize before converting to percent. S y VOU SNL = x100%; S y y = For codes n = 8 to 17. Guaranteed monotonic. 18. t W is the time from a valid SOP condition at the end of a Write sequence of I 2 serial interface, to the end of the self-timed internal nonvolatile write cycle. iming Diagrams Bus iming t F t HIGH t LOW t R t sp t HD:SO SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) Write ycle iming SL SD 8th BI OF LS BYE t W SOP ONDIION SR ONDIION FN8091 Rev 3.00 Page 7 of 17

8 ypical Performance urves V = V = 4 V REF (V) S = 0 S = 127 V = 1 S = V REF (V) S = 0 S = 127 S = 0.5 S = 0 S = 127 S = EMPERURE ( ) EMPERURE ( ) FIGURE 1. V OU vs EMPERURE ( V = 1, 2) FIGURE 2. V OU vs EMPERURE ( V = 4) VREF (V) V REF REGISER = d S REGISER = 127d I (m) V REF REGISER = d S REGISER = 127d V (V) V (V) 7 FIGURE 3. V OU vs V (V = +2.7V O +5.5V) FIGURE 4. SUPPLY VOLGE vs SUPPLY URREN NO LOD V = 1 100µV/DIV (V OU x 1000) NO LOD V = 4 50µV/DIV (V OU x 1000) FIGURE 5. V OU VOLGE NOISE ( V = 1, NO LOD) FIGURE 6. V OU VOLGE NOISE ( V = 4, NO LOD) FN8091 Rev 3.00 Page 8 of 17

9 ypical Performance urves (ontinued) H1 = V H2 = V OU V REF (V) V REF REGISER = d S REGISER = 127d EMPERURE ( ) FIGURE 7. URY vs EMPERURE (-40 O +85 ) FIGURE 8. POWER-ON INL IN LSB ODE FIGURE 9. INL, V REF ND EMP SLOPE D DNL IN LSB ODE FIGURE 10. DNL, V REF ND EMP SLOPE D S REGISER = 127d V REF REGISER = d V REF (V) V REF REGISER ODE (m) FIGURE 11. V OU vs V REF ODE (m) V REF (V) S REGISER ODE (n) FIGURE 12. V OU vs EMP SENSE ODE (n), = -40 ND +85 FN8091 Rev 3.00 Page 9 of 17

10 ypical Performance urves (ontinued) V REF (V) V REF REGISER = d S REGISER = 127d I OU (m) FIGURE 13. V OU vs I OU (±1m) Pin Descriptions V OU Programmable voltage output pin. bsolute voltage is determined by device temperature and Equation 1. Drive capability is limited to ±500µ output current and 5000pF output capacitance. 2, 1, 0 Hardware slave address pins that can be used to provide several ISL21400 with a unique physical address to allow for multiple devices off one I 2 bus. GND his is the circuit ground pin. It is common for the V OU and control signal inputs. SD Serial Data Input/Output. Bidirectional pin used for serial data transfer. s an output, it is open drain and may be wire-ored with any number of open drain or open collector outputs. pull-up resistor is required and the value is dependent on the speed of the serial data bus and the number of outputs tied together. SL Serial lock Input. ccepts a clock signal for clocking serial data into and out of the device. he SL line requires a pull-up resistor whose value is dependent on the speed of the serial clock bus and the number of inputs tied together. V Positive Power Supply. onnect to a voltage supply in the range of 2.7V<V <5.5V, with minimum noise and ripple. For best performance, bypass with a 0.1µF capacitor to ground. If the V gain is set to 4 and V OU approaches 5.0V, then V must be set to >5.2V for best output performance. Functional Description Functional Overview Refer to the Functional Block Diagram on page 2. he ISL21400 provides a programmable output voltage which combines both a temperature independent term and a temperature dependent term. he temperature independent term uses a bandgap voltage reference, and the temperature dependent term uses a Proportional o bsolute emperature (P) reference, or emperature Sensor. Each voltage source is scalable using two Ds via the I 2 serial bus. he resulting output voltage can vary from 0V to over 5V and has a variable, programmable emperature Slope (S). Reference Sections Referring to the Block Diagram on page 2, the V REF and emperature Sense (V S ) outputs are summed together () and then passed through the output gain stage (). he voltage output is programmable and is determined by Equation 1: n 2 m V OU = V V REF V S (EQ. 1) where: V = 1, 2, 4 V REF = (not temperature dependent) 0 n (setting contained in Register 0, V REF ) V S = ( - 0 ) = dv S / d = -2.1mV/ = device temperature 0 = m (setting contained in Register 1, S) See pplications Information on page 14 for ways to use Equation 1 and methods for output voltage calculations. FN8091 Rev 3.00 Page 10 of 17

11 ddr BLE 1. ISL21400 REGISER BI MP D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 0 V REF 7 V REF 6 V REF 5 V REF 4 V REF 3 V REF 2 V REF 1 V REF 0 1 S7 S6 S5 S4 S3 S2 S1 S0 2 D7 D6 D5 D4 D3 D2 GIN1 GIN0 3 D7 D6 D5 D4 D3 D2 D1 D0 4 D7 D6 D5 D4 D3 D2 D1 D0 Ds Section he ISL21400 contains two 8-bit Ds whose registers can be programmed via the I 2 serial bus. he D registers are non-volatile such that the values are restored during the V power-up cycle of the device. One D (V REF ) is dedicated to scale the bandgap voltage reference (emperature invariant) and the other D (V S ) is dedicated to scale the emperature Sensor. Both of these Ds can determine the output voltage as defined by Equation 1 (see Register Descriptions ). Output Gain mplifier Section he ISL21400 contains an output gain amplifier () that is programmed via the I 2 serial bus. he gain amplifier is the last stage before the output and therefore controls the overall gain for the device. he gain can be programmed for 1x, 2x, or 4x amplification. his gain factor is used to program the output voltage as determined by Equation 1 (see Register Descriptions ). here are 5 registers in the ISL21400 device, all nonvolatile (see able 2). ll registers are accessible for reading or writing through the I 2 serial bus. Register Descriptions BLE 2. REGISER DESRIPIONS REG NONVOLILE DESRIPION 0 Y Reference setting 1 Y emperature Sensor setting 2 Y Gain and storage 3 Y Storage 4 Y Storage Register 0: Bandgap Reference Gain (Nonvolatile) Register 0 sets the output voltage of the bandgap reference (V REF ). Referring to Equation 1, the number n is the setting from Register 0 as shown in Equation 2: n V REF , for n = 0 to (EQ. 2) his term of Equation 1 can vary from 0V to 1.20V. Register 1: emperature Slope Gain (Nonvolatile) Register 1 sets the emperature Slope (S) of the temperature sensor. Referring to Equation 1, the number m is the setting from Register 1 as shown in Equation 3: 2 m V S (EQ. 3) V S is the temperature dependent term and varies from +136mV at -40 to -126mV at +85. he other term varies from -1 to +1 and scales the temperature term before adding to the V REF portion. Register 2: Device Gain and Storage (nonvolatile) BLE 3. REGISER 2 OUPU GIN (NONVOLILE): OUPU GIN GIN1 GIN0 OUPU GIN, V 0 0 x x x x 4 Register 2 contains 2 bits (2 LSB s) which control the output gain of the device. able 3 shows the state of these two bits and the resulting output gain. Note that two states produce the same gain (Gain 1:0 set to 01b and 10b) of x2. he other 6-bits in the register can be used for general purpose memory (nonvolatile) or left alone. Registers 3 and 4: General Purpose Data (nonvolatile) hese two registers are one byte each and can be used for general purpose nonvolatile memory. I 2 Serial Interface he ISL21400 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is the master and the device being controlled is the slave. he master always initiates data transfers and provides the clock for both transmit and receive operations. herefore, the ISL21400 operates as a slave device in all applications. FN8091 Rev 3.00 Page 11 of 17

12 ll communication over the I 2 interface is conducted by sending the MSB of each byte of data first. Protocol onventions Data states on the SD line can change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating SR and SOP conditions (see Figure 10). On power-up of the ISL21400 the SD pin is in the input mode. ll I 2 interface operations must begin with a SR condition, which is a HIGH to LOW transition of SD while SL is HIGH. he ISL21400 continuously monitors the SD and SL lines for the SR condition and does not respond to any command until this condition is met (see Figure 10). SR condition is ignored during the power-up sequence and during non-volatile write cycles for the device. ll I 2 interface operations must be terminated by a SOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (see Figure 10) SOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. SOP condition at the end of a write operation to a non-volatile byte initiates an internal non-volatile write cycle. he device enters its standby state when the internal, non-volatile write cycle is completed. n, cknowledge, is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the SD bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the eight bits of data (see Figure 11). he ISL21400 responds with an after recognition of a SR condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. he ISL21400 also responds with an after receiving a Data Byte of a write operation. he master must respond with an after receiving a Data Byte of a read operation. valid Identification Byte contains as the seven MSBs. he bits must correspond to the logic levels at those pins of the ISL21400 device. he LSB in the Read/Write bit. Its value is 1 for a Read operation, and 0 for a Write operation (see able 4). Write Operation BLE 4. IDENIFIION BYE FORM R/W state. When the internal non-volatile write cycle is completed, the ISL21400 enters its standby state (see Figure 12). SOP conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated signal. If a SOP byte is issued in the middle of a data byte, or before 1 full data byte + is sent, then the ISL21400 resets itself without performing the write. he contents of the array are not affected. Data Protection valid Identification Byte, ddress Byte, and total number of SL pulses act as a protection for the registers. SOP condition also acts as a protection for non-volatile memory. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. he presence of the SOP condition after the rest of the bits are received then triggers the non-volatile write. Read Operation urrent ddress Read operation is shown in Figure 13. It consists of a minimum 2 bytes: a SR followed by the ID byte from the master with the R/W bit set to 1, then an followed by the data byte or bytes sent by the slave. he master terminates the Read operation by not responding with an and then issuing a SOP condition. his operation is useful if the master knows the current address and desires to read one or more data bytes. Random ddress Read operation consists of a three byte dummy write instruction followed by a urrent ddress Read operation (see Figure 14). he master initiates the operation issuing the following sequence: a SR, the identification byte with the R/W bit set to "0", an ddress Byte, a second SR, and a second Identification byte with the R/W bit set to "1". fter each of the three bytes, the ISL21400 responds with an. he ISL21400 then transmits Data Bytes as long as the master responds with an during the SL cycle following the eighth bit of each byte. he master terminates the Read operation (issuing a SOP condition) following the last bit of the last Data Byte (see Figure 13). he Data Bytes are from the registers indicated by an internal pointer. his pointer initial s value is determined by the ddress Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. ddress 04h is the last valid data byte, higher addresses are not available. Data from addresses higher than memory location 04h will be invalid. (MSB) (LSB) Write operation requires a SR condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a SOP condition. fter each of the three bytes, the ISL21400 responds with an. he master will then send a SOP and at this time the device begins its internal non-volatile write cycle. During this time, the device ignores transitions at the SD and SL pins, and the SD output is at a high impedance FN8091 Rev 3.00 Page 12 of 17

13 SL SD SR D D D SOP SBLE HNGE SBLE FIGURE 14. VLID D HNGES, SR ND SOP ONDIIONS SL FROM MSER SD OUPU FROM RNSMIER HIGH SD OUPU FROM REEIVER HIGH SR FIGURE 15. NOWLEDGE RESPONSE FROM REEIVER SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W = 0 WRIE DDRESS BYE D BYE S O P SIGNL SD SIGNLS FROM HE ISL21400 FIGURE 16. BYE WRIE SEQUENE SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W = 1 RED S O P SIGNL SD SIGNLS FROM HE SLVE FIRS RED D BYE LS RED D BYE FIGURE 17. DDRESS RED SEQUENE FN8091 Rev 3.00 Page 13 of 17

14 SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W = 0 DDRESS BYE S R IDENIFIION BYE WIH R/W = 1 S O P SIGNL SD SIGNLS FROM HE SLVE FIRS RED D BYE LS RED D BYE FIGURE 18. RNDOM DDRESS RED SEQUENE pplications Information Power-Up onsiderations he ISL21400 has on-chip EEPROM memory storage for the D and gain settings of the device. hese settings must be recalled correctly on power-up for proper operation. Normally there are no issues with recall, although it is always best to provide a smooth, glitch-free power-up waveform on V. dding a small 0.1µF capacitor at the device V will help with power-up as well as V OU load changes. Noise Performance he output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 90µV P-P. he noise measurement is made with a bandpass filter made of a 1-pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Load capacitance up to 5000pF can be added but will result in only marginal improvements in output noise and transient response. he output stage of the ISL21400 is not designed to drive heavily capacitive loads. For high impedance loads, an R- network can be added to filter high frequency noise and preserve D control. Output Voltage Programming onsiderations Setting and controlling the output voltage of the ISL21400 can be done easily by breaking down the components into temperature variant and invariant, and setting them separately. Let s use Equation 1 to derive separate Reference Output and Output emperature Slope equations: V OU = n 2 m V V REF V V S = V V REF REF + V V S S"" Reference erm + emp Slope erm he first term controls the output D value, and the second term controls the emperature slope, where n REF = (ranges from 0 to 1) 2 m S = (ranges from -1 to +1) D OUPU ONROL DISUSSION he reference term yields Equation 4 for Reference Output: V OU (D) = V V REF REF (EQ. 4) Note that the D term is dependent on the 1.20V reference voltage, which is constant, the overall gain, V, and the Reference gain, REF. Since the product V * REF ranges from 0 to 4, the total reference D output can range from 0.0V to 4.8V. In order to get the 4.8V output, V must be greater than 4.8V by the output dropout plus any overhead for output loading (the specification for V OU = 5.0V is listed with V = 5.5V). he Resolution of V OU (D) control changes with V, so that with a 4.80V full scale output ( V = 4), the resolution is 4.80/ or 18.8mV/bit. With V = 1, the resolution is 4.7mV/bit. EMP SENSE ONROL DISUSSION Equation 4 yields this expression, Equation 5, for emperature Slope: V OU S = V V S S (EQ. 5) Since V S = ( - 0 ), the slope term is dependent on the base temp slope of the device, (-2.1mV/ ), and the gain terms V and S. his gives a formula (Equation 6) for the portion of V OU at a specific temperature: V OU S= V S 0 (EQ. 6) he product V * S ranges from -4 to 4, so the emperature Slope can range from -8.4 to +8.4mV/, which is independent of the output D voltage. he resolution of Slope control is determined by this range (±8.4mV/ ) and the gain terms, and will vary from 65.8µV/ /bit ( V = 4) down to 16.2µV/ /bit ( V = 1). t = 0 = +25, V OU (S) = 0, no changes in S will cause a change in V OU, and V OU will only vary with the V OU (D) control. s temperature increases or decreases, from = +25, V OU will then change according to the programmed emp Slope. FN8091 Rev 3.00 Page 14 of 17

15 In many cases a form of Equation 6 is needed which yields a V OU change with respect to temperature. By rearranging, we get Equation 7: V OU V OU S = = 0 V S,(in mv/ (EQ. 7) EXMPLE 1: PROGRMMED EMPERURE OMPENSION EXMPLE he ISL21400 can easily compensate for known temperature drift by programming the device for the initial V OU setting and empco using standard equations and some simple steps. he accuracy of the final programmed output will be limited to the data sheet specifications (typically 1% accuracy for V OU and Slope). In this example, an N-hannel MOSFE gate has a -2.8mV/ empco from -10 to +85. constant bias drain current is desired, with a target Vgs range derived from the data sheet of 2.5V to 3.5V at +25. Offset Setting: Using Equation 2 and targeting V OU = 3.0VD: V OU D= V V REF REF = 3.00V V REF = 1.20V V REF = 2.50 Note that REF varies from 0 to 1, so to get 2.40, V = 4. REF = = = n = 159 decimal = 9F hex n emperature Slope Setting: Using Equation 5, which can solve for Slope directly: V OU = V S = 2.8mV S = S = = 2 m m = 170 decimal = 9 hex he ISL21400 device can be programmed with these calculated parameters and perform temperature compensation or direct control in the target circuit. If parameters change for some reason, then the device can be reprogrammed with new values and the circuit retested. EXMPLE 2. LULING HE V OU EMPERURE SLOPE In some applications, it may be desirable to calculate what the output voltage and temp slope are, given the programmed register settings. Such an application could be a closed loop system with internal calibration procedure. By reading the registers of the ISL21400, then calculating the V OU parameters, the system characteristics can be recorded. For the following example, let s determine the voltage output, V OU (D) at +25, and also the change due to temperature variation (ppm) from +25 to +85. Equations 4 and 7 will be used to calculate the answers. Given, the contents of the registers: V = 1 n = 178 decimal m = 74 decimal Using Equation 2: V OU D= V V REF REF 178 = = V Using Equation 5: V OU = V S mv = = mV lso, to solve for overall temp slope of the output: mV = 872.5mV 1010ppm Note that Equation 1 can be used directly to solve for output voltage at a given temperature, in this case +85 : n V OU V V REF m = V OU +85 = = = V ypical pplications ircuits LDMOS RF Power mplifier (RFP). he ISL21400 is used to set the gate bias for the LDMOS transistor in a single stage of an RFP. Normally this is done with a D or digital potentiometer with some discrete temperature compensation circuitry. he ISL21400 simplifies this control and allows a full range of D bias and tempco control. typical circuit can be calibrated for correct bias at room temperature (+25 ) on power-up using a microcontroller or direct I 2 control. he temperature of the unit can then be increased to the highest operating range, and the emperature Slope setting can then be adjusted to bring the amplifier back to correct bias. Since the emp Slope setting has a negligible effect on the room temperature setting, the amplifier will be biased correctly over the operating temperature of the unit. FN8091 Rev 3.00 Page 15 of 17

16 +28V U2 1 IN OU 3 2 GND +5V REGULOR +28V I 2 BUS SL SD V 8 VOU 7 GND 4 ISL21400 R1 1k 1 100pF R2 100 L1 RF OUPU RF INPU 2 Q1 LDMOS FIGURE 19. LDMOS RFP BIS ONROL opyright Intersil mericas LL ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN8091 Rev 3.00 Page 16 of 17

17 Mini Small Outline Plastic Packages (MSOP) INDEX RE 1 2 N 1 2 OP VIEW e D b SIDE VIEW E1 GUGE PLNE SEING PLNE 0.25 (0.010) 4X 4X NOES: 1. hese package dimensions are within allowable dimensions of JEDE MO-187B. 2. Dimensioning and tolerancing per NSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. erminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. llowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm ( inch). 10. Datums - - and - B - to be determined at Datum plane - H ontrolling dimension: MILLIMEER. onverted inch dimensions are for reference only. E 0.20 (0.008) B 0.10 (0.004) 0.20 (0.008) a SEING PLNE 0.20 (0.008) D L1 L E 1 R1 R L END VIEW -- -B- -- -H- -B- M8.118 (JEDE MO-187) 8 LED MINI SMLL OULINE PLSI PGE INHES MILLIMEERS SYMBOL MIN MX MIN MX NOES b c D E e BS 0.65 BS - E L L REF 0.95 REF - N R R o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - Rev. 2 01/03 FN8091 Rev 3.00 Page 17 of 17