Features. Pinout. DEN to Ld MSOP (Pb-free) M WA to Ld MSOP (Pb-free) M8.118

Transcription

1 DSHEE ISL981 Single Digitally ontrolled Potentiometer (XDP ) Low Noise/Low Power/I 2 Bus/256 aps FN8234 Rev 3. he ISL981 integrates a digitally controlled potentiometer (XDP) on a monolithic MOS integrated circuit. he digitally controlled potentiometers are implemented with a combination of resistor elements and MOS switches. he position of the wipers are controlled by the user through the I 2 bus interface. Each potentiometer has an associated Wiper Register (WR) that can be directly written to and read by the user. he contents of the WR controls the position of the wiper. When powered on the ISL981 s wiper will always commence at mid-scale (128 tap position). he DP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features 256 resistor taps -.4% resolution I 2 serial interface with write/read capability Power-on preset to mid-scale (128 tap position) Wiper resistance: 7 3.3V Standby current 5µ max Power supply: 2.7V to 5.5V 5k, 1k total resistance 8 Ld MSOP Pb-free plus anneal available (RoHS compliant) Pinout ISL981 (8 LD MSOP) OP VIEW N SL SD GND V RH RL RW Ordering Information PR NUMBER PR MRING R OL (k ) EMP RNGE ( ) PGE PG. DWG# ISL981WIU8Z* (Note) (No longer available, recommended replacement: ISL981UU8Z-) ISL981WU8Z* (Note) (No longer available, recommended replacement: ISL981UU8Z-) DEN 1-4 to Ld MSOP (Pb-free) M W 1-4 to Ld MSOP (Pb-free) M8.118 ISL981UIU8Z* (Note) DEM 5-4 to Ld MSOP (Pb-free) M8.118 ISL981UU8Z* (Note) 81U 5-4 to Ld MSOP (Pb-free) M8.118 *dd "-" suffix for tape and reel. NOE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD-2. FN8234 Rev 3. Page 1 of 12

2 Block Diagram V RH SD SL I 2 ND ONROL WIPER REGISER RL RW GND Pin Descriptions Equivalent ircuitry MSOP PIN SYMBOL DESRIPION 1 N No connection R OL 2 SL I 2 interface clock 3 SD Serial data I/O for the I 2 interface 4 GND Ground 5 RW Wiper terminal of the DP R H 1pF H W 25pF L 1pF R L 6 RL Low terminal of the DP R W 7 RH High terminal of the DP 8 V Power supply FN8234 Rev 3. Page 2 of 12

3 bsolute Maximum Ratings Storage emperature to +15 Voltage at ny Digital Interface Pin With Respect to V SS V to V +.3V V V to +6V Voltage at ny DP Pin With Respect to V SS V to V Lead emperature (Soldering, 1s) I W (1s) ±6m Latchup lass II, +15 ESD HBM kV MM V hermal Information hermal Resistance (ypical, Note 1) J ( /W) 8 Ld MSOP Package 13 Maximum Junction emperature (Plastic Package Recommended Operating onditions Industrial to +85 utomotive to +15 V V to 5.5V Power Rating mW Wiper urrent ±3.m UION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. his is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOES: 1. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See ech Brief B379 for details. nalog Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PRMEER ES ONDIIONS MIN YP (Notes 2) MX UNI R OL R H to R L Resistance W, U versions respectively 1, 5 k R H to R L Resistance olerance % R W Wiper resistance V = +25 Wiper current = V /R OL 7 2 H / L / W Potentiometer apacitance (Note 14, Equivalent circuitry) 1/1/25 pf I LkgDP Leakage on DP pins (Note 14) Voltage at pin from GND to V.1 1 µ VOLGE DIVIDER MODE RL; RH; measured at RW, unloaded) INL (Note 7) Integral Non-Linearity -1 1 LSB (Note 3) DNL (Note 6) Differential Non-Linearity Monotonic over all tap positions W option LSB (Note 3) U option LSB (Note 3) ZSerror (Note 4) Zero-Scale Error W option 1 7 LSB (Note 3) U option.5 2 FSerror (Note 5) Full-Scale Error W option -7-1 LSB (Note 3) U option V (Notes 8, 14) Ratiometric emperature oefficient DP Register set to 8 hex ±4 ppm/ RESISOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 12) Integral Non-Linearity DP register set between 2 hex and FF hex. Monotonic over all tap positions -1 1 MI (Note 9) RDNL (Note 6) Differential Non-Linearity DP register set between 2 hex W option MI (Note 9) and FF hex. Monotonic over all tap U option positions MI (Note 9) Roffset (Note 1) Offset W option 1 7 MI (Note 9) U option.5 2 MI (Note 9) R (Notes 13, 14) Resistance emperature oefficient DP register set between 2 hex and FF hex ±35 ppm/ FN8234 Rev 3. Page 3 of 12

4 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PRMEER ES ONDIIONS MIN I 1 V Supply urrent f SL = 4kHz; SD = Open; (for I 2, ctive, (Volatile Write/Read) Read and Volatile Write States only) I SB V urrent (Standby) V = +5.5V, I 2 Interface in Standby State, emperature range from -4 to +85 I LkgDig Leakage urrent at Pins SD and SL V = +5.5V, I 2 Interface in Standby State, emperature range from -4 to +15 V = +3.6V, I 2 Interface in Standby State, emperature range from -4 to +85 V = +3.6V, I 2 Interface in Standby State, emperature range from -4 to +15 YP (Note 1) MX UNIS 2 1 µ 2 5 µ 2 8 µ.8 2 µ.8 5 µ Voltage at pin from GND to V -1 1 µ t DP (Note 14) DP Wiper Response ime SL falling edge of last bit of DP Data Byte to wiper change 1 µs Vpor Power-On Recall Voltage Minimum V at which memory recall occurs V V Ramp V Ramp Rate.2 V/ms t D (Note 14) Power-Up Delay V above Vpor, to DP Initial Value Register recall completed, and I 2 Interface in standby state 3 ms SERIL INERFE SPEIFIIONS V IL SD, and SL Input Buffer LOW Voltage V IH Hysteresis (Note 14) V OL (Note 14) SD, and SL Input Buffer HIGH Voltage SD and SL Input Buffer Hysteresis.5* V SD Output Buffer LOW Voltage, Sinking 4m -.3.3*V V.7*V V +.3 V.4 V pin (Note 14) SD, and SL Pin apacitance 1 pf f SL SL Frequency 4 khz t IN (Note 14) Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed. 5 ns t (Note 14) t BUF (Note 14) SL Falling Edge to SD Output Data Valid ime the Bus Must be Free Before the Start of a New ransmission SL falling edge crossing 3% of V, until SD exits the 3% to 7% of V window. SD crossing 7% of V during a SOP condition, to SD crossing 7% of V during the following SR condition. V 9 ns 13 ns t LOW lock LOW ime Measured at the 3% of V crossing. 13 ns t HIGH lock HIGH ime Measured at the 7% of V crossing. 6 ns t SU:S SR ondition Setup ime SL rising edge to SD falling edge. Both crossing 7% of V. 6 ns t HD:S SR ondition Hold ime From SD falling edge crossing 3% of V to SL falling edge crossing 7% of V. 6 ns t SU:D Input Data Setup ime From SD exiting the 3% to 7% of V window, to SL rising edge crossing 3% of V 1 ns t HD:D Input Data Hold ime From SL rising edge crossing 7% of V to SD entering the 3% to 7% of V window. t SU:SO SOP ondition Setup ime From SL rising edge crossing 7% of V, to SD rising edge crossing 3% of V. ns 6 ns FN8234 Rev 3. Page 4 of 12

5 Operating Specifications t HD:SO SD vs SL iming Over the recommended operating conditions unless otherwise specified. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN SOP ondition Hold ime for Read, or Volatile Only Write From SD rising edge to SL falling edge. Both crossing 7% of V. YP (Note 1) MX UNIS 6 ns t DH (Note 14) Output Data Hold ime From SL falling edge crossing 3% of V, until ns SD enters the 3% to 7% of V window. t R (Note 14) SD and SL Rise ime From 3% to 7% of V ns.1 * b t F (Note 14) SD and SL Fall ime From 7% to 3% of V ns.1 * b b (Note 14) apacitive Loading of SD or SL otal on-chip and off-chip 1 4 pf Rpu (Note 14) SD and SL Bus Pull-Up Resistor Off-hip Maximum is determined by t R and t F. For b = 4pF, max is about 2~2.5k. For b = 4pF, max is about 15~2k 1 k t F t HIGH t LOW t R SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) NOES: 2. ypical values are for = +25 and 3.3V supply voltage. 3. LSB: [V(RW) 255 V(RW) ]/255. V(RW) 255 and V(RW) are V(RW) for the DP register set to FF hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 4. ZS error = V(RW) /LSB. 5. FS error = [V(RW) 255 V ]/LSB. 6. DNL = [V(RW) i V(RW) i-1 ]/LSB-1, for i = 1 to 255. i is the DP register setting. 7. INL = (V(RW) i i LSB V(RW) )/LSB, for i = 1 to 255. Max V RW i Min V RW i 8. V = for i = 16 to 24 decimal, = -4 to +15. Max( ) is the maximum value of the wiper Max V RW i + Min V RW i voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 9. MI = R 255 R /255. R 255 and R are the measured resistances for the DP register set to FF hex and hex respectively. Roffset = R /MI, when measuring between RW and RL. 1. Roffset = R 255 /MI, when measuring between RW and RH. 11. RDNL = (R i R i-1 )/MI, for i = 32 to RINL = [R i (MI i) R ]/MI, for i = 32 to Max Ri Min Ri 1 6 R = for i = 32 to 255, = -4 to +15. Max( ) is the maximum value of the resistance and Min ( ) is the Max Ri + Min Ri minimum value of the resistance over the temperature range. 14. his parameter is not 1% tested. FN8234 Rev 3. Page 5 of 12

6 ypical Performance urves WIPER RESISNE ( ) Vcc = 2.7, = -4 Vcc = 2.7, = +85 Vcc = 2.7, = Vcc = 5.5, = -4 Vcc = 5.5, = +85 Vcc = 5.5, = P POSIION (DEIML) FIGURE 1. WIPER RESISNE vs P POSIION [I(RW) = V /Rtotal] FOR 5k (U) SNDBY I (µ) V (V) FIGURE 2. SNDBY I vs V DNL (LSB) Vcc = 5.5, = -4 Vcc = 2.7, = +25 Vcc = 5.5, = +25 Vcc = 2.7, = +85 Vcc = 2.7, = -4 Vcc = 5.5, = +85 INL (LSB) Vcc = 2.7, = -4 Vcc = 5.5, = -4 Vcc = 2.7, = +25 Vcc = 2.7, = +85 Vcc = 5.5, = +85 Vcc = 5.5, = P POSIION (DEIML) FIGURE 3. DNL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W) P POSIION (DEIML) FIGURE 4. INL vs P POSIION IN VOLGE DIVIDER MODE FOR 1k (W) ZSerror (LSB) V V EMPERURE ( ) FIGURE 5. ZSerror vs EMPERURE FSerror (LSB) Vcc = 5.5V Vcc = 2.7V EMPERURE ( ) FIGURE 6. FSerror vs EMPERURE FN8234 Rev 3. Page 6 of 12

7 ypical Performance urves (ontinued) DNL (LSB) Vcc = 5.5, = +25 Vcc = 2.7, = +25 Vcc = 5.5, = +85 Vcc = 2.7, = +85 Vcc = 2.7, = -4 Vcc = 5.5, = P POSIION (DEIML) FIGURE 7. DNL vs P POSIION IN RHEOS MODE FOR 5k (U) INL (LSB) Vcc = 2.7, = +25 Vcc = 5.5, = -4 Vcc = 5.5, = Vcc = 2.7, = Vcc = 5.5, = +25 Vcc = 2.7, = P POSIION (DEIML) FIGURE 8. INL vs P POSIION IN RHEOS MODE FOR 5k (U) END O END R OL HNGE (%) V 2.7V (ppm/ ) EMPERURE ( ) FIGURE 9. END O END R OL % HNGE vs EMPERURE P POSIION (DEIML) FIGURE 1. FOR VOLGE DIVIDER MODE IN ppm INPU (ppm/ ) OUPU P POSIION (DEIML) FIGURE 11. FOR RHEOS MODE IN ppm ap Position = Mid Point R OL = 9.4 FIGURE 12. FREQUENY RESPONSE (2.2MHz) FN8234 Rev 3. Page 7 of 12

8 ypical Performance urves (ontinued) Signal at Wiper (Wiper Unloaded) SL Signal at Wiper (Wiper Unloaded Movement From ffh to h) Wiper Movement Mid Point From 8h to 7fh FIGURE 13. MIDSLE GLIH, ODE 8h O 7Fh (WIPER ) FIGURE 14. LRGE SIGNL SELING IME Principles of Operation he ISL981 is an integrated circuit incorporating one DP with its associated registers, and an I 2 serial interface providing direct communication between a host and the potentiometer. DP Description he DP is implemented with a combination of resistor elements and MOS switches. he physical ends of the DP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). he RW pin of the DP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. he position of the wiper terminal within the DP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of the DP contains all zeroes (WR[7:]: h), its wiper terminal (RW) is closest to its Low terminal (RL). When the WR of the DP contains all ones (WR[7:]: FFh), its wiper terminal (RW) is closest to its High terminal (RH). s the value of the WR increases from all zeroes ( decimal) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. t the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL981 is being powered up, he WR is reset to 8h (128 decimal), which locates RW roughly at the center between RL and RH. he WR can be read or written to directly using the I 2 serial interface as described in the following sections. he I 2 interface ddress Byte has to be set to hex to access the WR. I 2 Serial Interface he ISL981 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master always initiates data transfers and provides the clock for both transmit and receive operations. herefore, the ISL981 operates as a slave device in all applications. ll communication over the I 2 interface is conducted by sending the MSB of each byte of data first. Protocol onventions Data states on the SD line must change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating SR and SOP conditions (See Figure 15). On power-up of the ISL981 the SD pin is in the input mode. ll I 2 interface operations must begin with a SR condition, which is a HIGH to LOW transition of SD while SL is HIGH. he ISL981 continuously monitors the SD and SL lines for the SR condition and does not respond to any command until this condition is met (See Figure 15). SR condition is ignored during the powerup for the device. ll I 2 interface operations must be terminated by a SOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (See Figure 15) SOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. n acknowledge () is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the SD bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the eight bits of data (See Figure 16). FN8234 Rev 3. Page 8 of 12

9 he ISL981 responds with an after recognition of a SR condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. he ISL981 also responds with an after receiving a Data Byte of a write operation. he master must respond with an after receiving a Data Byte of a read operation. valid Identification Byte contains 11 as the seven MSBs. he LSB is the Read/Write bit. Its value is 1 for a Read operation, and for a Write operation (See able 1) he address byte is set to h and follows the identification byte. Read and write operations always point to address h, indicating the WR for the device. BLE 1. IDENIFIION BYE FORM 1 1 R/W (MSB) Write Operation (LSB) Write operation requires a SR condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a SOP condition. fter each of the three bytes, the ISL981 responds with an. t this time the device enters its standby state (See Figure 17). Data Protection valid Identification Byte. ddress Byte, and total number of SL pulses act as a protection for the registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. he Data Byte is transferred to the Wiper Register (WR) at the falling edge of the SL pulse that loads the last bit (LSB) of the Data Byte. Read Operation Read operation consists of a three byte instruction followed by one Data Byte (See Figure 18). he master initiates the operation issuing the following sequence: a SR, the identification byte with the R/W bit set to "", an ddress Byte, a second SR, and a second Identification byte with the R/W bit set to "1". fter each of the three bytes, the ISL981 responds with an. he the ISL981 transmits Data Bytes as long as the master responds with an during the SL cycle following the eighth bit of each byte. he master terminates the read operation (issuing a and a SOP condition) following the last bit of the Data Byte (See Figure 18). SL SD SR D D D SOP SBLE HNGE SBLE FIGURE 15. VLID D HNGES, SR, ND SOP ONDIIONS SL FROM MSER SD OUPU FROM RNSMIER HIGH IMPEDNE SD OUPU FROM REEIVER HIGH IMPEDNE SR FIGURE 16. NOWLEDGE RESPONSE FROM REEIVER FN8234 Rev 3. Page 9 of 12

10 WRIE SIGNLS FROM HE MSER S R IDENIFIION BYE DDRESS BYE D BYE S O P SIGNL SD 1 1 SIGNLS FROM HE ISL981 FIGURE 17. BYE WRIE SEQUENE SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W= DDRESS BYE S R IDENIFIION BYE WIH R/W=1 S O P SIGNL SD SIGNLS FROM HE SLVE D BYE FIGURE 18. RED SEQUENE FN8234 Rev 3. Page 1 of 12

11 Revision History he revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DE REVISION HNGE FN Updated the Ordering Information table on page 1. dded Revision History and bout Intersil sections. Updated Package Outline Drawing M8.118 to the latest revision. -Revision 2 to Revision 3 changes - Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing. -Revision 3 to Revision 4 changes - orrected lead width dimension typo in side view 1 from " " to " ". bout Intersil Intersil orporation is a leading provider of innovative power management and precision analog solutions. he company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at opyright Intersil mericas LL ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN8234 Rev 3. Page 11 of 12

12 Package Outline Drawing M LED MINI SMLL OULINE PLSI PGE Rev 4, 7/11 3.± D DEIL "X" 1.1 MX SIDE VIEW ±.5 4.9±.15 5 PIN# 1 ID.95 REF 1 2 B.65 BS OP VIEW GUGE PLNE.25 H.85±1.55 ±.15 DEIL "X" 3 ±3 SEING PLNE M -B D.1 ±.5.1 SIDE VIEW 1 (5.8) (4.4) (3.) NOES: 1. Dimensions are in millimeters. (.65) (.4) Dimensioning and tolerancing conform to JEDE MO-187- and MSEY14.5m Plastic or metal protrusions of.15mm max per side are not included. Plastic interlead protrusions of.15mm max per side are not included. (1.4) 5. Dimensions are measured at Datum Plane "H". YPIL REOMMENDED LND PERN 6. Dimensions in ( ) are for reference only. FN8234 Rev 3. Page 12 of 12