ICS1527. Video Clock Synthesizer

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1 Integrated ircuit Systems IS1527 Video lock Synthesizer General Description he IS1527 is a low-cost, high-performance frequency generator. It is suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IS s advanced low-voltage MOS mixed-mode technology, the IS1527 is an effective clock synthesizer that supports video projectors and displays at resolutions from VG to beyond XG. he IS1527 offers single-ended clock outputs to 60 or 110 MHz. he HSYN_out, and VSYN_out pins provide the regenerated versions of the HSYN and VSYN inputs synchronous to the L output. he advanced PLL uses either its internal programmable feedback divider or an external divider. he device is programmed by a standard I 2 -bus serial interface and is available in a SSOP16 package. IS1527 Functional Diagram HSYN VSYN I 2 EXFB IS1527 External Divider HSYN_out VSYN_out L Features Lead-free packaging (Pb-free) Low jitter (typical 27 ps short term jitter) LVMOS single-ended clock outputs 60/110 MHz speed grades available Uses 3.3 V power supply 5 Volt tolerant Inputs (HSYN, VSYN) oast (ignore HSYN) capability via VSYN pin Industry standard I 2 -bus programming interface PLL Lock detection via I 2 or LO output pin 16-pin SSOP package pplications Frequency synthesis LD monitors, video projectors and plasma displays Genlocking multiple video subsystems Pin onfiguration (16-pin SSOP) VSSD SD SL VSYN EXFB HSYN VDD VSS VDDD VSSQ VSYN_out VDDQ L HSYN_out LO I2DR MDS 1527 G IS reserves the right to make changes in the preliminary device data identified in this publication without notice. IS advises its customers to obtain the latest version of all device data to verify that information being relied upon is current and accurate. Revision

2 Section 1 Overview Section 1 Overview he IS1527 has the ability to operate in line-locked mode with the HSYN input. he IS1527 is a user-programmable, high-performance general purpose clock generator. It is intended for graphics system line-locked and genlocked applications, and provides the clock signals required by high-performance analog-to-digital converters. 1.1 Phase-Locked Loop he phase-locked loop has a very wide input frequency range (8 khz to 100 MHz). Not only is the IS1527 an excellent, general purpose clock synthesizer, but it is also capable of line-locked operation. Refer to the block diagram below. Figure 1-1 Simplified Block Diagram HSYN PFD P VO VOD 2,4,8,16 L FD EXFB Flip-flop HSYN_out VSYN Flip-flop VSYN_out Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity he heart of the IS1527 is a voltage controlled oscillator (VO). he VO speed is controlled by the voltage on the loop filter. his voltage will be described later in this section. he VO s clock output is first passed through the VO Divider (VOD). he VOD allows the VO to operate at higher speeds than the required output clock. NOE: Under normal, locked operation the VOD has no effect on the speed of the output clocks, just the VO frequency. he output of the VOD is the full speed output frequency seen on the L. his clock is then sent through the 12-bit internal Feedback Divider (FD). he feedback divider controls how many clocks are seen during every cycle of the input reference. he Phase Frequency Detector (PFD) then compares the feedback to the input and controls the filter voltage by enabling and disabling the charge pump. he charge pump has programmable current drive and will source and sink current as appropriate to keep the input and the HSYN_out output aligned. he input HSYN and VSYN can be conditioned by a high-performance Schmitt-trigger by sharpening the rising/falling edge. he HSYN_out and VSYN_out signals are aligned with the output clock (L) via a set of flip flops. 1.2 Output Drivers and Logic Inputs he IS1527 uses low-voltage L (LVL) inputs and LVMOS outputs, operating at the 3.3 V supply voltage. he LVL inputs are 5 V tolerant. he LVMOS drive resistive terminations or transmission lines. 1.3 utomatic Power-On Reset Detection he IS1527 has automatic power-on reset detection (POR) circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required. MDS 1527 G 2 Revision

3 1.4 I 2 Bus Serial Interface he IS1527 uses a 5 volt tolerant, industry-standard I 2 -bus serial interface that runs at either low-speed (100 khz) or high-speed (400 khz). he interface uses 12 word addresses for control and status: one write-only, eight read/write, and three read-only addresses. wo IS1527 devices can sit on the same I 2 bus, each selected by the Master according to the state of the I2DR pin. he 7 bit device address is (binary) when I2DR is low. he device address is (binary) when I2DR is high. See Section 4, Programming Section 1 Overview MDS1527 G 3 Revision

4 Section 2 Pin Descriptions Section 2 Pin Descriptions able 2-1 IS1527 Pin Descriptions PIN NO. PIN NME YPE DESRIPION OMMENS Notes 1 VSSD POWER Digital ground 2 SD IN/OU Serial data I 2 -bus 1 3 SL IN Serial clock I 2 -bus 1 4 VSYN IN Vertical sync 1 & 2 5 EXFB IN External feedback From External Divider 1 & 2 6 HSYN IN Horizontal sync lock input to PLL 1 & 2 7 VDD POWER nalog supply Power for analog circuitry 8 VSS POWER nalog ground Ground for analog circuitry 9 I2DR IN I 2 device address hip I 2 address select 10 LO LVMOS OU 11 HSYN_out LVMOS OU 12 L LVMOS OU Lock HSYN output Pixel clock output PLL lock Schmitt-trigger filtered HSYN realigned with the output pixel clock LVMOS driver for full-speed clock 13 VDDQ POWER Output driver supply Power for output drivers 14 VSYN_out LVMOS OU VSYN output Schmitt-trigger filtered VSYN realigned with the output pixel clock 15 VSSQ POWER Output driver ground Ground for output drivers 16 VDDD POWER Digital supply Power for digital sections Notes: 1. hese LVL inputs are 5 V tolerant. 2. onnect to ground if unused. MDS 1527 G 4 Revision

5 Section 3 Register map summary Section 3 Register map summary Word ddress Name ccess Bit Name Bit # 00h Input ontrol Reset Value Description R / W Pen 0 1 harge Pump Enable 0=External Enable via VSYN, 1=lways Enabled VSYN_Pol 1 0 VSYN Polarity (harge Pump Enable) Requires 00h:0=0 0=oast (charge pump disabled) while VSYN low, 1=oast (charge pump disabled) while VSYN high HSYN_Pol 2 0 HSYN Polarity 0=Rising Edge, 1=Falling Edge Fbk_Pol 3 0 External Feedback Polarity 0=Positive Edge, 1=Negative Edge Fbk_Sel 4 0 External Feedback Select 0=Internal Feedback, 1=External Reserved 5 0 Reserved EnPLS 6 1 Enable PLL Lock Status Output 0=Disable, 1=Enable Reserved 7 0 Reserved 01h Loop ontrol * R / W IP IP (harge Pump urrent) Bit 2,1,0 = {000 =1 µ, 001 = 2 µ, 010 = 4 µ = 64 µ, 111 = 128 µ}. Increasing the harge Pump urrent makes the loop respond faster, raising the loop bandwidth. he typical value when using the internal loop filter is 011. Reserved 3 Reserved VOD VO Divider Bit 5,4= {00 = 2, 01= 4, 10= 8, 11= 16} Reserved 6-7 Reserved 02h FdBk Div R / W FBD Feedback Divider LSBs (bits 0-7) 0 * 03h FdBk Div 1 * R / W FBD Feedback Divider MSBs (bits 8-11) Divider setting = 12 bit word + 8 Minimum 12 = Maximum 4103 = Reserved 4-7 Reserved 04h Reserved Reserved Reserved 05h Schmitt- R / W Schmitt trigger * control 0 1 Schmitt-trigger control 0=Schmitt-trigger, 1=No Schmitt-trigger Metal_Rev Metal Mask Revision Number 06h Output Enables R / W Reserved 0 0 Reserved OE 1 0 Output Enable for L, HSYN_out, VSYN_out 0=High Impedance (disabled), 1=Enabled Reserved Reserved MDS1527 G 5 Revision

6 Section 3 Register map summary Word ddress Name ccess Bit Name Bit # Reset Value Description 07h Reserved Reserved 0-6 Reserved Reserved 7 0 Part requires a 0 for correct operation 08h Reset Write Reserved Writing 5h resets part and commits values written to word addresses 01h-03h and 05h 09-0Fh Reserved Read Reserved 0-7 Reserved 10h hip Ver Read Reserved 0-7 Reserved 11h hip Rev Read hip Rev Reserved 12h Rd_Reg Read Reserved 0 N/ Reserved PLL_Lock 1 N/ PLL Lock Status 0=Unlocked, 1=Locked Reserved Reserved *. Written values to these registers do not take effect immediately, but require a commit via register 08h MDS 1527 G 6 Revision

7 Section 4 Programming Section 4 Programming 4.1 Industry-Standard I 2 Serial Bus: Data Format Figure 4-1 IS1527 Data Format for I 2 2-Wire Serial Bus Single/multiple register write (page write) S R Device address B 0 Word address Data (0)... Data (n) S O P Single/multiple register read Device address Word address Device address Data (0) Data (n) S R B 0 S R B 1... N S O O P Sequential single/multiple register read S R Device address B 1 Data (0)... Data (n) N S O O P Master drives line Slave drives line Notes: he IS1527 uses 16 byte pages (00h-0Fh is the first page, 10h-1Fh is the second page). Writing or reading beyond the end of page yields undefined results. he IS1527 has a device address of B, where B is the state of the I2DR pin. MDS1527 G 7 Revision

8 Section 5 /D Operating onditions Section 5 /D Operating onditions 5.1 bsolute Maximum Ratings able 5-1 lists absolute maximum ratings for the IS1527. Stresses above these ratings can cause permanent damage to the device. hese ratings, which are standard values for IS commercially rated parts, are stress ratings only. Functional operation of the IS1527 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. able 5-1 IS1527 bsolute Maximum Ratings Item Rating VDD, VDD, VDDQ (measured to VSS) * 4.3 V Digital Inputs VSS 0.3 V to 5.5 V nalog Inputs VSS -0.3 V to 6.0 V nalog Outputs VSS 0.3 V to VDD +0.3 V Digital Outputs VSSQ 0.3 V to VDDQ +0.3 V Storage emperature 65 to +150 Junction emperature 125 Soldering emperature 260 ESD Susceptibility* > 2 V ** *. Measured with respect to VSS. During normal operations, the VDD supply voltage for the IS1527 must remain within the recommended operating conditions. **. Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation. able 5-2 Environmental onditions Parameter Min. yp. Max. Units mbient Operating emperature Power Supply Voltage V able 5-3 D haracteristics Parameter Symbol onditions Min. Max. UNIS Digital Supply urrent IDDD VDDD = 3.6 V - 25 m Output Driver Supply urrent IDDQ VDDD = 3.6 V - 6 m No drivers enabled nalog Supply urrent IDD VDD = 3.6 V - 5 m Power consumption 300 mw Power-On-Reset (POR) VSS 1.8 V hreshold MDS 1527 G 8 Revision

9 Section 5 /D Operating onditions General able 5-4 haracteristics Parameter Symbol Min. ypical Max. Units Notes VO Frequency f VO MHz VO Gain 165 MHz/V Inputs EXFB Input Frequency f EXFB 8 10,000 khz EXFB Input High Voltage V IH 2.0 V EXFB Input Low Voltage V IL 1.0 V nalog Input (HSYN/VSYN) HSYN Input Frequency f HSYN 8 10,000 khz VSYN Input Frequency f VSYN Hz Input High Voltage V IH V Input Low Voltage V IL VSS V Input Hysteresis V Schmitt trigger active SD, SL Digital Inputs Input High Voltage V IH V Input Low Voltage V IL VSS V I 2 DDR Digital Input Input High Voltage V IH 2 VDD+0.3 V Input Low Voltage V IL VSS V SD Digital Output SD Output Low Voltage V OL 0.4 V IOU = 3 m SD Output High Voltage V OH 6.0 V Determined by external Rset resistor LVMOS Outputs (L, HSYN_out, VSYN_out, LO) Output Frequency, F s MHz VDDD = 3.3 V IS GLF Output Frequency, F s MHz VDDD = 3.3 V IS GLF Duty ycle S D % 2 Jitter, SJ, RMS SJ ns 30 khz input to 50 Jitter, SJ, pk-pk SJ ns MHz output Jitter, Input-Output IOJ ns HSYN in to L out Output Low Voltage V OL 0.4 V IOU = 4 m Output High Voltage V OH 2.4 V IOU = -4 m HSYN to HSYN_out propagation delay (without Schmitt-trigger) 2 9 ns 1 MDS1527 G 9 Revision

10 Section 5 /D Operating onditions Parameter Symbol Min. ypical Max. Units Notes HSYN to HSYN_out propagation delay (with Schmitt-trigger) L to HSYN_out/ VSYN_out skew lock and HSYN_out/VSYN_out ransition ime - Rise lock and HSYN_out/VSYN_out ransition ime - Fall 6 10 ns ns R ns 2 F ns 2 LO ransition ime - Rise LR 3.0 ns 2 LO ransition ime - Fall LF 2.0 ns 2 Note 1 Measured between chosen edge of HSYN (00h:2) and rising edge of output Note 2 Measured at 110 MHz, 3.3 VD, 25 o, 15 pf, unterminated MDS 1527 G 10 Revision

11 Section 6 Package Outline and Package Dimensions Section 6 Package Outline and Package Dimensions 16-pin SSOP 4.40 mm body, 0.65 mm pitch Package dimensions are kept current with JEDE Publication No Millimeters Inches Symbol Min Max Min Max INDEX RE E1 E 1 2 D α c e b SEING PLNE aaa L Section 7 Ordering Information Part / Order Number Marking Shipping packaging Package emperature 1527G-60LF 1527G2LF ubes 16-pin SSOP 0 to G-60LF 1527G2LF ape & Reel 16-pin SSOP 0 to G-110LF 1527G1LF ubes 16-pin SSOP 0 to G-110LF 1527G1LF ape & Reel 16-pin SSOP 0 to +70 While the information presented herein has been checked for both accuracy and reliability, Integrated ircuit Systems (IS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. his product is intended for use in normal commercial applications. ny other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IS. IS reserves the right to change any circuitry or specifications without notice. IS does not authorize or warrant any IS product for use in life support devices or critical medical instruments. MDS1527 G 11 Revision

ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA

ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part