Features. R TOTAL (k ) TEMP. RANGE ( C)

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1 DATASHEET ISL35 Single Push Button Controlled Potentiometer (XDCP ) Low Noise, Low Power, 3 Taps, Push Button Controlled Potentiometer FN588 Rev. The Intersil ISL35 is a three-terminal digitally-controlled potentiometer (XDCP) implemented by a resistor array composed of 3 resistive elements and a wiper switching network. The ISL35 features a push button control, a shutdown mode, as well as an industry-leading µtqfn package. The push button control has individual and inputs for adjusting the wiper. To eliminate redundancy, the wiper position will automatically increment or decrement if one of these inputs is held longer than s. Forcing both and low for more than s activates shutdown mode. Shutdown mode disconnects the top of the resistor chain and moves the wiper to the lowest position, minimizing power consumption. The three terminals accessing the resistor chain naturally configure the ISL35 as a voltage divider. A rheostat is easily formed by floating an end terminal or connecting it to the wiper. V CC (SUPPLY VOLTAGE) CONTROL BLOCK V SS (GROUND) V SS O µtfqfn 9 8 V CC (TOP VIEW) 3 7 V SS 4 5 NO LONGER AVAILABLE OR SUPPORTED O SOIC (TOP VIEW) 4 5 V CC Features Solid-state volatile potentiometer Push button controlled Single or Auto increment/decrement - Fast Mode after s button press Shutdown Mode 3 wiper tap points - Zero scale wiper position on power-up Low power CMOS - to 5.5V - Terminal voltage, to V CC - Standby current, 3µA max R TOTAL value = k 5k Packages - 8 Ld SOIC and Ld µtqfn (.mmx.mm) Pb-free (RoHS compliant) Applications Volume Control LED/LCD Brightness Control Contrast Control Programming Bias Voltages Ladder Networks Ordering Information PART NUMBER PART MARKING R TOTAL (k ) TEMP. RANGE ( C) PACKAGE (Pb-free) PKG. DWG. # ISL35WFB8Z* (Note ) 35 WFBZ -4 to +5 8 Ld SOIC M8.5 ISL35WFRUZ-TK (Note ) (No longer available or supported) GA -4 to +5 Ld µtqfn L..x.A *Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES:. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN588 Rev. Page of

2 Pinouts V SS O 3 4 ISL35 (8 LD SOIC) TOP VIEW V CC V SS ISL35 ( LD ΜTQFN) TOP VIEW O V CC NO LONGER AVAILABLE OR SUPPORTED Pin Descriptions SOIC PIN µtqfn PIN SYMBOL BRIEF DESCRIPTION The is a negative-edge triggered input with internal pull-up. Toggling will move the wiper close to terminal. The is a negative-edge triggered input with internal pull-up. Toggling will move the wiper close to terminal. 3 3 The and pins of the ISL35 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is V CC. The terminology of and RL references the relative position of the terminal in relation to wiper movement direction selected by the / input. 4 4 V SS Ground 5 The pin is the wiper terminal of the potentiometer, which is equivalent to the movable terminal of a mechanical potentiometer. 7 The and pins of the ISL35 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is V CC. The terminology of and references the relative position of the terminal in relation to wiper movement direction selected by the / input. 7 5, 8, No connection 8 9 V CC Supply Voltage Block Diagrams V CC (SUPPLY VOLTAGE) 5-BIT UP/DOWN COUNTER CONTROL BLOCK ONE 8 OF THIRTY TWO DECODER TRANSFER GATES RESISTOR ARRAY V SS (GROUND) GENERAL DETAILED FN588 Rev. Page of

3 Absolute Maximum Ratings Storage Temperature C to +5 C Voltage at and Pin with Respect to GND. -.3V to V CC +.3 V CC V to +V Voltage at any DCP Pin with Respect to GND V to V CC I W (s) ±ma Latchup Class II, Level +5 C ESD Rating Human Body Model kV Machine Model V Thermal Information Thermal Resistance (Typical, Note 3, 4) JA ( C/W) JC ( C/W) 8 Lead SOIC Lead µtqfn Maximum Junction Temperature (Plastic Package) C Pb-free Reflow Profile see link below Recommended Operating Conditions Temperature Range (Extended Industrial) C to +5 C V CC V to 5.5V Power Rating mW Wiper Current ±3.mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the case temp location is the center of the exposed metal pad on the package underside. Potentiometer Specifications Over recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 8) TYP (Note 5) MAX (Note 8) UNIT R TOTAL to Resistance W option k U option 5 k to Resistance Tolerance - + % End-to-End Temperature Coefficient W option ±8 ppm/ C (Note ) U option ±5 ppm/ C (Note ) Wiper Resistance V CC = 3.3V, wiper current I RW = V CC /R TOTAL 3 4 V RH, V RL V RH and V RL Terminal Voltages V RH and V RL to GND V CC V Noise on Wiper Terminal From Hz to MHz -8 dbv C H /C L /C W (Note 7) Potentiometer Capacitance //5 pf I LkgDCP Leakage on DCP Pins Voltage at pin from GND to V CC.5.4 µa VOLTAGE DIVIDER MODE ; V ; measured at unloaded) INL (Note ) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) TC V (Note ) Integral Non-linearity - LSB (Note ) Differential Non-linearity Monotonic over all tap positions LSB (Note ) Zero-scale Error W option.3 3 LSB U option.3 (Note ) Full-scale Error W option LSB U option (Note ) Ratiometric Temperature Coefficient Wiper from 5 hex to F hex for W and U option ±5 ppm/ C f CUTOFF 3dB Cut-Off Frequency Wiper at the middle scale, W option 5 khz Wiper at the middle scale, U option 75 khz RESISTOR MODE (Measurements between and with not connected, or between and with not connected) RINL (Note 5) Integral Non-linearity DCP register set between hex and F hex; monotonic over all tap positions; W option DCP register set between hex and F hex; monotonic over all tap positions; U option MI (Note ) - MI (Note ) FN588 Rev. Page 3 of

4 Potentiometer Specifications RDNL (Note 4) Roffset (Note 3) Over recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 8) TYP (Note 5) MAX (Note 8) Differential Non-linearity W and U option MI (Note ) Offset W option 3 MI (Note ) U option.5 MI (Note ) DC Electrical Specifications Over recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS I CC V CC Active Current, perform wiper move operation MIN (Note 8) TYP (Note 5) MAX (Note 8) UNIT UNIT 5 µa I SB Standby Current. 3 µa I Lkg, Input Leakage Current V IN = V SS to V CC - + µa V IH, Input HIGH Voltage V CC x.7 V V IL, input LOW Voltage V CC x. V C IN (Note 7), Input Capacitance V CC = 3.3V, T A = +5 C, f = MHz pf Rpull_up (Note 7) Pull-up Resistor for and M AC Electrical Specifications Over recommended operating conditions unless otherwise specified. SYMBOL PARAMETER MIN (Note 8) TYP (Note 5) MAX (Note 8) UNIT t GAP Time Between Two Separate Push Button Events ms t DB Debounce Time 5 3 ms t S SLOW Wiper Change on a Slow Mode ms t S FAST Wiper Change on a Fast Mode ms t stdn (Note 7) Time to Enter Shutdown Mode (keep and LOW) s t R VCC V CC Power-up Rate. 5 V/ms NOTES: 5. Typical values are for T A = +5 C and 3.3V supply voltage.. LSB: [V(RW) 3 V(RW) ]/3. V(RW) 3 and V(RW) are voltage on RW pin for the DCP register set to F hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW) /LSB. 8. FS error = [V(RW) 3 V CC ]/LSB. 9. DNL = [V(RW) i V(RW) i- ]/LSB -, for i = to 3; i is the DCP register setting.. INL = [V(RW) i i LSB V(RW)]/LSB for i = to 3 Max V RW. i Min V RW i TC for i = 5 to 3 decimal, T = -4 C to +5 C. Max( ) is the maximum value of the wiper V = Max V RW i + Min V RW i +5 Cvoltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.. MI = RW 3 RW /3. MI is a minimum increment. RW 3 and RW are the measured resistances for the DCP register set to F hex and hex respectively. 3. Roffset = RW /MI, when measuring between RW and RL. Roffset = RW 3 /MI, when measuring between RW and RH. 4. RDNL = (RW i RW i- )/MI, for i = to RINL = [RW i (MI i) RW ]/MI, for i = to 3.. Max Ri Min Ri for i = 5 to 3, T = -4 C to +5 C. Max( ) is the maximum value of the resistance and Min ( ) is TC R = Max Ri + Min Ri +5 Cthe minimum value of the resistance over the temperature range. 7. Limits should be considered typical and are not production tested. 8. Parts are % tested at +5 C. Over-temperature limits established by characterization and are not production tested. FN588 Rev. Page 4 of

5 Slow Mode Timing t DB t GAP MI * V W * MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage. Fast Mode Timing t DB t S FAST t S SLOW V W MI * s * MI in the AC timing diagram refers to the minimum incremental change in the wiper voltage. Shutdown Mode Timing t DB s SHUTDOWN MODE V W FN588 Rev. Page 5 of

6 Typical Performance Curves WIPER RESISTAE ( ) ºC +5ºC -4ºC I CC (µa) FIGURE. WIPER RESISTAE vs TAP POSITION [ I(RW) = V CC /R TOTAL ] FOR k (W) TEMPERATURE ( C) FIGURE. STANDBY I CC vs TEMPERATURE DNL (LSB) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR k (W) INL (LSB) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR k (W). ZERO SCALE ERROR (LSB) FULL SCALE ERROR (LSB) TEMPERATURE ( C) FIGURE 5. ZS ERROR vs TEMPERATURE TEMPERATURE ( C) FIGURE. FS ERROR vs TEMPERATURE FN588 Rev. Page of

7 Typical Performance Curves (Continued)..8.. RDNL (LSB). -. RINL (LSB) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR k (W) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR k (W) R TOTAL CHANGE (%) k TCv (ppm/ C) k 5k 5k TEMPERATURE ( C) FIGURE 9. END-TO-END R TOTAL % CHANGE vs TEMPERATURE FIGURE. TC FOR VOLTAGE DIVIDER MODE IN ppm INT SINEWAVE 3 5 TCr (ppm/ C) 5 5 5k k 3dB CUTOFF = 5kHz MIDSCALE OUTT FIGURE. TC FOR RHEOSTAT MODE IN ppm FIGURE. FREQUEY RESPONSE (5kHz) FN588 Rev. Page 7 of

8 Power-up and Power-down Requirements There are no restrictions on the power-up or power-down conditions of V CC and the voltages applied to the potentiometer pins provided that V CC is always more positive than or equal to V RH and V RL, i.e., V CC V RH, V RL. The V CC ramp rate specification is always in effect. Pin Descriptions and The and pins of the ISL35 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is V SS and the maximum is V CC. The terminology of and references the relative position of the terminal in relation to wiper movement direction. The pin is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. The default wiper position at power-up is at tap. The debounced input is used to increment the wiper position. An on-chip pull-up holds the input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent higher tap position. The debounced input is used to decrement the wiper position. An on-chip pull-up holds the input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent lower tap position. Device Operation There are three sections of the ISL35: the input control, the counter and decode section and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch, connecting a point on the resistor array to the wiper output. The resistor array is comprised of 3 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The ISL35 is designed to interface directly to two push button switches for effectively moving the wiper up or down. The and inputs increment or decrement a 5-bit counter respectively. The output of this counter is decoded to select one of the thirty-two wiper positions along the resistive array. The wiper increment input, and the wiper decrement input, are both connected to an internal pull-up so that they normally remain HIGH. When pulled LOW by an external push button switch or a logic LOW level input, the wiper will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wiper position if or remain LOW for less than 5ms, typical. Each of the buttons can be pushed either once for a single increment/decrement or continuously for a multiple increments/decrements. The number of increments/decrements of the wiper position depend on how long the button is being pushed. When making a continuous push, after the first second, the increment/decrement speed increases. For the first second, the device will be in the slow scan mode. Then, if the button is held for longer than s, the device will go into the fast scan mode. As soon as the button is released, the ISL35 will return to a stand-by condition. If both and buttons are pulled low more than 5ms from each other, all commands are ignored upon release of ALL buttons. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. Shutdown Mode The ISL35 enters into Shutdown Mode if both and inputs are kept LOW for s. In this mode, the resistors array is totally disconnected from its pin and the wiper is moved to the position closest to the pin, as shown in Figure 3. FIGURE 3. DCP CONNECTION IN SHUTDOWN MODE Note that and inputs must be brought LOW within t DB time window of 5ms (see Shutdown Mode Timing on page 5) otherwise all commands will be ignored until both inputs are released. Holding either or input LOW for more than 5ms will exit shutdown mode and return wiper to prior shutdown position. If or will be held LOW for more than 5ms, the ISL35 will start auto-increment or auto-decrement of wiper position. R TOTAL with V CC Removed The end-to-end resistance of the array will fluctuate once V CC is removed. FN588 Rev. Page 8 of

9 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN Ordering Information Table on page. - Added Revision History. - Added About Intersil Verbiage. -Updated POD M8.5 to most current revision with changes as follows: -Revision to Revision Changes: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern -Revision to Revision 3 Changes: Changed in Typical Recommended Land Pattern the following:.4(.95) to.(.87).7 (.3) to.(.3). to 5.(.5) -Revision 3 to Revision 4 Changes: Changed Note "98" to "994" About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC 7-5. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN588 Rev. Page 9 of

10 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) NX (b) 5 INDEX AREA X PIN # ID X. C. C.5 C SEATING PLANE (DATUM A) N SECTION "C-C" N- N. C (A) A e A D TOP VIEW SIDE VIEW 3 (ND-) X e NX L BOTTOM VIEW C C e C L NX b 5 A (DATUM B) B E 4xk. M C A B.5 M C FOR ODD TERMINAL/SIDE b L C TERMINAL TIP L..x.A LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE SYMBOL MILLIMETERS MIN NOMINAL MAX NOTES A A A3.7 REF - b D E e.5 BSC - k L N Nd 4 3 Ne 3-4 Rev. 3 / NOTES:. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.5mm and.3mm from the terminal tip.. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 7. Maximum package warpage is.5mm. 8. Maximum allowable burrs is.7mm in all directions. 9. Same as JEDEC MO-55UABD except: No lead-pull-back, "A" MIN dimension =.45 not.5mm "L" MAX dimension =.45 not.4mm.. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB MIN L MIN DETAIL A PIN ID.5.5 LAND PATTERN FN588 Rev. Page of

11 Package Outline Drawing M8.5 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, / DETAIL "A".7 (.5).4 (.) INDEX AREA 4. (.57) 3.8 (.5). (.44) 5.8 (.8).5 (.).5 (.) x 45 3 TOP VIEW 8 SIDE VIEW B.5 (.).9 (.8). (.87) SEATING PLANE 8 5. (.97) 4.8 (.89).75 (.9).35 (.53) 7. (.3).7 (.5) 3 -C-.7 (.5).5(.).33(.3).5(.).(.4) (.5) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y4.5M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (. inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only.. The lead width as measured.3mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.mm (.4 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS--AA ISSUE C. FN588 Rev. Page of