DATASHEET. Features. Applications ISL Single, Low Voltage Digitally Controlled Potentiometer (XDCP ) FN7778 Rev 2.

Transcription

1 DTSHEET Single, Low Voltage Digitally ontrolled Potentiometer (XDP ) FN7778 Rev 2. The is a volatile, low voltage, low noise, low power, I 2 Bus, 256 Taps, single digitally controlled potentiometer (DP), which integrates DP core, wiper switches and control logic on a monolithic MOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and MOS switches. The position of the wipers are controlled by the user through the I 2 bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the s wiper will always commence at mid-scale (128 tap position). The low voltage, low power consumption, and small package of the make it an ideal choice for use in battery operated equipment. In addition, the has a V LOGI pin allowing down to 1.2V bus operation, independent from the V value. This allows for low logic levels to be connected directly to the without passing through a voltage level shifter. The DP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features 256 resistor taps I 2 serial interface - No additional level translator for low bus supply - Two address pins allow up to four devices per bus Power supply - V = 1.7V to 5.5V analog power supply - V LOGI = 1.2V to 5.5V I 2 bus/logic power supply Wiper resistance: 7 V = 3.3V Shutdown Mode - forces the DP into an end-to-end open circuit and R W is shorted to R L internally Power-on preset to mid-scale (128 tap position) Shutdown and standby current <2.8µ max DP terminal voltage from V to V 1k 5k or 1k total resistance Extended industrial temperature range: -4 to Ld MSOP or 1 Ld µtqfn packages Pb-free (RoHS compliant) pplications Power supply margining RF power amplifier bias compensation LD bias compensation Laser diode bias compensation 1 8 RESISTNE (Ω) FIGURE 1. FORWRD ND BKWRD RESISTNE vs TP POSITION, 1k DP FIGURE 2. V REF DJUSTMENT FN7778 Rev 2. Page 1 of 2

2 Block Diagram V LOGI V SL SD 1 I/O BLOK LEVEL SHIFTER POWER-UP INTERFE, ONTROL ND STTUS LOGI WR VOLTILE REGISTER ND WIPER ONTROL IRUITRY R H R L R W GND Pin onfigurations (1 LD MSOP) TOP VIEW Pin Descriptions MSOP µtqfn SYMBOL DESRIPTION 1 1 V LOGI I 2 bus /logic supply. Range 1.2V to 5.5V V LOGI SL SD GND V RH 2 1 SL Logic Pin - Serial bus clock input 3 2 SD Logic Pin - Serial bus data input/open drain output RW RL 4 3 Logic Pin - Hardwire slave address pin for I 2 serial bus. Range: V LOGI or GND (1 LD µtqfn) TOP VIEW Logic Pin - Hardwire slave address pin for I 2 serial bus. Range: V LOGI or GND V LOGI 6 5 RL DP low terminal 7 6 RW DP wiper terminal SL SD GND V RH RW RL 8 7 RH DP high terminal 9 8 V nalog power supply. Range 1.7V to 5.5V 1 9 GND Ground pin FN7778 Rev 2. Page 2 of 2

3 Ordering Information PRT NUMBER (Note 5) PRT MRKING RESISTNE OPTION (kω) TEMP RNGE ( ) PKGE (Pb-free) PKG. DWG. # TFUZ (Notes 1, 3) 3315T 1-4 to Ld MSOP M1.118 UFUZ (Notes 1, 3) (No longer available, recommended replacement: TFUZ-TK) 3315U 5-4 to Ld MSOP M1.118 WFUZ (Notes 1, 3) 3315W 1-4 to Ld MSOP M1.118 TFRUZ-T7 (Notes 2, 4) HB 1-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 TFRUZ-TK (Notes 2, 4) HB 1-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 UFRUZ-T7 (Notes 2, 4) (No longer available, recommended replacement: TFUZ-TK) UFRUZ-TK (Notes 2, 4) (No longer available, recommended replacement: TFUZ-TK) WFRUZ-T7 (Notes 2, 4) (No longer available, recommended replacement: TFUZ-TK) WFRUZ-TK (Notes 2, 4) (No longer available, recommended replacement: TFUZ-TK) H 5-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 H 5-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 GZ 1-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 GZ 1-4 to Ld 2.1x1.6 µtqfn L1.2.1x1.6 NOTES: 1. dd -TK or -T7 suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 1% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2 5. For Moisture Sensitivity Level (MSL), please see device information page for. For more information on MSL please see techbrief TB363. FN7778 Rev 2. Page 3 of 2

4 bsolute Maximum Ratings Supply Voltage Range V V to 6.V V LOGI V to 6.V Voltage on ny DP Terminal Pin V to 6.V Voltage on ny Digital Pins V to 6.V Wiper current I W (1s) ±6m ESD Rating Human Body Model (Tested per JESD22-114E) kV DM Model (Tested per JESD22-114E) kV Machine Model (Tested per JESD ) V Latch Up (Tested per JESD-78B; lass 2, Level ) Thermal Information Thermal Resistance (Typical) J ( /W) J ( /W) 1 Ld MSOP Package (Notes 6, 7) Ld µtqfn Package (Notes 6, 7) Maximum Junction Temperature (Plastic Package) Storage Temperature Range to +15 Pb-Free Reflow Profile see link below Recommended Operating onditions Temperature to +125 V Supply Voltage V to 5.5V V LOGI Supply Voltage V to 5.5V DP Terminal Voltage to V Max Wiper urrent ±3m UTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For J, the case temp location is the center top of the package. nalog Specifications V = 2.7V to 5.5V, V LOGI = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -4 to SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS R TOTL R H to R L Resistance W option 1 k U option 5 k T option 1 k R H to R L Resistance Tolerance -2 ±2 +2 % End-to-End Temperature oefficient W option 175 ppm/ U option 85 ppm/ T option 7 ppm/ V RH, V RL DP Terminal Voltage V RH or V RL to GND V V R W Wiper Resistance R H - floating, V RL = V, force I W current to the wiper, I W = (V - V RL )/R TOTL, V = 2.7V to 5.5V 7 2 V = 1.7V 58 H / L / W Terminal apacitance See DP Macro Model on page 9 32 pf I LkgDP Leakage on DP Pins Voltage at pin from GND to V -.4 <.1.4 µ Noise Resistor Noise Density Wiper at middle point, W option 16 Wiper at middle point, U option 49 Wiper at middle point, T option 61 nv nv nv Hz Hz Hz Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 db PSRR Power Supply Reject Ratio Wiper output change if V change ±1%; wiper at middle point -75 db FN7778 Rev 2. Page 4 of 2

5 nalog Specifications V = 2.7V to 5.5V, V LOGI = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -4 to (ontinued) SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS VOLTGE DIVIDER MODE RL; RH; measured at RW, unloaded) INL (Note 13) DNL (Note 12) Integral Non-linearity, Guaranteed Monotonic Differential Non-linearity, Guaranteed Monotonic W option -1. ± LSB (Note 9) U, T option -.5 ± LSB (Note 9) W option -1 ±.4 +1 LSB (Note 9) U, T option -.4 ± LSB (Note 9) FSerror (Note 11) Full-scale Error W option LSB (Note 9) U, T option LSB (Note 9) ZSerror (Note 1) Zero-scale Error W option LSB (Note 9) U, T option.4 2 LSB (Note 9) T V (Notes 14) Ratiometric Temperature oefficient W option, Wiper Register set to 8 hex 8 ppm/ U option, Wiper Register set to 8 hex 4 ppm/ T option, Wiper Register set to 8 hex 2.3 ppm/ Large Signal Wiper Settling Time From code to FF hex 3 ns f cutoff -3dB utoff Frequency Wiper at middle point W option 12 khz Wiper at middle point U option 25 khz Wiper at middle point T option 12 khz RHEOSTT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) R INL (Note 18) R DNL (Note 17) Integral Non-linearity, Guaranteed Monotonic Differential Non-linearity, Guaranteed Monotonic W option; V = 2.7V to 5.5V -2. ±1 +2. MI W option; V = 1.7V 1.5 MI U, T option; V = 2.7V to 5.5V -1. ± MI U, T option; V = 1.7V 2.1 MI W option; V = 2.7V to 5.5V -1 ±.4 +1 MI W option; V = 1.7V ±.6 MI U, T option; V = 2.7V to 5.5V -.5 ± MI U, T option; V = 1.7V ±.35 MI FN7778 Rev 2. Page 5 of 2

6 nalog Specifications V = 2.7V to 5.5V, V LOGI = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -4 to (ontinued) SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS R offset (Note 16) Offset, Wiper at Position W option; V = 2.7V to 5.5V MI W option; V = 1.7V 6.3 MI U, T option; V = 2.7V to 5.5V.5 2 MI U, T option; V = 1.7V 1.1 MI TR (Note 19) Resistance Temperature oefficient W option; Wiper register set between 32 hex and FF hex 22 ppm/ U option; Wiper register set between 32 hex and FF hex 1 ppm/ T option; Wiper register set between 32 hex and FF hex 75 ppm/ Operating Specifications V = 2.7V to 5.5V, V LOGI = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -4 to SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS I LOGI V LOGI Supply urrent (Write/Read) V LOGI = 5.5V, V = 5.5V, f SL = 4 khz (for I 2 active read and write) V LOGI = 1.2V, V = 1.7V, f SL = 4 khz (for I 2 active read and write) 2 µ 5 µ I V Supply urrent (Write/Read) V LOGI = 5.5V, V = 5.5V 18 µ V LOGI = 1.2V, V = 1.7V 1 µ I LOGI SB V LOGI Standby urrent V LOGI = V = 5.5V, I 2 interface in standby V LOGI = 1.2V, V = 1.7V, I 2 interface in standby I SB V Standby urrent V LOGI = V = 5.5V, I 2 interface in standby V LOGI = 1.2V, V = 1.7V, I 2 interface in standby 1.3 µ.4 µ 1.5 µ 1 µ I LOGI SHDN V LOGI Shutdown urrent V LOGI = V = 5.5V, I 2 interface in standby 1.3 µ V LOGI = 1.2V, V = 1.7V, I 2 interface in standby.4 µ I SHDN V Shutdown urrent V LOGI = V = 5.5V, I 2 interface in standby V LOGI = 1.2V, V = 1.7V, I 2 interface in standby 1.5 µ 1 µ FN7778 Rev 2. Page 6 of 2

7 Operating Specifications V = 2.7V to 5.5V, V LOGI = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -4 to (ontinued) SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS t DP Wiper Response Time W option; SL rising edge of the acknowledge bit after data byte to wiper new position from 1% to 9% of the final value. U option; SL rising edge of the acknowledge bit after data byte to wiper new position from 1% to 9% of the final value. T option; SL rising edge of the acknowledge bit after data byte to wiper new position from 1% to 9% of the final value..4 µs 1.5 µs 3.5 µs I LkgDig Leakage urrent, at Pins, 1, SD, SL Voltage at pin from GND to V LOGI -.4 <.1.4 µ tshdnrec DP Recall Time from Shutdown Mode SL rising edge of the acknowledge bit after R data byte to wiper recalled position and RH connection 1.5 µs V, V LOGI Ramp (Note 21) V, V LOGI Ramp Rate Ramp monotonic at any level.1 5 V/ms Serial Interface Specification for SL, SD,, 1 Unless Otherwise Noted. SYMBOL PRMETER TEST ONDITIONS MIN (Note 2) TYP (Note 8) MX (Note 2) UNITS V IL Input LOW Voltage x V LOGI V V IH Input HIGH Voltage.7 x V LOGI V LOGI +.3 V Hysteresis SD and SL Input Buffer V LOGI > 2V.5 x V LOGI V Hysteresis V LOGI <2V.1 x V LOGI V OL SD Output Buffer LOW Voltage I OL = 3m, V LOGI > 2V.4 V I OL = 1.5m,.2 x V LOGI V V LOGI <2V pin SD, SL Pin apacitance 1 pf f SL SL Frequency 4 khz t sp Pulse Width Suppression Time at SD and SL Inputs ny pulse narrower than the max spec is suppressed 5 ns t t BUF SL Falling Edge to SD Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission SL falling edge crossing 3% of V LOGI, until SD exits the 3% to 7% of V LOGI window SD crossing 7% of V LOGI during a STOP condition, to SD crossing 7% of V LOGI during the following STRT condition t LOW lock LOW Time Measured at the 3% of V LOGI crossing t HIGH lock HIGH Time Measured at the 7% of V LOGI crossing t SU:ST STRT ondition Set-up Time SL rising edge to SD falling edge; both crossing 7% of V LOGI 9 ns 13 ns 13 ns 6 ns 6 ns FN7778 Rev 2. Page 7 of 2

8 Serial Interface Specification for SL, SD,, 1 Unless Otherwise Noted. (ontinued) SYMBOL PRMETER TEST ONDITIONS t HD:ST STRT ondition Hold Time From SD falling edge crossing 3% of V LOGI to SL falling edge crossing 7% of V LOGI t SU:DT Input Data Set-up Time From SD exiting the 3% to 7% of V LOGI window, to SL rising edge crossing 3% of V LOGI t HD:DT Input Data Hold Time From SL falling edge crossing 7% of V to SD entering the 3% to 7% of V window t SU:STO STOP ondition Set-up Time From SL rising edge crossing 7% of V LOGI, to SD rising edge crossing 3% of V LOGI t HD:STO STOP ondition Hold Time for Read or Write From SD rising edge to SL falling edge; both crossing 7% of V (Note 11) t DH Output Data Hold Time From SL falling edge crossing 3% of V LOGI, until SD enters the 3% to 7% of V LOGI window. I OL =3m,V LOGI > 2V. I OL =.5m, V LOGI < 2V MIN (Note 2) TYP (Note 8) MX (Note 2) 6 ns 1 ns ns 6 ns 13 ns ns t R SD and SL Rise Time From 3% to 7% of V LOGI x b 25 ns t F SD and SL Fall Time From 7% to 3% of V LOGI x b 25 ns b apacitive Loading of SD or SL Total on-chip and off-chip (Note 11) 1 4 pf t SU: 1, Setup Time Before STRT condition 6 ns t HD: 1, Hold Time fter STOP condition 6 ns NOTES: 8. Typical values are for T = +25 and 3.3V supply voltages. 9. LSB = [V(RW) 255 V(RW) ]/255. V(RW) 255 and V(RW) are V(RW) for the DP register set to FF hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 1. ZS error = V(RW) /LSB. 11. FS error = [V(RW) 255 V ]/LSB. 12. DNL = [V(RW) i V(RW) i-1 ]/LSB-1, for i = 1 to 255. i is the DP register setting. 13. INL = [V(RW) i i LSB V(RW) ]/LSB for i = 1 to Max V RW i Min V RW i 1 for i = 16 to 255 decimal, T = -4 to Max( ) is the maximum value of the wiper T V = VRW voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. i MI = RW 255 RW /255. MI is a minimum increment. RW 255 and RW are the measured resistances for the DP register set to FF hex and hex respectively. 16. Roffset = RW /MI, when measuring between RW and RL. Roffset = RW 255 /MI, when measuring between RW and RH. 17. RDNL = (RW i RW i-1 )/MI -1, for i = 16 to RINL = [RW i (MI i) RW ]/MI, for i = 16 to Max Ri Min Ri 1 6 for i = 16 to 255, T = -4 to Max( ) is the maximum value of the resistance and Min( ) is the T R = Ri minimum value of the resistance over the temperature range. 2. ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. It is preferable to ramp up both the V LOGI and the V supplies at the same time. If this is not possible it is recommended to ramp-up the V LOGI first followed by the V. UNITS FN7778 Rev 2. Page 8 of 2

9 DP Macro Model R TOTL RH H W L 32pF RL 32pF 32pF RW Timing Diagrams SD vs SL Timing t F t HIGH t LOW t R t sp SL t SU:DT t SU:ST t HD:ST t HD:DT t SU:STO SD (INPUT TIMING) t t DH t BUF SD (OUTPUT TIMING) and 1 Pin Timing STRT STOP SL LK 1 SD t SU: t HD:, 1 FN7778 Rev 2. Page 9 of 2

10 RDNL (MI) RDNL (MI) INL (LSB) INL (LSB) DNL (LSB) DNL (LSB) Typical Performance urves FIGURE 3. 1k DNL vs TP POSITION, V = 5V FIGURE 4. 5k DNL vs TP POSITION, V = 5V FIGURE 5. 1k INL vs TP POSITION, V = 5V FIGURE 6. 5k INL vs TP POSITION, V = 5V FIGURE 7. 1k RDNL vs TP POSITION, V = 5V FIGURE 8. 5k RDNL vs TP POSITION, V = 5V FN7778 Rev 2. Page 1 of 2

11 Tv (ppm/ ) Tv (ppm/ ) WIPER RESISTNE ( ) WIPER RESISTNE ( ) RINL (MI) RINL (MI) Typical Performance urves (ontinued) FIGURE 9. 1k RINL vs TP POSITION, V = 5V FIGURE 1. 5k RINL vs TP POSITION, V = 5V FIGURE 11. 1k WIPER RESISTNE vs TP POSITION, V = 5V FIGURE 12. 5k WIPER RESISTNE vs TP POSITION, V = 5V FIGURE 13. 1k Tv vs TP POSITION FIGURE 14. 5k Tv vs TP POSITION FN7778 Rev 2. Page 11 of 2

12 Tr (ppm/ ) Tr (ppm/ ) Typical Performance urves (ontinued) Tr (ppm/ ) FIGURE 15. 1k Tr vs TP POSITION FIGURE 16. 5k Tr vs TP POSITION Tv (ppm/ ) FIGURE 17. 1k Tv vs TP POSITION FIGURE 18. 1k Tr vs TP POSITION SL LOK RW PIN 1mV/DIV 1µs/DIV FIGURE 19. WIPER DIGITL FEED-THROUGH 2mV/DIV 5µs/DIV FIGURE 2. WIPER TRNSITION GLITH FN7778 Rev 2. Page 12 of 2

13 Typical Performance urves (ontinued) 1V/DIV 1µs/DIV 1V/DIV.1s/DIV WIPER SL 9TH LOK OF THE DT BYTE (K) FIGURE 21. WIPER LRGE SIGNL SETTLING TIME FIGURE 22. POWER-ON STRT-UP IN VOLTGE DIVIDER MODE H1:.5V/DIV,.2µs/DIV RH PIN H2:.2V/DIV,.2µs/DIV RW PIN STNDBY URRENT I (µ) V = 5.5V, V LOGI = 5.5V V = 1.7V, V LOGI = 1.2V R TOTL = 1k -3dB FREQUENY = 1.4MHz T MIDDLE TP FIGURE 23. 1k -3dB UT OFF FREQUENY Functional Pin Descriptions Potentiometers Pins RH ND RL The high (R H ) and low (R L ) terminals of the are equivalent to the fixed terminals of a mechanical potentiometer. R H and R L are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to R H, and with the WR set to, the wiper is closest to R L. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register FIGURE 24. STNDBY URRENT vs TEMPERTURE Bus Interface Pins TEMPERTURE ( ) SERIL DT INPUT/OUTPUT (SD) The SD is a bidirectional serial data input/output pin for I 2 interface. It receives device address, operation code, wiper address and data from an I 2 external master device at the rising edge of the serial clock SL, and it shifts out data after each falling edge of the serial clock. SD requires an external pull-up resistor, since it is an open drain input/output. SERIL LOK (SL) This input is the serial clock of the I 2 serial interface. SL requires an external pull-up resistor, since a master is an open drain output. FN7778 Rev 2. Page 13 of 2

14 DEVIE DDRESS (1, ) The address inputs are used to set the least significant 2 bits of the 7-bit I 2 interface slave address. match in the slave address serial data stream must match with the ddress input pins in order to initiate communication with the. maximum of four devices may occupy the I 2 serial bus (see Table 3). V LOGI This is an input pin, that supplies internal level translator for serial bus operation from 1.2V to 5.5V. Principles of Operation The is an integrated circuit incorporating one DP with its associated registers and an I 2 serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. t either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a make before break mode when the wiper changes tap positions. Voltage at any DP pins, R H, R L or R W, should not exceed V level at any conditions during power-up and normal operation. The V LOGI pin needs to be connected to the I 2 bus supply which allows reliable communication with the wide range of microcontrollers and independent of the V level. This is extremely important in systems where the master supply has lower levels than DP analog supply. DP Description The DP is implemented with a combination of resistor elements and MOS switches. The physical ends of each DP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DP contains all zeroes (WR[7:]= h), its wiper terminal (RW) is closest to its Low terminal (RL). When the WR register of a DP contains all ones (WR[7:]= FFh), its wiper terminal (RW) is closest to its High terminal (RH). s the value of the WR increases from all zeroes () to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. t the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the is being powered up, the WR is reset to 8h (128 decimal), which locates RW roughly at the center between R L and R H. The WR can be read or written to directly using the I 2 serial interface as described in the following sections. Memory Description The contains two volatile 8-bit registers: Wiper Register (WR) and ccess ontrol Register (R). The memory map of is shown in Table 1. The Wiper Register (WR) at address contains current wiper position. The ccess ontrol Register (R) at address 1h contains information and control bits described in Table 2. DDRESS (hex) Shutdown Function TBLE 1. MEMORY MP VOLTILE REGISTER NME DEFULT SETTING (hex) 1 R 4 WR 4 TBLE 2. ESS ONTROL REGISTER (R) BIT # NME/ VLUE SHDN The SHDN bit (R[6]) disables or enables shutdown mode for all DP channels simultaneously. When this bit is, i.e., DP is forced to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor, as shown in Figure 25. Default value of the SHDN bit is 1. 2kΩ RH FIGURE 25. DP ONNETION IN SHUTDOWN MODE In the shutdown mode, the RW terminal is shorted to the RL terminal with around 2kΩ resistance, as shown in Figure 25. When the device enters shutdown, all current DP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than.2µs to.4µs, the wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. RW RL FN7778 Rev 2. Page 14 of 2

15 WIPER VOLTGE, V RW (V) POWER-UP USER PROGRMMED FIGURE 26. SHUTDOWN MODE WIPER RESPONSE I 2 Serial Interface The supports an I 2 bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the operates as a slave device in all applications. ll communication over the I 2 interface is conducted by sending the MSB of each byte of data first. Protocol onventions MID SLE = 8H SHDN TIVTED SHDN RELESED SHDN MODE TIME (s) FTER SHDN WIPER RESTORE TO THE ORIGINL POSITION Data states on the SD line must change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating STRT and STOP conditions (see Figure 27). On power-up of the, the SD pin is in the input mode. ll I 2 interface operations must begin with a STRT condition, which is a HIGH-to-LOW transition of SD while SL is HIGH. The continuously monitors the SD and SL lines for the STRT condition and does not respond to any command until this condition is met (see Figure 27). STRT condition is ignored during the power-up of the device. ll I 2 interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (see Figure 27). STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. n K (cknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SD bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The responds with an K after recognition of a STRT condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. The also responds with an K after receiving a Data Byte of a write operation. The master must respond with an K after receiving a Data Byte of a read operation. valid Identification Byte contains 11 as the five MSBs, and the following two bits matching the logic values present at pins 1 and. The LSB is the Read/Write bit. Its value is 1 for a Read operation and for a Write operation (see Table 3). TBLE 3. IDENTIFITION BYTE FORMT LOGI VLUES T PINS 1 ND, RESPETIVELY R/W (MSB) (LSB) SL SD STRT DT DT DT STOP STBLE HNGE STBLE FIGURE 27. VLID DT HNGES, STRT ND STOP ONDITIONS FN7778 Rev 2. Page 15 of 2

16 SL FROM MSTER SD OUTPUT FROM TRNSMITTER HIGH IMPEDNE SD OUTPUT FROM REEIVER HIGH IMPEDNE STRT K FIGURE 28. KNOWLEDGE RESPONSE FROM REEIVER WRITE SIGNLS FROM THE MSTER S T R T IDENTIFITION BYTE DDRESS BYTE DT BYTE S T O P SIGNL T SD SIGNLS FROM THE SLVE K K K FIGURE 29. BYTE WRITE SEQUENE SIGNLS FROM THE MSTER S T R T IDENTIFITION BYTE WITH R/W = DDRESS BYTE S T R T IDENTIFITION BYTE WITH R/W = 1 RED K K K S T O P SIGNL T SD SIGNLS FROM THE SLVE K K K FIRST RED DT BYTE LST RED DT BYTE FIGURE 3. RED SEQUENE FN7778 Rev 2. Page 16 of 2

17 Write Operation Write operation requires a STRT condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a STOP condition. fter each of the three bytes, the responds with an K. The data is transferred from I 2 block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29). Read Operation Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 3). The master initiates the operation issuing the following sequence: a STRT, the Identification byte with the R/W bit set to, an ddress Byte, a second STRT, and a second Identification byte with the R/W bit set to 1. fter each of the three bytes, the responds with an K; then the transmits Data Byte. The master terminates the read operation issuing a NK (K) and a STOP condition following the last bit of the last Data Byte (see Figure 3). pplications Information V LOGI Requirements It is recommended to keep V LOGI powered all the time during normal operation. In a case where turning V LOGI OFF is necessary, it is recommended to ground the V LOGI pin of the. Grounding the V LOGI pin or both V LOGI and V does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to.1µf as close to the V LOGI pin as possible. V Requirements and Placement It is recommended to put a 1µF capacitor in parallel with.1µf decoupling capacitor close to the V pin. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance make to a much higher impedance break within a short period of time (<1µs). There are several code transitions such as Fh to 1h, 1Fh to 2h,..., EFh to FFh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN7778 Rev 2. Page 17 of 2

18 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DTE REVISION HNGE 8/12/15 FN Updated Ordering Information table on page 3 hanged Products section to bout Intersil. Updated POD M1.118 from rev to rev 1. hanges since rev: Updated to new POD template. dded land pattern 7/29/11 FN On page 7, Wiper Response Time changed text in each option From: S rising edge to wiper new position, from 1% to 9% of final value. To: SL rising edge of the acknowledge bit after data byte to wiper new position from 1% to 9% of the final value. 7/28/11 dded Shutdown Function section and revised VLOGI Standby urrent and V Shutdown urrent limits on page 6. On page 7, split Wiper Response Time up into 3 separate conditions for each option (W, U, T). 12/15/1 FN7778. Initial Release bout Intersil Intersil orporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at opyright Intersil mericas LL ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN7778 Rev 2. Page 18 of 2

19 Package Outline Drawing M LED MINI SMLL OUTLINE PLSTI PKGE Rev 1, 4/12 3.± D DETIL "X" 1.1 MX SIDE VIEW ±.5 4.9±.15 5 PIN# 1 ID.95 REF 1 2 B.5 BS TOP VIEW GUGE PLNE.25 H.85±1.55 ±.15 DETIL "X" 3 ±3 SETING PLNE M -B D.1 ±.5.1 SIDE VIEW 1 (5.8) (4.4) (3.) NOTES: 1. Dimensions are in millimeters. (.5) Dimensioning and tolerancing conform to JEDE MO-187-B and MSEY14.5m Plastic or metal protrusions of.15mm max per side are not included. Plastic interlead protrusions of.15mm max per side are not included. (.29) 5. Dimensions are measured at Datum Plane "H". (1.4) TYPIL REOMMENDED LND PTTERN 6. Dimensions in ( ) are for reference only. FN7778 Rev 2. Page 19 of 2

20 Package Outline Drawing L1.2.1x1.6 1 LED ULTR THIN QUD FLT NO-LED PLSTI PKGE Rev 5, 3/1 B PIN 1 INDEX RE 1 PIN #1 ID MIN. 4.1 MIN. 4X.2 MIN X TOP VIEW 9 6X.5 BOTTOM VIEW 6 1X.4 1 X M M B (1 X.2) 1 (.5 MIN) PKGE OUTLINE MX..55 SEE DETIL "X" (1X.6) (.1 MIN.).1 SETING PLNE.8 (2.) (.8) SIDE VIEW (1.3). 125 REF (6X.5 ) (2.5) TYPIL REOMMENDED LND PTTERN -.5 DETIL "X" NOTES: Dimensioning and tolerancing conform to SME Y14.5M ll Dimensions are in millimeters. ngles are in degrees. Dimensions in ( ) for Reference Only. Unless otherwise specified, tolerance : Decimal ±.5 Lead width dimension applies to the metallized terminal and is measured between.15mm and.3mm from the terminal tip. Maximum package warpage is.5mm. Maximum allowable burrs is.76mm in all directions. Same as JEDE MO-255UBD except: No lead-pull-back, MIN. Package thickness =.45 not.5mm Lead Length dim. =.45mm max. not.42mm. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7778 Rev 2. Page 2 of 2