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2 AN-4153 Desigig Asyeric PWM Half-Bridge verers wih a Curre Doubler ad Sychroous Recifier usig FSFA-Series Fairchild Power Swiches (FPS TM roducio geeral, high-frequecy operaio allows he use of sallsized passive copoes i swich-ode power supplies (SMPS, hough i causes he swichig losses o icrease i a hard-swichig ode. To reduce swichig losses a high swichig frequecies, ay sof-swichig echiques have bee developed, icludig load-resoa ad zero-volagerasiio echiques. oad-resoa echiques use a resoa feaure of capaciors ad iducors durig he eire swichig period o vary he swichig frequecy, depedig o he ipu volage ad load curre. The chage of he swichig frequecy, i.e. pulse frequecy odulaio (PFM, akes i difficul o desig a SMPS icludig ipu filers. Sice here is o oupu iducor for filerig, he claped volage across oupu-recifyig diodes allows desigers o selec low-volage-raig diodes. However, he absece of he oupu iducor burdes he oupu capaciors whe he load curre icreases, akig load-resoa echiques usuiable for applicaios wih high oupu curre ad low oupu volage. O he oher had, zero-volage-rasiio echiques use a resoa feaure bewee parasiic copoes durig uro ad/or ur-off rasiios of he swichig period. Oe of he advaages of hese echiques is o use he parasiic copoes, such as he leakage iducace of he ai rasforer ad he oupu capaciaces of he swiches, so here is o eed o add ore exeral copoes o achieve sof swichig. addiio, hese echiques ake pulse-widh odulaio (PWM up wih fixed-swichig frequecy. Therefore, hese are easier o udersad, aalyze, ad desig ha load-resoa echiques. Due o is siple cofiguraio ad zero-volage swichig (ZS characerisic, a asyeric PWM half-bridge coverer is oe of he os popular opologies usig he zero-volage-rasiio echique. addiio, he ripple copoe of he oupu curre due o a oupu iducor becoes sall eough o be hadled by a appropriae oupu capacior. Beig easy o aalyze ad desig ad havig a oupu iducor, i is geerally used for applicaios wih high oupu curre ad low oupu volage (e.g. gae cosole power supplies. To hadle he large oupu curre, usig a sychroous recifier i he secodary side is popular o obai he coducio losses as ohic losses isead of diode losses. addiio, a curre doubler icreases he uilizaio of he ai rasforer whe he oupu curre is high. Fairchild s FSFA-series of gree power swiches (FPS iegraes a PWM coroller ad MOSFETs specifically desiged for asyeric-corolled opologies wih iial exeral copoes. pared wih discree-pwmcoroller-ad-mosfets soluios, FSFA-series swiches ca reduce oal cos, bill of aerials (BOM lis, size, ad weigh, while siulaeously icreasig efficiecy, produciviy, ad syse reliabiliy. This applicaio oe describes desig cosideraios of a asyeric PWM half-bridge coverer wih curre doubler ad sychroous recifier eployig FSFA-series swiches. icludes a sep-by-sep desig procedure as well as he geeral feaures ad operaioal priciples of he proposed opology. 1. Operaioal Priciples of a veioal Asyeric PWM Half-Bridge verer Figure 1 shows a coveioal asyeric PWM halfbridge coverer wih a ceer-apped rasforer. While he swich S 1 operaes wih a duy D, depedig o he ipu volage ad load curre, he swich S operaes wih 1-D. Durig DT S, i - is applied o he priary side of he rasforer ad he secodary diode D 1 urs o. The priary curre i pri icreases sice he ageizig curre i of he rasforer (o illusraed ad he oupu iducor curre i o icrease ogeher. Durig (1-DT S, is applied o he rasforer ad D urs o. The capacior C b is o oly a volage source durig (1-DT S bu also a DC-blockig capacior o preve rasforer sauraio. Whe he vol sec balace for he ageizig iducace of he rasforer is applied, he followig is obaied: 008 Fairchild Seicoducor rporaio Rev /9/08

3 v :1:1 D 1 O D loss1 T S DT S D loss T S (1-DT S S C b v T1 i D1 i o o v GS S 1 S S 1 i i pri S 1 i pri D Figure 1. veioal Asyeric PWM Half- Bridge verer wih a Ceer-Tapped Trasforer i D v T1 /( *( i - /( *(- ( i D (1 D D i (1 i D1 i D The vol sec balace for he oupu iducor yields: i O D O ( D ( where is he urs raio of he rasforer. biig Equaios (1 ad (, he oupu volage is obaied as: D(1 D O i (3 As ca be see i Figure (he gai curve accordig o he duy cycle usig Equaio (3 igorig urs raio, he gai is proporioal o he duy cycle up o 50% ad iversely proporioal o i above 50%. Because of his syery, he axiu duy cycle should be resriced up o 50% o regulae he oupu volage. The loss pars of he duy cycle by he leakage iducace are o cosidered i Equaio (3. Figure 3 shows he key wavefors of he coveioal asyeric PWM halfbridge coverer illusraed i Figure 1. Sice boh secodary recifyig diodes coduc, he volage across he priary side of he rasforer becoes zero durig D loss1 T S ad D loss T S. As a resul, he oupu volage is o as high as i Equaio (3, which is obaied by averagig, recifyig, ad scalig dow v T1 by. addiio, he applied volage o he priary side of he rasforer durig powerig odes ( 1 ~ ad 3 ~ 4 is slighly less ha i or due o he leakage iducace as show i Figure 3. Therefore, he oupu volage equaio could be obaied as: O Figure 3. Key Wavefors of he veioal Asyeric PWM Half-Bridge verer D(1 D i 4 O TS where O is he oupu load curre ad F is he forward volage drop of he secodary side-recifyig diodes. To desig he rasforer, he ageizig curre us be kow. Assue ha he ageizig iducace ad he oupu iducace are high eough for he curre ripple o he o be igored ad he leakage iducace is low eough for he duy loss pars o be egleced. The he curre wavefors are siplified as show i Figure 4. To ee he curre sec balace for C b, he posiive par of he priary curre i pri is equivale o he egaive par such ha he ageizig curre is obaied as: F (4 Figure. Noralized Gai Curve Figure 4. Siplified Curre Wavefors i he Priary Side 008 Fairchild Seicoducor rporaio Rev /9/08

4 O O D O (1 D (1 D where is he DC copoe of i. As ca be see i Equaio (5, could be zero whe he duy cycle is 50%. Geerally i has a DC offse, so he core sauraio has o be ake io accou whe he rasforer is desiged.. Operaioal Priciples of a Asyeric PWM Half-Bridge verer wih Curre Doubler ad Sychroous Recifier For low-oupu-volage ad high-oupu-curre applicaios, he curre doubler is widely used. Figure 5 illusraes he asyeric PWM half-bridge coverer wih he curre doubler o he secodary side. The secodary widig is a sigle-eded cofiguraio, while he oupu iducors are divided io wo saller iducors. To icrease he oal efficiecy, a sychroous recifier (SR coprised of MOSFETs wih low R ds(o is used. The curre doubler has several advaages copared o he coveioal ceerapped cofiguraio. Firs, he DC copoe of he ageizig curre is lower ha or equal o ha of he ceer-apped cofiguraio, which akes i possible o use he saller core for he rasforer. The aou of he ageizig curre is he sae as ha of he ceer-apped cofiguraio whe each oupu iducor carries half he load curre. The aou of he ageizig curre is reduced whe he oupu iducors carry he load curre uevely. Secod, he roo-ea-square (rs value of he secodary widig curre is saller ha ha of he ceerapped cofiguraio, sice alos half of he load curre flows hrough each oupu iducor. As a resul, he low curre desiy for he secodary widig could be used wih he sae core ad he sae gauge of wire. Third, he widig iself is easier ha he ceer-apped cofiguraio. This is oable especially for uli-oupu applicaios because of he liiaio of he pi uber of he bobbi of he rasforer. Fourh, he gae sigals for SR are obaied easily ad effecively fro he oupu iducors, as show i Figure 6(b. A appropriae gae volage (e.g., bewee 10 ad 0 could be easily obaied fro he oupu iducors due o a eough uber of urs, while he secodary side uber of urs of he rasforer is oly a few. Addiioally, he separaed oupu iducors reduce he burde of he cos of he bigger core. These advaages ake he curre doubler oe of he os popular opologies for high-oupu-curre applicaios. (5.1. Operaioal Priciples Figure 7 shows he ode aalysis for he asyeric PWM half-bridge coverer wih he curre doubler ad correspodig key wavefors. Assue ZS is achieved sufficiely wih very shor duraio. The ZS odes ca be igored i he ode aalysis. The ZS operaio is discussed i deail i he ex secio. Oher assupios are: (1 The DC-blockig capacior C b is large eough o eglec he volage ripple o i, ad ( All elees i he circui are ideal. Figure 5. Asyeric PWM Half-Bridge verer wih he Curre Doubler Figure 6. Mehods for Producig he Gae Driver Sigal Usig; (a he Trasforer; (b he Oupu ducor 008 Fairchild Seicoducor rporaio Rev /9/08 3

5 e s sar wih Mode, a powerig ode. Whe S 1 urs o, i - is applied o he priary side of he rasforer. The ageizig curre i icreases wih he slope of ( i - /. The slope of he curre of O1 is deeried by subracig he oupu volage fro ( i - / because SR urs off. O he oher had, he curre of O decreases wih he slope of O / O, which is free-wheelig hrough SR 1. While wo oupu iducors share he load curre, SR 1 carries he whole load curre. The secodary widig of he rasforer hadles oly i so ha i / is he refleced curre o he priary side of he rasforer ad i is superiposed o he ageizig curre, which cosiues he priary curre i pri. fac, v T is slighly lower ha he value illusraed i Figure 7 due o leakage iducace (see Chaper 1. is igored i his secio o siplify aalysis. Whe S 1 urs off, Mode 3 begis. As he oupu capaciace of S is discharged, v T1 decreases. becoes zero whe he oupu capaciace volage of S equals. A his ie, he body diode of SR urs o sice is reverse-biased volage is eliiaed. Subsequely, boh SRs ur o ogeher durig his ode. The body diode of S urs o afer he S oupu capaciace is wholly discharged ad ha of S 1 is eirely charged. Sice boh SRs ur o, i ad i O are free-wheelig wih he slope of O / O1 ad O / O, respecively, ad v T1 ad v T are zero, is applied oly o he leakage iducace, causig he priary curre s polariy o chage rapidly. Whe S urs o afer he S body diode coducs, he S ZS codiio is achieved. The duraio of his ode is obaied as: D loss O (6 D T i S Mode 4, aoher powerig ode, sars wih he ed of couaio bewee SRs. The applied volage o he priary side of he rasforer is so ha he ageizig curre decreases wih he slope of / ad :1 S SR i o D loss1 T S DT S D loss T S (1-DT S GS S (a Mode 1 ( 0 ~ 1 O :1 i pri i ( i - / - / S SR i o ( i - / v T (b Mode ( 1 ~ O - / :1 - O / O1 i o i S SR o i o1 (( i - /- O / O1 ( /- O / O - O / O O (c Mode 3 ( ~ 3 i i SR :1 di o1 di o di o1 di o S SR i o (d Mode 4 ( 3 ~ 4 O (e Key wavefors Figure 7. Mode Aalysis ad Wavefors for Asyeric PWM Half-Bridge verer wih he Curre Doubler 008 Fairchild Seicoducor rporaio Rev /9/08 4

6 he slope of i O is ( /- O / O. The oher iducor curre is free-wheelig hrough SR. As ca be see i Figure 7, he large ripple o each oupu iducor is cacelled because of he ou-of-phase. Therefore, wo saller iducors ca be used i he curre doubler cofiguraios copared wih he ceer-apped or bridge recifyig cofiguraios. Whe S urs off, Mode 1 sars as aoher regeeraig ode. The operaig priciple of Mode 1 is alos he sae as Mode 3, excep for a ZS codiio. Mode 1, v T1 becoes zero a he isa whe he oupu capaciace volage of S 1 is equivale o i -. Before his isa, he load curre o he oupu iducor O is refleced o he priary side of he rasforer ad helps o ee he ZS codiio of he swiches. The eergy sored i he leakage iducace oly has o discharge ad charge he oupu capaciace of he swiches afer his isa. Therefore, he ZS codiio for S 1 is harder ha S sice i - is higher ha i geeral. all oher respecs, Mode 1 ca be aalyzed i he sae way as Mode 3. The duraio of Mode 1 is obaied as: D O loss 1 (1 D i T (7 S The deailed oupu volage is calculaed wih Equaios (6 ad (7 as: O D(1 D i O T S where SR is he volage across he MOSFET as a SR durig powerig odes. is siilar o Equaio (4 excep for he urs raio, which is half ha of he coveioal coverer. By odifyig Equaio (5, he DC ad ripple copoes of i are obaied as: Δi SR (8 O ( D D (9 (1 D i ( DTS Dloss1 TS (10 where ad O are he DC copoes of he oupu iducor curres... ZS diios he previous secio, he duraio for ZS operaio was oied o siplify ode aalysis. More deailed aalysis for ZS operaio is give i his secio o discover a exac ZS codiio for each swich. Figure 8 shows he deailed odes for Mode 1. Fro 0, he priary curre sars o charge ad discharge he oupu capaciace of he swiches. Before he drai volage of S 1, v D reaches o i -, he doed erial of he rasforer is egaive so ha SR 1 is sill reverse-biased. Therefore, o oly he eergy i he leakage iducace, bu also he eergy of he load curre, helps S 1 be discharged fro i o i -. Afer v D is reduced ore ha i -, he doed erial of he rasforer chages is polariy, which allows he body diode of SR 1 o ur o. Therefore, he ageizig iducace is shor-circuied so ha he swiches are charged ad discharged by he eergy i he leakage iducace oly fro a. Fially, v D is fully discharged a b, so he priary curre flows hrough he body diode of S 1, as ca be see i Figure 8(c. Afer c, he priary curre flows hrough boh he chael ad he body diode sice he gae sigal of S 1 is applied. Mode begis wih he ed of he couaio bewee SRs fro 1. For he ZS operaio of S 1 here are hree codiios i Figure 8, as follows: (1 The eergy i he leakage iducace should be sufficie o discharge S 1 fro i - o zero ad charge S fro o i. ( The isa b us be earlier ha whe he priary curre chages is polariy. Oherwise, he drai volages of S 1 ad S are agai charged ad discharged, respecively. (3 The gae sigal of S 1 us be applied before he priary curre chages is polariy. Figure 9 shows he deailed odes i Mode 3. While he deailed ode aalysis is siilar o he case of Figure 8, hree codiios for he ZS operaio of S are differe fro hose of Figure 8: (1' Sice he polariy of he rasforer erials chages whe v DS reaches, he porio of dischargig S by he load curre, ~ d, is uch larger ha 0 ~ a i Figure 8. Therefore, he reaiig porio of dischargig S by he eergy i he leakage iducace oly is shoreed; he ZS of S is easier o achieve copared wih he ZS of S 1. Therefore, he eergy i he leakage iducace should be sufficie o discharge S fro o zero ad charge S 1 fro i - o i. (' The couaio bewee SRs begis wih he chage of polariy of he rasforer erials so ha i akes loger fro e o he isa whe he curres i SRs are equal. addiio, he couaio slope is ore sluggish ha he case i Figure 8, sice he applied volage o he leakage iducace is reduced o fro i -. (3' The gae sigal of S us be applied before he priary curre chages is polariy if diio (3 is saisfied due o he sae dead ie ad he reaso eioed i (. Wih respec o boh eergy ((1 ad (1 ad iig (( & 3 ad ( & 3, he ZS codiio of S 1 is ore difficul o achieve ha ha of S. Therefore, he ZS codiio should be cosidered wih S 1 oly. geeral, he codiio for iig is easily saisfied if he codiio for eergy is 008 Fairchild Seicoducor rporaio Rev /9/08 5

7 saisfied. Therefore, he required leakage iducace for he ZS of boh swiches a special load codiio ca be calculaed as: COSS > D(1 D i TS ( [(1 D ] O, ar i D O, ar (11 where C OSS is he oupu capaciace of he swich ad O,ar is he arge load codiio where a desiger was he syse o operae i ZS codiio wih he leakage iducace. A easy way o achieve ZS for boh swiches eve a ligh load codiios is o icrease. However, he icreased icreases duy loss pars by reducig he slope of he priary curre i Modes 1 ad 3. This resuls i he icrease of coducio loss for he reduced effecive duy cycle. Therefore, i is o recoeded as a ehod o icrease for ZS a very ligh load. Accordig o Equaio (9, as he load curre decreases, he DC copoe of he ageizig curre decreases as well. f he DC copoe of i is less ha half he ripple copoe of i, he ZS operaio is perfored by he ageizig iducace wih he leakage iducace. Equaio (11, igorig he secod er i he deoiaor, :1 S SR i o O D loss1 T S (a Mode 1_1 ( 0 ~ a (1-DT S DT S :1 S S SR v D i - v DS i o i SR i O (b Mode 1_ ( a ~ b :1 S SR i o ( i - / O i pri (c Mode 1_3 ( b ~ c 0 a b c 1 :1 (e Key wavefors S SR i o O (d Mode 1_4 ( c ~ 1 Figure 8. Deailed Mode Aalysis Durig Mode Fairchild Seicoducor rporaio Rev /9/08 6

8 rearragee for yields: < C D(1 D OSS i (1 D T i S D, O ar (1 To obai appropriae ad usig Equaios (11 ad (1, ieraios are ecessary. A exaple of his is give i he ex secio..3. Sychroous Recifier is ore profiable ha he coducio losses o he secodary recifyig sage are coposed of ohic losses isead of diode losses whe he oupu curre is high. Sice os of load curre flow hrough he chael, coducio losses ca be reduced draaically if sychroous MOSFETs wih very low R ds(o (less ha several Ω ur o ad off appropriaely. buck-derived opologies such as forward, half-bridge, ad full-bridge coverers, he gae sigal for SR is easily obaied fro he :1 S SR i o O D loss T S (a Mode 3_1 ( ~ d DT S (1-DT S :1 S S SR v DS i - v D i o i i SR O (b Mode 3_ ( d ~ e :1 S SR i pri i o - / O (c Mode 3_3 ( e ~ f d e f 3 :1 (e Key wavefors S SR i o O (d Mode 3_4 ( f ~ 3 Figure 9. Deailed Mode Aalysis Durig Mode Fairchild Seicoducor rporaio Rev /9/08 7

9 ai rasforer (as show i Figure 6(a. Ulike flyback or C coverers, here is o eed o add ay oher special fucios, excep for he drivig circui. Ease of cosrucio of he SR driver is aoher reaso o use he half-bridge opology for high-oupu-load-curre applicaios. Moreover, whe usig a curre doubler, i is ore efficie o ge he gae sigal fro he oupu iducors ha fro he ai rasforer (as show i Figure 6(b. Figure 10 illusraes he SR gae-sigal wavefors fro he ai rasforer ad he oupu iducors. is difficul o ue up he urs raio a ad b (where a s / 1 ad b s / o ake he sufficie gae volage (as show i Figure 10(a. This is because boh posiive ad egaive pars are depede o oly o he urs raios a ad b bu also o. Addiioally, he power loss by he egaive par of he gae sigal is deeried by he urs raio,, ad i. O he oher had, he power loss by he egaive par of he gae sigal does o deped o he load codiio (as show i Figure 10(b, where c 3 / 1 ad d 4 /. addiio, durig he duy loss par, D loss1 T S ad D loss T S, he gae sigals chage heir polariy o a egaive value so ha he SRs ur off rapidly ad defiiely. This helps o reduce he ur-off loss of he sychroous MOSFETs. v T v gae_ v gae_sr v gae_ v gae_sr Dloss1TS ( i- / ( i- // a -( i- // b - / - // a // b Dloss1TS (( i- /- O/ c - O/ d DlossTS DlossTS (a - O/ c ( /- O/ d (b Sae shape as v excep for c Sae shape as v O excep for d Figure 10. Gae Sigals for Sychroous Recifier; (a Trasforer upled; (b Oupu ducor upled 3. Desig Procedure ad Exaple his chaper, a desig procedure is show usig he desig referece illusraed i Figure 11. The arge syse for his exaple is a gae cosole power-supply ui wih 1 of oupu volage ad 30 A of oupu load curre. To hadle he large oupu-load curre, he curre doubler wih he sychroous recifier discussed i he previous chaper is used. Sice he ipu coes fro a power facor correcio (PFC circui, he ipu-volage rage is o wide. [STEP 1] Syse Specificaios The firs sep i desigig is o defie he syse specificaios. Geerally, a PFC circui is used for ediuor high-power applicaios such as CD/PDP T syses, gae cosole power supplies, ad bea projecors o ee ieraioal haroic regulaios. Thus, he ipu volage rage for he ai power sage (i.e. he oupu volage of PFC sage is alos fixed (e.g., 370~410 dc. However, he ipu volage rage ay be wideed o ee special requirees. his chaper, he arge specificaios are: Noial ipu volage: 390 dc pu volage rage: 370~410 dc Oupu volage: 1 Oupu curre: 30 A Swichig frequecy: 100 khz [STEP ] Turs Raio ad Duy Cycle The oupu volage equaio (Equaio 8 is used o deerie urs raio. However, he oupu volage equaio coais he leakage ad ageizig iducace, which are o ye deeried. Therefore, a desiger should ake assupios for he followig: SR cosiderig R ds(o of used MOSFETs as a SR; α, he raio bewee ad ; The leakage iducace ha will be chaged laer by ieraios of Equaios (11 ad (1; The oial duy cycle a he oial ipu volage. Accordig o Equaio (8, he urs raio is obaied as: O D (1 D i, ( D (1 D i, 4( O SR αts (13 ( O SR α where i, ad D are he oial ipu volage ad he oial duy cycle a i,, respecively. For urs raio, he duy cycle a a ipu volage ad a load curre is calculaed as: D ( 4 O αi SR O its ( Fairchild Seicoducor rporaio Rev /9/08 8

10 C10 FUSE1 R105 cc R107 Cvcc #7 -cc #3 Dvcc Rvcc #1 D #9 H-cc Np Ns N1 Ddr1 Rdr1 Qdr1 Rs1 0 Q101 Cs1 u o 1/30A N4 i PFC oupu Clik C107 Cfb U- RT # FB rol C Chvcc #10 CTR N Rdr Ddr Qdr Q10 Rs Cs u1 01 N3 R10 #4 CS C103 #5 SG U1 FSFA100 #6 PG R101 Figure 11. Referece Desig Scheaic Desig Exaple For he exaple, he followig values are assued: SR 0.3 α is 0.95 The iiial leakage iducace is 0 µh. This ay be icreased afer checkig he ZS codiio. Takig he core size for 360W io accou, if is less ha his value, he produciviy is o good. The oial duy cycle a 390 dc is 0.4. Usig hese values, he urs raio is obaied by Equaio (13 as: μ ( ( μ ( yieldig a urs raio is. The oial duy cycle a he oial ipu volage is recalculaed by Equaio (14 as: D ( μ μ [STEP 3] Mageizig ad eakage ducace Usig he urs raio obaied i Sep, he ZS codiio could be checked wih Equaios (11 ad (1. Desig Exaple This exaple is desiged o achieve he ZS operaio fro full- o 30%-load codiio usig he leakage iducace ad he ageizig iducace. The duy cycle a 30% load codiio ad he axiu ipu volage is obaied by Equaio (14 as: ( μ μ Sice C OSS of he FSFA100 MOSFETs is 150 pf, he required leakage iducace is obaied wih as: C [(1 D ] OSS i > D(1 D, D i TS O ar O, ar 1 ( 150 p [ ( ] ( μ 9 400μ (400μ 0μ 400μ 0μ 1.0μH. The required leakage iducace is 1.0 µh, which is oo sall o corol i a ass producio. f he obaied value is larger ha he assued value, he obaied value is used, ad he SMPS desiger us repea Sep o check if he urs raio is sill valid. However, i his desig exaple, he desiger chooses he iiial value for produciviy, ad here is o ieraio eeded. Figure 1. Priary Curre Wavefor 008 Fairchild Seicoducor rporaio Rev /9/08 9

11 The ageizig iducace ca be deeried usig Equaio (1 as: D(1 D i TS < C D OSS O, ar (1 D i ( μ 150 p ( μ 638μH. Therefore, is seleced as 600 µh. [STEP 4] Trasforer Usig Equaios (9 ad (10, he peak ageizig curre is obaied as: Δi O (1 D ( DT S D loss D (1 D 1TS ( i (15 The axiu value of he peak ageizig curre occurs whe each oupu iducor carries half he load curre for he wors case ad he duy cycle is zero durig sarup or rasie isa. Therefore, he axiu i is: i ax O (16 The iiu uber of urs for he rasforer priary side is give as: ax i i N P (17 A B e ax where A e is he effecive cross-secioal area of he used core i, ad B ax is he axiu flux desiy i Tesla. B ax 0.~0.5 T is recoeded if here is o referece daa. The uber of urs for he rasforer secodary side is obaied as: NP NS (18 where N P is larger ha N i P i Equaio (17. The diaeer of he wire is seleced based o he curre desiy, whose rage is geerally 4~10 A/. is recoeded o selec he curre desiy as low as possible o reduce coducio losses o he wire. However, ry o reduce he widig layers a he sae ie. The ore widig layers, he ore circulaig curre caused by he proxiiy effec. Soeies ryig o reduce coducio losses by icreasig he wire diaeer akes coducio losses icrease by icreasig he circulaig curre. addiio, i is beer o choose a wire wih uli-srads of hier wire, such as iz wire, o iiize he ski effec. Whe he oupu iducor curre ripple is igored, Figure 1 shows he priary-curre wavefor. The rs value of his wavefor is give as: rs P i P1 P P3 ( P1 P1 P P ( P3 P3P4 P4 D (1 D ( Δi (0 Δi (1 O Δi ( O Δi P4 (3 where ad Δi are defied i Equaios (9 ad (10. For he secodary-side widig, half he load curre is he rs value whe i is assued ha each oupu iducor carries he load curre evely ad he ripple o he oupu iducor is sall eough o be igored. Desig Exaple Whe he duy cycle is zero, he axiu i is obaied as: O 30 ax i.31a. The give core is EER404 (A e 158. The iiu urs uber for he rasforer priary side is calculaed as: N i P ax i A B e ax 600μ μ 0.3 Whe N P is seleced as 39, he secodary urs uber is obaied as 6. Use Equaios (19-(3 o ge he rs value of he rasforer priary side curre. Assue each oupu iducor carries he oupu load curre evely a he oial codiio (D P A P A P A P A 008 Fairchild Seicoducor rporaio Rev /9/08 10

12 Therefore, he rs value of he rasforer priary side curre is obaied by Equaio (19 as: rs P i ( (( A ( 1.15(.51 (.51 3 ( The rs value of he rasforer secodary side curre is half he load curre, so i rs S 15 A. Sice he diaeer of he wire becoes oo hi, i is o easy o wid 39 urs for he priary side of he rasforer i wo layers. Choose he bigges wire ha ca be woud 13 urs i oe layer of he bobbi for EER404. Due o cosideraio of he ski effec, iz wire of 100 srads wih AWG38 (Aerica wire gauge is seleced as he priary wire. his case, he curre desiy is aroud.9 A/. For he secodary side, 50-srad iz wire wih AWG36 is chose where he curre desiy is aroud 4.7 A/. [STEP 5] Oupu ducace The oupu iducor curre ripple is give as: ( O SR (1 D Dloss1 TS Δ i (4 ( O1 O SR ( D Dloss TS Δ io (5 O geeral, he curre ripple o he oupu iducor is se o 10-0% of he raed oupu load curre. Desig Exaple he desig exaple, he ripple o each oupu iducor is seleced o be less ha 0% of he raed oupu load curre. The iducaces are calculaed as: 01 0 ( O SR (1 D Dloss 1 TS Δi (1 0.3( μ 13.μH 6 ( O SR ( D Dloss TS ΔiO. (1 0.3( μ 9.4μH 6 To icrease produciviy, boh oupu iducors are seleced as he sae value, 15µH. [STEP 6] Operaig frequecy Figure 11, he operaig frequecy f S is obaied by usig he followig equaio whe FSFA-series is used. 7kΩ f S 100 [ khz] (6 R 105 Desig Exaple For he desig exaple, he frequecy seig resisor R 105 is seleced as 7 kω for 100 khz operaio. [STEP 7] DC-Blockig Capaciace has bee assued ha he DC-blockig capacior is large eough o eglec he volage ripple o i. However, oo large a DC-blockig capacior leads o slow dyaic respose. Therefore, i is recoeded o ake he volage ripple o he DC-blockig capacior aroud 10% of he ipu volage. The volage ripple o he DC-blockig capacior is obaied as: Dloss1TS P1 DlossTS P Δ v 1 ( D Dloss1 TS ( P1 P (7 Desig Exaple Whe he volage ripple o he capacior is 30, he Dlockig capaciace is calculaed usig Equaio (7 as: C 10 Dloss 1T S P1 DlossTS P 1 Δv C10 ( D Dloss 1 TS ( P1 P μ μ ( μ ( F Therefore, 0 F is seleced as he DC-blockig capacior. [STEP 8] Sesig Resisor The pulse-by-pulse curre lii of he FSFA-series swiches ca be adjused by chagig R 101 i Figure 11. is deeried by he peak of he priary curre obaied usig Equaio (1 whe he ipu volage is axiized. Due o he ripple curre of he ageizig iducace, he axiu peak of he priary curre happes whe he ipu volage is axiized. Desig Exaple iuig wih he exaple, calculae he duy cycle a he axiu ipu volage ad full-load codiios usig Equaio ( Fairchild Seicoducor rporaio Rev /9/08 11

13 410,100% ( O 4 αi SR O its ( μ μ μ 60 μ The, he peak of he priary curre is obaied cobiig Equaios (7, (9, (10, ad (1 as: P Δi O (1 D D 1 O (1 D i DTS (1 D i ( μ ( μ ( μ 0μ 3.7A Sice he ieral hreshold volage for he pulse-by-pulse curre lii is -0.58, 0.1 Ω is seleced as he sesig resisor, R 101. [STEP 9] Sychroous Recifier The volage sresses o he SRs are calculaed as: Di 1 (8 SR (1 D i SR (9 For widigs o drive he gae of he SRs, durig powerig odes he volages across he oupu iducors are: (1 D i O (30 D Desig Exaple i O O (31 siderig he wors case for each SR, he volage sresses o he are: D i Q 101 (1 D 3 ( i Q A N-chael power MOSFET wih 8Ω of R ds(o ad 100 of he volage raig, HUF7565G3, is seleced for boh SRs wih cosideraio of he volage rigig ad overshoo. The volages across he oupu iducors durig powerig odes are: ( D@ 370,100% 370 ( i 01 O ax ( O i i 0 O 1 ax D@ 370,100% O 1 14 To proec he SRs, he gae sigal has o be resriced ±0. The urs raios bewee he oupu iducors ad he widigs for he gae drivers are: N N N N [STEP 10] Exeral Sof Sar A sarup, he duy cycle sars icreasig slowly o esablish he correc workig codiios for rasforers, iducors, ad capaciors. The volage o he oupu capaciors is progressively icreased o soohly esablish he required oupu volage. For he FSFA-series, he sofsar ie is ierally ipleeed for 15s whe he operaig frequecy is se o 100 khz. addiio, o help he sof-sar operaio, a capacior ad a resisor are coeced o he R T pi exerally, as show i Figure 11. Before he power supply is powered o, he capacior C 107 reais fully discharged. Afer power-o, C 107 becoes charged gradually by he curre hrough he R T pi, which deeries he operaig frequecy. The curre hrough he R T pi is iversely proporioal o he oal ipedace of he coeced resisors. The oal ipedace durig sarup is lower ha ha of he oral operaio because R 107 is added o R 105 i parallel, which eas he operaig frequecy decreases coiuously fro higher o oial. Eveually, C 107 is fully charged o he R T pi volage ad he operaig frequecy is deeried by R 105 oly. Durig C 107 chargig ie, he operaig frequecy is higher ha durig oral operaio. asyeric PWM halfbridge coverers, a swichig period coais powerig ad couaio periods. The eergy cao be rasferred o he oupu side durig he couaio period. Sice he DC 008 Fairchild Seicoducor rporaio Rev /9/08 1

14 lik volage applied o he D pi ad he leakage iducace of he ai rasforer are fixed, he powerig period over he swichig period is shorer i high swichig frequecies. As C 107 is charged, he swichig frequecy decreases so ha he powerig period over he swichig period icreases. is helpful o sar SMPS wih he ieral sof-sar ie ogeher. Desig Exaple 4. Desig Suary Figures 13 ad 14 show he full scheaic of he referece desig ad is rasforer cofiguraio. Table 1 shows he deailed wire iforaio of he rasforer. The elecrical feaures of he rasforer are described i Table. he desig exaple,. µf ad 1 kω are seleced as C 107 ad R 107, respecively. Figure 13. Full Scheaic wih poes alues of he Referece Desig N P N S Figure 14. Trasforer srucio of he Referece Desig 008 Fairchild Seicoducor rporaio Rev /9/08 13

15 Table 1. Trasforer Widig Specificaios Pi No. Widig (sar ed Wire Turs Widig Mehod sulaio Tape (5 u 1T N P 1 8 iz wire (AWG srads (1 39 T Soleoid sulaio Tape (5 u 1T 1 N S 16 9 iz wire (AWG36 50 srads 6 T Soleoid NOTE: 1. sulaio ape (5 µ, 1T each should be isered bewee he layers. Table. Trasforer Elecrical Characerisics Mageizig ducace ( 1-8 Pi Spec. Reark 600 µh (ypical (600 µh ± 5% eakage ducace ( µh ± 10% 100 khz, 1 All oher pis ope 100 khz, 1 All oher pis shored 5. Experieal Resuls Figures 15 ad 16 show he experieal wavefors of he coverer desiged i he previous chaper a he oial ipu ad he full-load codiio. The gae sigal of S 1, he priary- ad secodary-side volages across he ai rasforer, ad he priary curre are show i Figure 15. These wavefors are cosise wih he heoreical aalysis, icludig he ZS operaio. The oupu iducor curres ad he SRs curres are show i Figure 16. The oupu iducor curres are ubalaced due o he duy cycle ad he parasiic copoes, which eas he averaged ageizig curre is saller ha ha of he ceer-apped cofiguraio. [1] Figure 17 shows he widig volages for he gae driver circuis of SRs a he full-load codiio. The upper wavefors are for he iducor couplig illusraed i Figure 6(b, while he lower oes are for he rasforer couplig illusraed i Figure 6(a. As ca be see i Figure 17, sice he widig volage decreases o he egaive a he ur-off rasiio i he upper wavefors, he SRs are ured off ore rapidly ad defiiely ha i he rasforer couplig case. Figure 17, he saller egaive pars i he iducor couplig case are show copared o he rasforer couplig case. The saller egaive pars allow he power losses o he gae driver circui for SRs o be reduced. The ZS operaios a various load codiios are show i Figure 18. The drai volage ad he gae sigal of he lower side swich are displayed. As desiged i he previous chaper, he coverer shows ZS operaio dows o 30% load codiio. The efficiecy of he coverer is show i Figure 19. The easured efficiecies are 93.7%, 94.6%, ad 93.1% a 0%, 50%, ad 100% of he raed load codiio, respecively. shows a argial perforace so ha he 85 PUS progra ca be achieved wih well-desiged PFC ad DC-DC sages. Figure 15. Experieal Wavefors Figure 16. Wavefors for he Secodary Side 008 Fairchild Seicoducor rporaio Rev /9/08 14

16 96 Efficiecy [%] % 94.6% 93.1% oad [%] Figure 19. Measured Efficiecy of he Desiged verer Figure 17. Gae Sigals for SR; Upper Wavefors Use Oupu ducors; ower Wavefors Use he Trasforer v gs_ (0/div. v ds_ (00/div. 6. Refereces [1] Hog Mao, Sogqua Deg, Yagyag we, ad ssa Baarseh, Uified Seady-Sae Model ad DC Aalysis of Half-Bridge DC-DC verers wih Curre Doubler Recifier, APEC '04. Nieeeh Aual EEE, ol., 004, pp [] Yu-Chieh Hug, Fu-Sa Shyu, Chih Jug i, ad Ye- Shi ai, Desig ad pleeaio of Syerical Half- Bridge DC-DC verer, The Fifh eraioal ferece o PEDS 003. ol. 1, Nov. 003 pp [3] Paov, Y. ad Jovaovic, M.M., Desig ad Perforace Evaluaio of ow-olage / High-Curre DC/DC O-board Modules, EEE Trasacios o Power Elecroics, ol. 16, ssue 1, Ja. 001 pp (a ZS fail begis v gs_ (0/div. v ds_ (00/div. (b Figure 18. ZS erificaio; (a a 40% oad; (b a 30% oad 008 Fairchild Seicoducor rporaio Rev /9/08 15

17 DSCAMER FARCHD SEMCONDUCTOR RESERES THE RGHT TO MAKE CHANGES WTHOUT FURTHER NOTCE TO ANY PRODUCTS HEREN TO MPROE REABTY, FUNCTON, OR DESGN. FARCHD DOES NOT ASSUME ANY ABTY ARSNG OUT OF THE APPCATON OR USE OF ANY PRODUCT OR CRCUT DESCRBED HEREN; NETHER DOES T CONEY ANY CENSE UNDER TS PATENT RGHTS, NOR THE RGHTS OF OTHERS. FE SUPPORT POCY FARCHD S PRODUCTS ARE NOT AUTHORZED FOR USE AS CRTCA COMPONENTS N FE SUPPORT DECES OR SYSTEMS WTHOUT THE EXPRESS WRTTEN APPROA OF THE PRESDENT OF FARCHD SEMCONDUCTOR CORPORATON. As used herei: 1. ife suppor devices or syses are devices or syses which, (a are ieded for surgical ipla io he body, or (b suppor or susai life, or (c whose failure o perfor whe properly used i accordace wih isrucios for use provided i he labelig, ca be reasoably expeced o resul i sigifica ijury o he user.. A criical copoe is ay copoe of a life suppor device or syse whose failure o perfor ca be reasoably expeced o cause he failure of he life suppor device or syse, or o affec is safey or effeciveess. 008 Fairchild Seicoducor rporaio Rev /9/08 16

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